1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
11 imply SPL_SEPARATE_BSS
14 bool "Enable support for CRC32 instruction"
18 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
19 This is faster than software crc32 calculation. This instruction may
20 not be present on all ARMv8.0, but is always present on ARMv8.1 and
23 config COUNTER_FREQUENCY
24 int "Timer clock frequency"
25 depends on ARM64 || CPU_V7A
26 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
27 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
28 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
29 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
30 default 100000000 if ARCH_ZYNQMP
33 For platforms with ARMv8-A and ARMv7-A which features a system
34 counter, those platforms needs software to program the counter
35 frequency. Setup time clock frequency for certain platform.
36 0 means no need to configure the system counter frequency.
37 For platforms needs the frequency set in U-Boot with a
38 pre-defined value, should have the macro defined as a non-zero value.
40 config POSITION_INDEPENDENT
41 bool "Generate position-independent pre-relocation code"
42 depends on ARM64 || CPU_V7A
44 U-Boot expects to be linked to a specific hard-coded address, and to
45 be loaded to and run from that address. This option lifts that
46 restriction, thus allowing the code to be loaded to and executed from
47 almost any 4K aligned address. This logic relies on the relocation
48 information that is embedded in the binary to support U-Boot
49 relocating itself to the top-of-RAM later during execution.
51 config INIT_SP_RELATIVE
52 bool "Specify the early stack pointer relative to the .bss section"
54 default n if ARCH_QEMU
55 default y if POSITION_INDEPENDENT
57 U-Boot typically uses a hard-coded value for the stack pointer
58 before relocation. Enable this option to instead calculate the
59 initial SP at run-time. This is useful to avoid hard-coding addresses
60 into U-Boot, so that it can be loaded and executed at arbitrary
61 addresses and thus avoid using arbitrary addresses at runtime.
63 If this option is enabled, the early stack pointer is set to
64 &_bss_start with a offset value added. The offset is specified by
65 SYS_INIT_SP_BSS_OFFSET.
67 config SYS_INIT_SP_BSS_OFFSET
68 int "Early stack offset from the .bss base address"
70 depends on INIT_SP_RELATIVE
73 This option's value is the offset added to &_bss_start in order to
74 calculate the stack pointer. This offset should be large enough so
75 that the early malloc region, global data (gd), and early stack usage
76 do not overlap any appended DTB.
78 config SPL_SYS_NO_VECTOR_TABLE
82 config LINUX_KERNEL_IMAGE_HEADER
86 Place a Linux kernel image header at the start of the U-Boot binary.
87 The format of the header is described in the Linux kernel source at
88 Documentation/arm64/booting.txt. This feature is useful since the
89 image header reports the amount of memory (BSS and similar) that
90 U-Boot needs to use, but which isn't part of the binary.
92 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
93 depends on LINUX_KERNEL_IMAGE_HEADER
96 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
97 TEXT_OFFSET value written to the Linux kernel image header.
109 ARM GICV3 Interrupt translation service (ITS).
110 Basic support for programming locality specific peripheral
111 interrupts (LPI) configuration tables and enable LPI tables.
112 LPI configuration table can be used by u-boot or Linux.
113 ARM GICV3 has limitation, once the LPI table is enabled, LPI
114 configuration table can not be re-programmed, unless GICV3 reset.
120 config DMA_ADDR_T_64BIT
130 config GPIO_EXTRA_HEADER
133 # Used for compatibility with asm files copied from the kernel
134 config ARM_ASM_UNIFIED
138 # Used for compatibility with asm files copied from the kernel
142 config SYS_ICACHE_OFF
143 bool "Do not enable icache"
145 Do not enable instruction cache in U-Boot.
147 config SPL_SYS_ICACHE_OFF
148 bool "Do not enable icache in SPL"
150 default SYS_ICACHE_OFF
152 Do not enable instruction cache in SPL.
154 config SYS_DCACHE_OFF
155 bool "Do not enable dcache"
157 Do not enable data cache in U-Boot.
159 config SPL_SYS_DCACHE_OFF
160 bool "Do not enable dcache in SPL"
162 default SYS_DCACHE_OFF
164 Do not enable data cache in SPL.
166 config SYS_ARM_CACHE_CP15
167 bool "CP15 based cache enabling support"
169 Select this if your processor suports enabling caches by using
173 bool "MMU-based Paged Memory Management Support"
174 select SYS_ARM_CACHE_CP15
176 Select if you want MMU-based virtualised addressing space
177 support via paged memory management.
180 bool 'Use the ARM v7 PMSA Compliant MPU'
182 Some ARM systems without an MMU have instead a Memory Protection
183 Unit (MPU) that defines the type and permissions for regions of
185 If your CPU has an MPU then you should choose 'y' here unless you
186 know that you do not want to use the MPU.
188 # If set, the workarounds for these ARM errata are applied early during U-Boot
189 # startup. Note that in general these options force the workarounds to be
190 # applied; no CPU-type/version detection exists, unlike the similar options in
191 # the Linux kernel. Do not set these options unless they apply! Also note that
192 # the following can be machine-specific errata. These do have ability to
193 # provide rudimentary version and machine-specific checks, but expect no
195 # CONFIG_ARM_ERRATA_430973
196 # CONFIG_ARM_ERRATA_454179
197 # CONFIG_ARM_ERRATA_621766
198 # CONFIG_ARM_ERRATA_798870
199 # CONFIG_ARM_ERRATA_801819
200 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
201 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
203 config ARM_ERRATA_430973
206 config ARM_ERRATA_454179
209 config ARM_ERRATA_621766
212 config ARM_ERRATA_716044
215 config ARM_ERRATA_725233
218 config ARM_ERRATA_742230
221 config ARM_ERRATA_743622
224 config ARM_ERRATA_751472
227 config ARM_ERRATA_761320
230 config ARM_ERRATA_773022
233 config ARM_ERRATA_774769
236 config ARM_ERRATA_794072
239 config ARM_ERRATA_798870
242 config ARM_ERRATA_801819
245 config ARM_ERRATA_826974
248 config ARM_ERRATA_828024
251 config ARM_ERRATA_829520
254 config ARM_ERRATA_833069
257 config ARM_ERRATA_833471
260 config ARM_ERRATA_845369
263 config ARM_ERRATA_852421
266 config ARM_ERRATA_852423
269 config ARM_ERRATA_855873
272 config ARM_CORTEX_A8_CVE_2017_5715
275 config ARM_CORTEX_A15_CVE_2017_5715
280 select SYS_CACHE_SHIFT_5
285 select SYS_CACHE_SHIFT_5
290 select SYS_CACHE_SHIFT_5
292 imply SPL_SEPARATE_BSS
296 select SYS_CACHE_SHIFT_5
301 select SYS_CACHE_SHIFT_5
303 imply SPL_SEPARATE_BSS
308 select SYS_CACHE_SHIFT_5
315 select SYS_CACHE_SHIFT_6
322 select SYS_CACHE_SHIFT_5
323 select SYS_THUMB_BUILD
329 select SYS_ARM_CACHE_CP15
331 select SYS_CACHE_SHIFT_6
335 select SYS_CACHE_SHIFT_5
344 select SYS_CACHE_SHIFT_5
348 default "arm720t" if CPU_ARM720T
349 default "arm920t" if CPU_ARM920T
350 default "arm926ejs" if CPU_ARM926EJS
351 default "arm946es" if CPU_ARM946ES
352 default "arm1136" if CPU_ARM1136
353 default "arm1176" if CPU_ARM1176
354 default "armv7" if CPU_V7A
355 default "armv7" if CPU_V7R
356 default "armv7m" if CPU_V7M
357 default "pxa" if CPU_PXA
358 default "sa1100" if CPU_SA1100
359 default "armv8" if ARM64
363 default 4 if CPU_ARM720T
364 default 4 if CPU_ARM920T
365 default 5 if CPU_ARM926EJS
366 default 5 if CPU_ARM946ES
367 default 6 if CPU_ARM1136
368 default 6 if CPU_ARM1176
373 default 4 if CPU_SA1100
377 prompt "Select the ARM data write cache policy"
378 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
380 default SYS_ARM_CACHE_WRITEBACK
382 config SYS_ARM_CACHE_WRITEBACK
383 bool "Write-back (WB)"
385 A write updates the cache only and marks the cache line as dirty.
386 External memory is updated only when the line is evicted or explicitly
389 config SYS_ARM_CACHE_WRITETHROUGH
390 bool "Write-through (WT)"
392 A write updates both the cache and the external memory system.
393 This does not mark the cache line as dirty.
395 config SYS_ARM_CACHE_WRITEALLOC
396 bool "Write allocation (WA)"
398 A cache line is allocated on a write miss. This means that executing a
399 store instruction on the processor might cause a burst read to occur.
400 There is a linefill to obtain the data for the cache line, before the
404 config ARCH_VERY_EARLY_INIT
407 config SPL_ARCH_VERY_EARLY_INIT
411 bool "Enable ARCH_CPU_INIT"
413 Some architectures require a call to arch_cpu_init().
414 Say Y here to enable it
416 config SYS_ARCH_TIMER
417 bool "ARM Generic Timer support"
418 depends on CPU_V7A || ARM64
421 The ARM Generic Timer (aka arch-timer) provides an architected
422 interface to a timer source on an SoC.
423 It is mandatory for ARMv8 implementation and widely available
427 bool "Support for ARM SMC Calling Convention (SMCCC)"
428 depends on CPU_V7A || ARM64
431 Say Y here if you want to enable ARM SMC Calling Convention.
432 This should be enabled if U-Boot needs to communicate with system
433 firmware (for example, PSCI) according to SMCCC.
436 bool "Support ARM semihosting"
438 Semihosting is a method for a target to communicate with a host
439 debugger. It uses special instructions which the debugger will trap
440 on and interpret. This allows U-Boot to read/write files, print to
441 the console, and execute arbitrary commands on the host system.
443 Enabling this option will add support for reading and writing files
444 on the host system. If you don't have a debugger attached then trying
445 to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
447 config SEMIHOSTING_FALLBACK
448 bool "Recover gracefully when semihosting fails"
449 depends on SEMIHOSTING && ARM64
452 Normally, if U-Boot makes a semihosting call and no debugger is
453 attached, then it will panic due to a synchronous abort
454 exception. This config adds an exception handler which will allow
455 U-Boot to recover. Say 'y' if unsure.
457 config SPL_SEMIHOSTING
458 bool "Support ARM semihosting in SPL"
461 Semihosting is a method for a target to communicate with a host
462 debugger. It uses special instructions which the debugger will trap
463 on and interpret. This allows U-Boot to read/write files, print to
464 the console, and execute arbitrary commands on the host system.
466 Enabling this option will add support for reading and writing files
467 on the host system. If you don't have a debugger attached then trying
468 to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
470 config SPL_SEMIHOSTING_FALLBACK
471 bool "Recover gracefully when semihosting fails in SPL"
472 depends on SPL_SEMIHOSTING && ARM64
473 select ARMV8_SPL_EXCEPTION_VECTORS
476 Normally, if U-Boot makes a semihosting call and no debugger is
477 attached, then it will panic due to a synchronous abort
478 exception. This config adds an exception handler which will allow
479 U-Boot to recover. Say 'y' if unsure.
481 config SYS_THUMB_BUILD
482 bool "Build U-Boot using the Thumb instruction set"
485 Use this flag to build U-Boot using the Thumb instruction set for
486 ARM architectures. Thumb instruction set provides better code
487 density. For ARM architectures that support Thumb2 this flag will
488 result in Thumb2 code generated by GCC.
490 config SPL_SYS_THUMB_BUILD
491 bool "Build SPL using the Thumb instruction set"
492 default y if SYS_THUMB_BUILD
493 depends on !ARM64 && SPL
495 Use this flag to build SPL using the Thumb instruction set for
496 ARM architectures. Thumb instruction set provides better code
497 density. For ARM architectures that support Thumb2 this flag will
498 result in Thumb2 code generated by GCC.
500 config TPL_SYS_THUMB_BUILD
501 bool "Build TPL using the Thumb instruction set"
502 default y if SYS_THUMB_BUILD
503 depends on TPL && !ARM64
505 Use this flag to build TPL using the Thumb instruction set for
506 ARM architectures. Thumb instruction set provides better code
507 density. For ARM architectures that support Thumb2 this flag will
508 result in Thumb2 code generated by GCC.
511 config SYS_L2CACHE_OFF
514 If SoC does not support L2CACHE or one does not want to enable
515 L2CACHE, choose this option.
517 config ENABLE_ARM_SOC_BOOT0_HOOK
518 bool "prepare BOOT0 header"
520 If the SoC's BOOT0 requires a header area filled with (magic)
521 values, then choose this option, and create a file included as
522 <asm/arch/boot0.h> which contains the required assembler code.
524 config USE_ARCH_MEMCPY
525 bool "Use an assembly optimized implementation of memcpy"
527 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
529 Enable the generation of an optimized version of memcpy.
530 Such an implementation may be faster under some conditions
531 but may increase the binary size.
533 config SPL_USE_ARCH_MEMCPY
534 bool "Use an assembly optimized implementation of memcpy for SPL"
535 default y if USE_ARCH_MEMCPY
538 Enable the generation of an optimized version of memcpy.
539 Such an implementation may be faster under some conditions
540 but may increase the binary size.
542 config TPL_USE_ARCH_MEMCPY
543 bool "Use an assembly optimized implementation of memcpy for TPL"
544 default y if USE_ARCH_MEMCPY
547 Enable the generation of an optimized version of memcpy.
548 Such an implementation may be faster under some conditions
549 but may increase the binary size.
551 config USE_ARCH_MEMMOVE
552 bool "Use an assembly optimized implementation of memmove" if !ARM64
553 default USE_ARCH_MEMCPY if ARM64
556 Enable the generation of an optimized version of memmove.
557 Such an implementation may be faster under some conditions
558 but may increase the binary size.
560 config SPL_USE_ARCH_MEMMOVE
561 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
562 default SPL_USE_ARCH_MEMCPY if ARM64
563 depends on SPL && ARM64
565 Enable the generation of an optimized version of memmove.
566 Such an implementation may be faster under some conditions
567 but may increase the binary size.
569 config TPL_USE_ARCH_MEMMOVE
570 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
571 default TPL_USE_ARCH_MEMCPY if ARM64
572 depends on TPL && ARM64
574 Enable the generation of an optimized version of memmove.
575 Such an implementation may be faster under some conditions
576 but may increase the binary size.
578 config USE_ARCH_MEMSET
579 bool "Use an assembly optimized implementation of memset"
581 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
583 Enable the generation of an optimized version of memset.
584 Such an implementation may be faster under some conditions
585 but may increase the binary size.
587 config SPL_USE_ARCH_MEMSET
588 bool "Use an assembly optimized implementation of memset for SPL"
589 default y if USE_ARCH_MEMSET
592 Enable the generation of an optimized version of memset.
593 Such an implementation may be faster under some conditions
594 but may increase the binary size.
596 config TPL_USE_ARCH_MEMSET
597 bool "Use an assembly optimized implementation of memset for TPL"
598 default y if USE_ARCH_MEMSET
601 Enable the generation of an optimized version of memset.
602 Such an implementation may be faster under some conditions
603 but may increase the binary size.
605 config ARM64_SUPPORT_AARCH32
606 bool "ARM64 system support AArch32 execution state"
608 default y if !TARGET_THUNDERX_88XX
610 This ARM64 system supports AArch32 execution state.
613 prompt "Target select"
618 select GPIO_EXTRA_HEADER
619 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
620 select SPL_SEPARATE_BSS if SPL
625 select GPIO_EXTRA_HEADER
626 select SPL_DM_SPI if SPL
629 Support for TI's DaVinci platform.
632 bool "Marvell Kirkwood"
633 select ARCH_MISC_INIT
634 select BOARD_EARLY_INIT_F
636 select GPIO_EXTRA_HEADER
639 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
645 select GPIO_EXTRA_HEADER
646 select SPL_DM_SPI if SPL
647 select SPL_DM_SPI_FLASH if SPL
656 select GPIO_EXTRA_HEADER
657 select SPL_SEPARATE_BSS if SPL
659 config TARGET_STV0991
660 bool "Support stv0991"
666 select GPIO_EXTRA_HEADER
673 bool "Broadcom BCM283X family"
677 select GPIO_EXTRA_HEADER
680 select SERIAL_SEARCH_ALL
685 bool "Broadcom BCM63158 family"
691 bool "Broadcom BCM6753 family"
698 bool "Broadcom BCM68360 family"
704 bool "Broadcom BCM6858 family"
710 bool "Broadcom BCM7XXX family"
713 select GPIO_EXTRA_HEADER
716 imply OF_HAS_PRIOR_STAGE
718 This enables support for Broadcom ARM-based set-top box
719 chipsets, including the 7445 family of chips.
722 bool "Broadcom broadband chip family"
726 config TARGET_VEXPRESS_CA9X4
727 bool "Support vexpress_ca9x4"
731 config TARGET_BCMCYGNUS
732 bool "Support bcmcygnus"
734 select GPIO_EXTRA_HEADER
736 imply BCM_SF2_ETH_GMAC
744 bool "Support Broadcom Northstar2"
746 select GPIO_EXTRA_HEADER
748 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
749 ARMv8 Cortex-A57 processors targeting a broad range of networking
753 bool "Support Broadcom NS3"
755 select BOARD_LATE_INIT
757 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
758 ARMv8 Cortex-A72 processors targeting a broad range of networking
762 bool "Samsung EXYNOS"
772 select GPIO_EXTRA_HEADER
773 imply SYS_THUMB_BUILD
778 bool "Samsung S5PC1XX"
784 select GPIO_EXTRA_HEADER
788 bool "Calxeda Highbank"
799 imply OF_HAS_PRIOR_STAGE
801 config ARCH_INTEGRATOR
802 bool "ARM Ltd. Integrator family"
805 select GPIO_EXTRA_HEADER
810 bool "Qualcomm IPQ40xx SoCs"
816 select GPIO_EXTRA_HEADER
829 select GPIO_EXTRA_HEADER
831 select SYS_ARCH_TIMER
832 select SYS_THUMB_BUILD
838 bool "Texas Instruments' K3 Architecture"
843 config ARCH_OMAP2PLUS
846 select GPIO_EXTRA_HEADER
847 select SPL_BOARD_INIT if SPL
848 select SPL_STACK_R if SPL
850 imply TI_SYSC if DM && OF_CONTROL
853 imply SPL_SEPARATE_BSS
857 select GPIO_EXTRA_HEADER
858 imply DISTRO_DEFAULTS
861 Support for the Meson SoC family developed by Amlogic Inc.,
862 targeted at media players and tablet computers. We currently
863 support the S905 (GXBaby) 64-bit SoC.
868 select GPIO_EXTRA_HEADER
871 select SPL_LIBCOMMON_SUPPORT if SPL
872 select SPL_LIBGENERIC_SUPPORT if SPL
873 select SPL_OF_CONTROL if SPL
876 Support for the MediaTek SoCs family developed by MediaTek Inc.
877 Please refer to doc/README.mediatek for more information.
880 bool "NXP LPC32xx platform"
885 select GPIO_EXTRA_HEADER
891 bool "NXP i.MX8 platform"
893 select SYS_FSL_HAS_SEC
894 select SYS_FSL_SEC_COMPAT_4
895 select SYS_FSL_SEC_LE
897 select GPIO_EXTRA_HEADER
900 select ENABLE_ARM_SOC_BOOT0_HOOK
904 bool "NXP i.MX8M platform"
906 select GPIO_EXTRA_HEADER
908 select SYS_FSL_HAS_SEC
909 select SYS_FSL_SEC_COMPAT_4
910 select SYS_FSL_SEC_LE
918 bool "NXP i.MX8ULP platform"
924 select GPIO_EXTRA_HEADER
929 bool "NXP i.MXRT platform"
933 select GPIO_EXTRA_HEADER
939 bool "NXP i.MX23 family"
941 select GPIO_EXTRA_HEADER
947 bool "NXP i.MX28 family"
949 select GPIO_EXTRA_HEADER
955 bool "NXP i.MX31 family"
957 select GPIO_EXTRA_HEADER
962 select BOARD_POSTCLK_INIT
964 select GPIO_EXTRA_HEADER
966 select SYS_FSL_HAS_SEC
967 select SYS_FSL_SEC_COMPAT_4
968 select SYS_FSL_SEC_LE
969 select ROM_UNIFIED_SECTIONS
971 imply SYS_THUMB_BUILD
975 select ARCH_MISC_INIT
977 select GPIO_EXTRA_HEADER
979 select SYS_FSL_HAS_SEC
980 select SYS_FSL_SEC_COMPAT_4
981 select SYS_FSL_SEC_LE
982 imply BOARD_EARLY_INIT_F
984 imply SYS_THUMB_BUILD
988 select BOARD_POSTCLK_INIT
990 select GPIO_EXTRA_HEADER
992 select SYS_FSL_HAS_SEC
993 select SYS_FSL_SEC_COMPAT_4
994 select SYS_FSL_SEC_LE
996 imply SYS_THUMB_BUILD
997 imply SPL_SEPARATE_BSS
1001 default "arch/arm/mach-omap2/u-boot-spl.lds"
1005 bool "Freescale MX5"
1006 select BOARD_EARLY_INIT_F
1008 select GPIO_EXTRA_HEADER
1013 bool "Nexell S5P4418/S5P6818 SoC"
1014 select ENABLE_ARM_SOC_BOOT0_HOOK
1016 select GPIO_EXTRA_HEADER
1019 bool "Support Nuvoton SoCs"
1040 select LINUX_KERNEL_IMAGE_HEADER
1041 select OF_BOARD_SETUP
1044 select POSITION_INDEPENDENT
1050 select SYSRESET_WATCHDOG
1051 select SYSRESET_WATCHDOG_AUTO
1055 imply DISTRO_DEFAULTS
1056 imply OF_HAS_PRIOR_STAGE
1059 bool "Actions Semi OWL SoCs"
1063 select GPIO_EXTRA_HEADER
1068 select SYS_RELOC_GD_ENV_ADDR
1072 bool "QEMU Virtual Platform"
1081 imply OF_HAS_PRIOR_STAGE
1084 bool "Renesas ARM SoCs"
1087 select GPIO_EXTRA_HEADER
1088 imply BOARD_EARLY_INIT_F
1091 imply SYS_THUMB_BUILD
1092 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1094 config ARCH_SNAPDRAGON
1095 bool "Qualcomm Snapdragon SoCs"
1100 select GPIO_EXTRA_HEADER
1109 bool "Altera SOCFPGA family"
1110 select ARCH_EARLY_INIT_R
1111 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1112 select ARM64 if TARGET_SOCFPGA_SOC64
1113 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1117 select GPIO_EXTRA_HEADER
1118 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1120 select SPL_DM_RESET if DM_RESET
1121 select SPL_DM_SERIAL
1122 select SPL_LIBCOMMON_SUPPORT
1123 select SPL_LIBGENERIC_SUPPORT
1124 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
1125 select SPL_OF_CONTROL
1126 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1132 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1134 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1135 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1145 imply SPL_DM_SPI_FLASH
1146 imply SPL_LIBDISK_SUPPORT
1148 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1149 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1150 imply SPL_SPI_FLASH_SUPPORT
1155 bool "Support sunxi (Allwinner) SoCs"
1158 select CMD_MMC if MMC
1159 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1164 select DM_I2C if I2C
1165 select DM_SPI if SPI
1166 select DM_SPI_FLASH if SPI
1168 select DM_MMC if MMC
1169 select DM_SCSI if SCSI
1171 select GPIO_EXTRA_HEADER
1172 select OF_BOARD_SETUP
1176 select SPECIFY_CONSOLE_INDEX
1177 select SPL_SEPARATE_BSS if SPL
1178 select SPL_STACK_R if SPL
1179 select SPL_SYS_MALLOC_SIMPLE if SPL
1180 select SPL_SYS_THUMB_BUILD if !ARM64
1183 select SYS_THUMB_BUILD if !ARM64
1184 select USB if DISTRO_DEFAULTS
1185 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1186 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1187 select SPL_USE_TINY_PRINTF
1189 select SYS_RELOC_GD_ENV_ADDR
1190 imply BOARD_LATE_INIT
1193 imply CMD_UBI if MTD_RAW_NAND
1194 imply DISTRO_DEFAULTS
1197 imply OF_LIBFDT_OVERLAY
1198 imply PRE_CONSOLE_BUFFER
1200 imply SPL_LIBCOMMON_SUPPORT
1201 imply SPL_LIBGENERIC_SUPPORT
1202 imply SPL_MMC if MMC
1206 imply SYSRESET_WATCHDOG
1207 imply SYSRESET_WATCHDOG_AUTO
1212 bool "ST-Ericsson U8500 Series"
1216 select DM_MMC if MMC
1218 select DM_USB_GADGET if DM_USB
1222 imply AB8500_USB_PHY
1223 imply ARM_PL180_MMCI
1228 imply NOMADIK_MTU_TIMER
1233 imply SYS_THUMB_BUILD
1234 imply SYSRESET_SYSCON
1237 bool "Support Xilinx Versal Platform"
1241 select DM_ETH if NET
1242 select DM_MMC if MMC
1247 imply BOARD_LATE_INIT
1248 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1251 bool "Freescale Vybrid"
1253 select GPIO_EXTRA_HEADER
1255 select SYS_FSL_ERRATUM_ESDHC111
1260 bool "Xilinx Zynq based platform"
1264 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1266 select DM_ETH if NET
1267 select DM_MMC if MMC
1273 select SPL_BOARD_INIT if SPL
1274 select SPL_CLK if SPL
1275 select SPL_DM if SPL
1276 select SPL_DM_SPI if SPL
1277 select SPL_DM_SPI_FLASH if SPL
1278 select SPL_OF_CONTROL if SPL
1279 select SPL_SEPARATE_BSS if SPL
1281 imply ARCH_EARLY_INIT_R
1282 imply BOARD_LATE_INIT
1286 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1289 config ARCH_ZYNQMP_R5
1290 bool "Xilinx ZynqMP R5 based platform"
1294 select DM_ETH if NET
1295 select DM_MMC if MMC
1302 bool "Xilinx ZynqMP based platform"
1306 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1307 select DM_ETH if NET
1309 select DM_MMC if MMC
1311 select DM_SPI if SPI
1312 select DM_SPI_FLASH if DM_SPI
1316 select SPL_BOARD_INIT if SPL
1317 select SPL_CLK if SPL
1318 select SPL_DM if SPL
1319 select SPL_DM_SPI if SPI && SPL_DM
1320 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1321 select SPL_DM_MAILBOX if SPL
1322 imply SPL_FIRMWARE if SPL
1323 select SPL_SEPARATE_BSS if SPL
1327 imply BOARD_LATE_INIT
1329 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1333 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1337 select GPIO_EXTRA_HEADER
1338 imply DISTRO_DEFAULTS
1341 config ARCH_VEXPRESS64
1342 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1350 select MTD_NOR_FLASH if MTD
1351 select FLASH_CFI_DRIVER if MTD
1352 select ENV_IS_IN_FLASH if MTD
1353 imply DISTRO_DEFAULTS
1355 config TARGET_CORSTONE1000
1356 bool "Support Corstone1000 Platform"
1361 config TARGET_TOTAL_COMPUTE
1362 bool "Support Total Compute Platform"
1370 config TARGET_LS2080A_EMU
1371 bool "Support ls2080a_emu"
1374 select ARMV8_MULTIENTRY
1375 select FSL_DDR_SYNC_REFRESH
1376 select GPIO_EXTRA_HEADER
1378 Support for Freescale LS2080A_EMU platform.
1379 The LS2080A Development System (EMULATOR) is a pre-silicon
1380 development platform that supports the QorIQ LS2080A
1381 Layerscape Architecture processor.
1383 config TARGET_LS1088AQDS
1384 bool "Support ls1088aqds"
1387 select ARMV8_MULTIENTRY
1388 select ARCH_SUPPORT_TFABOOT
1389 select BOARD_LATE_INIT
1390 select GPIO_EXTRA_HEADER
1392 select FSL_DDR_INTERACTIVE if !SD_BOOT
1394 Support for NXP LS1088AQDS platform.
1395 The LS1088A Development System (QDS) is a high-performance
1396 development platform that supports the QorIQ LS1088A
1397 Layerscape Architecture processor.
1399 config TARGET_LS2080AQDS
1400 bool "Support ls2080aqds"
1403 select ARMV8_MULTIENTRY
1404 select ARCH_SUPPORT_TFABOOT
1405 select BOARD_LATE_INIT
1406 select GPIO_EXTRA_HEADER
1411 select FSL_DDR_INTERACTIVE if !SPL
1413 Support for Freescale LS2080AQDS platform.
1414 The LS2080A Development System (QDS) is a high-performance
1415 development platform that supports the QorIQ LS2080A
1416 Layerscape Architecture processor.
1418 config TARGET_LS2080ARDB
1419 bool "Support ls2080ardb"
1422 select ARMV8_MULTIENTRY
1423 select ARCH_SUPPORT_TFABOOT
1424 select BOARD_LATE_INIT
1427 select FSL_DDR_INTERACTIVE if !SPL
1428 select GPIO_EXTRA_HEADER
1432 Support for Freescale LS2080ARDB platform.
1433 The LS2080A Reference design board (RDB) is a high-performance
1434 development platform that supports the QorIQ LS2080A
1435 Layerscape Architecture processor.
1437 config TARGET_LS2081ARDB
1438 bool "Support ls2081ardb"
1441 select ARMV8_MULTIENTRY
1442 select BOARD_LATE_INIT
1443 select GPIO_EXTRA_HEADER
1446 Support for Freescale LS2081ARDB platform.
1447 The LS2081A Reference design board (RDB) is a high-performance
1448 development platform that supports the QorIQ LS2081A/LS2041A
1449 Layerscape Architecture processor.
1451 config TARGET_LX2160ARDB
1452 bool "Support lx2160ardb"
1455 select ARMV8_MULTIENTRY
1456 select ARCH_SUPPORT_TFABOOT
1457 select BOARD_LATE_INIT
1458 select GPIO_EXTRA_HEADER
1460 Support for NXP LX2160ARDB platform.
1461 The lx2160ardb (LX2160A Reference design board (RDB)
1462 is a high-performance development platform that supports the
1463 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1465 config TARGET_LX2160AQDS
1466 bool "Support lx2160aqds"
1469 select ARMV8_MULTIENTRY
1470 select ARCH_SUPPORT_TFABOOT
1471 select BOARD_LATE_INIT
1472 select GPIO_EXTRA_HEADER
1474 Support for NXP LX2160AQDS platform.
1475 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1476 is a high-performance development platform that supports the
1477 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1479 config TARGET_LX2162AQDS
1480 bool "Support lx2162aqds"
1482 select ARCH_MISC_INIT
1484 select ARMV8_MULTIENTRY
1485 select ARCH_SUPPORT_TFABOOT
1486 select BOARD_LATE_INIT
1487 select GPIO_EXTRA_HEADER
1489 Support for NXP LX2162AQDS platform.
1490 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1493 bool "Support HiKey 96boards Consumer Edition Platform"
1498 select GPIO_EXTRA_HEADER
1501 select SPECIFY_CONSOLE_INDEX
1504 Support for HiKey 96boards platform. It features a HI6220
1505 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1507 config TARGET_HIKEY960
1508 bool "Support HiKey960 96boards Consumer Edition Platform"
1512 select GPIO_EXTRA_HEADER
1517 Support for HiKey960 96boards platform. It features a HI3660
1518 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1520 config TARGET_POPLAR
1521 bool "Support Poplar 96boards Enterprise Edition Platform"
1525 select GPIO_EXTRA_HEADER
1530 Support for Poplar 96boards EE platform. It features a HI3798cv200
1531 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1532 making it capable of running any commercial set-top solution based on
1535 config TARGET_LS1012AQDS
1536 bool "Support ls1012aqds"
1539 select ARCH_SUPPORT_TFABOOT
1540 select BOARD_LATE_INIT
1541 select GPIO_EXTRA_HEADER
1543 Support for Freescale LS1012AQDS platform.
1544 The LS1012A Development System (QDS) is a high-performance
1545 development platform that supports the QorIQ LS1012A
1546 Layerscape Architecture processor.
1548 config TARGET_LS1012ARDB
1549 bool "Support ls1012ardb"
1552 select ARCH_SUPPORT_TFABOOT
1553 select BOARD_LATE_INIT
1554 select GPIO_EXTRA_HEADER
1558 Support for Freescale LS1012ARDB platform.
1559 The LS1012A Reference design board (RDB) is a high-performance
1560 development platform that supports the QorIQ LS1012A
1561 Layerscape Architecture processor.
1563 config TARGET_LS1012A2G5RDB
1564 bool "Support ls1012a2g5rdb"
1567 select ARCH_SUPPORT_TFABOOT
1568 select BOARD_LATE_INIT
1569 select GPIO_EXTRA_HEADER
1572 Support for Freescale LS1012A2G5RDB platform.
1573 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1574 development platform that supports the QorIQ LS1012A
1575 Layerscape Architecture processor.
1577 config TARGET_LS1012AFRWY
1578 bool "Support ls1012afrwy"
1581 select ARCH_SUPPORT_TFABOOT
1582 select BOARD_LATE_INIT
1583 select GPIO_EXTRA_HEADER
1587 Support for Freescale LS1012AFRWY platform.
1588 The LS1012A FRWY board (FRWY) is a high-performance
1589 development platform that supports the QorIQ LS1012A
1590 Layerscape Architecture processor.
1592 config TARGET_LS1012AFRDM
1593 bool "Support ls1012afrdm"
1596 select ARCH_SUPPORT_TFABOOT
1597 select GPIO_EXTRA_HEADER
1599 Support for Freescale LS1012AFRDM platform.
1600 The LS1012A Freedom board (FRDM) is a high-performance
1601 development platform that supports the QorIQ LS1012A
1602 Layerscape Architecture processor.
1604 config TARGET_LS1028AQDS
1605 bool "Support ls1028aqds"
1608 select ARMV8_MULTIENTRY
1609 select ARCH_SUPPORT_TFABOOT
1610 select BOARD_LATE_INIT
1611 select GPIO_EXTRA_HEADER
1613 Support for Freescale LS1028AQDS platform
1614 The LS1028A Development System (QDS) is a high-performance
1615 development platform that supports the QorIQ LS1028A
1616 Layerscape Architecture processor.
1618 config TARGET_LS1028ARDB
1619 bool "Support ls1028ardb"
1622 select ARMV8_MULTIENTRY
1623 select ARCH_SUPPORT_TFABOOT
1624 select BOARD_LATE_INIT
1625 select GPIO_EXTRA_HEADER
1627 Support for Freescale LS1028ARDB platform
1628 The LS1028A Development System (RDB) is a high-performance
1629 development platform that supports the QorIQ LS1028A
1630 Layerscape Architecture processor.
1632 config TARGET_LS1088ARDB
1633 bool "Support ls1088ardb"
1636 select ARMV8_MULTIENTRY
1637 select ARCH_SUPPORT_TFABOOT
1638 select BOARD_LATE_INIT
1640 select FSL_DDR_INTERACTIVE if !SD_BOOT
1641 select GPIO_EXTRA_HEADER
1643 Support for NXP LS1088ARDB platform.
1644 The LS1088A Reference design board (RDB) is a high-performance
1645 development platform that supports the QorIQ LS1088A
1646 Layerscape Architecture processor.
1648 config TARGET_LS1021AQDS
1649 bool "Support ls1021aqds"
1651 select ARCH_SUPPORT_PSCI
1652 select BOARD_EARLY_INIT_F
1653 select BOARD_LATE_INIT
1655 select CPU_V7_HAS_NONSEC
1656 select CPU_V7_HAS_VIRT
1657 select LS1_DEEP_SLEEP
1660 select FSL_DDR_INTERACTIVE
1661 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1662 select GPIO_EXTRA_HEADER
1663 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1666 config TARGET_LS1021ATWR
1667 bool "Support ls1021atwr"
1669 select ARCH_SUPPORT_PSCI
1670 select BOARD_EARLY_INIT_F
1671 select BOARD_LATE_INIT
1673 select CPU_V7_HAS_NONSEC
1674 select CPU_V7_HAS_VIRT
1675 select LS1_DEEP_SLEEP
1677 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1678 select GPIO_EXTRA_HEADER
1681 config TARGET_PG_WCOM_SELI8
1682 bool "Support Hitachi-Powergrids SELI8 service unit card"
1684 select ARCH_SUPPORT_PSCI
1685 select BOARD_EARLY_INIT_F
1686 select BOARD_LATE_INIT
1688 select CPU_V7_HAS_NONSEC
1689 select CPU_V7_HAS_VIRT
1691 select FSL_DDR_INTERACTIVE
1692 select GPIO_EXTRA_HEADER
1696 Support for Hitachi-Powergrids SELI8 service unit card.
1697 SELI8 is a QorIQ LS1021a based service unit card used
1698 in XMC20 and FOX615 product families.
1700 config TARGET_PG_WCOM_EXPU1
1701 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1703 select ARCH_SUPPORT_PSCI
1704 select BOARD_EARLY_INIT_F
1705 select BOARD_LATE_INIT
1707 select CPU_V7_HAS_NONSEC
1708 select CPU_V7_HAS_VIRT
1710 select FSL_DDR_INTERACTIVE
1714 Support for Hitachi-Powergrids EXPU1 service unit card.
1715 EXPU1 is a QorIQ LS1021a based service unit card used
1716 in XMC20 and FOX615 product families.
1718 config TARGET_LS1021ATSN
1719 bool "Support ls1021atsn"
1721 select ARCH_SUPPORT_PSCI
1722 select BOARD_EARLY_INIT_F
1723 select BOARD_LATE_INIT
1725 select CPU_V7_HAS_NONSEC
1726 select CPU_V7_HAS_VIRT
1727 select LS1_DEEP_SLEEP
1729 select GPIO_EXTRA_HEADER
1732 config TARGET_LS1021AIOT
1733 bool "Support ls1021aiot"
1735 select ARCH_SUPPORT_PSCI
1736 select BOARD_LATE_INIT
1738 select CPU_V7_HAS_NONSEC
1739 select CPU_V7_HAS_VIRT
1741 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1742 select GPIO_EXTRA_HEADER
1745 Support for Freescale LS1021AIOT platform.
1746 The LS1021A Freescale board (IOT) is a high-performance
1747 development platform that supports the QorIQ LS1021A
1748 Layerscape Architecture processor.
1750 config TARGET_LS1043AQDS
1751 bool "Support ls1043aqds"
1754 select ARMV8_MULTIENTRY
1755 select ARCH_SUPPORT_TFABOOT
1756 select BOARD_EARLY_INIT_F
1757 select BOARD_LATE_INIT
1759 select FSL_DDR_INTERACTIVE if !SPL
1760 select FSL_DSPI if !SPL_NO_DSPI
1761 select DM_SPI_FLASH if FSL_DSPI
1762 select GPIO_EXTRA_HEADER
1766 Support for Freescale LS1043AQDS platform.
1768 config TARGET_LS1043ARDB
1769 bool "Support ls1043ardb"
1772 select ARMV8_MULTIENTRY
1773 select ARCH_SUPPORT_TFABOOT
1774 select BOARD_EARLY_INIT_F
1775 select BOARD_LATE_INIT
1777 select FSL_DSPI if !SPL_NO_DSPI
1778 select DM_SPI_FLASH if FSL_DSPI
1779 select GPIO_EXTRA_HEADER
1781 Support for Freescale LS1043ARDB platform.
1783 config TARGET_LS1046AQDS
1784 bool "Support ls1046aqds"
1787 select ARMV8_MULTIENTRY
1788 select ARCH_SUPPORT_TFABOOT
1789 select BOARD_EARLY_INIT_F
1790 select BOARD_LATE_INIT
1791 select DM_SPI_FLASH if DM_SPI
1793 select FSL_DDR_BIST if !SPL
1794 select FSL_DDR_INTERACTIVE if !SPL
1795 select FSL_DDR_INTERACTIVE if !SPL
1796 select GPIO_EXTRA_HEADER
1799 Support for Freescale LS1046AQDS platform.
1800 The LS1046A Development System (QDS) is a high-performance
1801 development platform that supports the QorIQ LS1046A
1802 Layerscape Architecture processor.
1804 config TARGET_LS1046ARDB
1805 bool "Support ls1046ardb"
1808 select ARMV8_MULTIENTRY
1809 select ARCH_SUPPORT_TFABOOT
1810 select BOARD_EARLY_INIT_F
1811 select BOARD_LATE_INIT
1812 select DM_SPI_FLASH if DM_SPI
1813 select POWER_MC34VR500
1816 select FSL_DDR_INTERACTIVE if !SPL
1817 select GPIO_EXTRA_HEADER
1820 Support for Freescale LS1046ARDB platform.
1821 The LS1046A Reference Design Board (RDB) is a high-performance
1822 development platform that supports the QorIQ LS1046A
1823 Layerscape Architecture processor.
1825 config TARGET_LS1046AFRWY
1826 bool "Support ls1046afrwy"
1829 select ARMV8_MULTIENTRY
1830 select ARCH_SUPPORT_TFABOOT
1831 select BOARD_EARLY_INIT_F
1832 select BOARD_LATE_INIT
1833 select DM_SPI_FLASH if DM_SPI
1834 select GPIO_EXTRA_HEADER
1837 Support for Freescale LS1046AFRWY platform.
1838 The LS1046A Freeway Board (FRWY) is a high-performance
1839 development platform that supports the QorIQ LS1046A
1840 Layerscape Architecture processor.
1846 select ARMV8_MULTIENTRY
1862 select GPIO_EXTRA_HEADER
1863 select SPL_DM if SPL
1864 select SPL_DM_SPI if SPL
1865 select SPL_DM_SPI_FLASH if SPL
1866 select SPL_DM_I2C if SPL
1867 select SPL_DM_MMC if SPL
1868 select SPL_DM_SERIAL if SPL
1870 Support for Kontron SMARC-sAL28 board.
1873 bool "Support ten64"
1875 select ARCH_MISC_INIT
1877 select ARMV8_MULTIENTRY
1878 select ARCH_SUPPORT_TFABOOT
1879 select BOARD_LATE_INIT
1881 select FSL_DDR_INTERACTIVE if !SD_BOOT
1882 select GPIO_EXTRA_HEADER
1884 Support for Traverse Technologies Ten64 board, based
1887 config ARCH_UNIPHIER
1888 bool "Socionext UniPhier SoCs"
1889 select BOARD_LATE_INIT
1898 select OF_BOARD_SETUP
1902 select SPL_BOARD_INIT if SPL
1903 select SPL_DM if SPL
1904 select SPL_LIBCOMMON_SUPPORT if SPL
1905 select SPL_LIBGENERIC_SUPPORT if SPL
1906 select SPL_OF_CONTROL if SPL
1907 select SPL_PINCTRL if SPL
1910 imply DISTRO_DEFAULTS
1913 Support for UniPhier SoC family developed by Socionext Inc.
1914 (formerly, System LSI Business Division of Panasonic Corporation)
1916 config ARCH_SYNQUACER
1917 bool "Socionext SynQuacer SoCs"
1923 select SYSRESET_PSCI
1926 Support for SynQuacer SoC family developed by Socionext Inc.
1927 This SoC is used on 96boards EE DeveloperBox.
1930 bool "Support STMicroelectronics STM32 MCU with cortex M"
1937 bool "Support STMicroelectronics SoCs"
1946 Support for STMicroelectronics STiH407/10 SoC family.
1947 This SoC is used on Linaro 96Board STiH410-B2260
1950 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1951 select ARCH_MISC_INIT
1952 select ARCH_SUPPORT_TFABOOT
1953 select BOARD_LATE_INIT
1962 select OF_SYSTEM_SETUP
1967 select SYS_THUMB_BUILD
1971 imply OF_LIBFDT_OVERLAY
1972 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1976 Support for STM32MP SoC family developed by STMicroelectronics,
1977 MPUs based on ARM cortex A core
1978 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1979 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1981 SPL is the unsecure FSBL for the basic boot chain.
1983 config ARCH_ROCKCHIP
1984 bool "Support Rockchip SoCs"
1986 select BINMAN if SPL_OPTEE || (SPL && !ARM64)
1996 select ENABLE_ARM_SOC_BOOT0_HOOK
1999 select SPL_DM if SPL
2000 select SPL_DM_SPI if SPL
2001 select SPL_DM_SPI_FLASH if SPL
2003 select SYS_THUMB_BUILD if !ARM64
2006 imply DEBUG_UART_BOARD_INIT
2007 imply DISTRO_DEFAULTS
2009 imply SARADC_ROCKCHIP
2011 imply SPL_SYS_MALLOC_SIMPLE
2014 imply USB_FUNCTION_FASTBOOT
2016 config ARCH_OCTEONTX
2017 bool "Support OcteonTX SoCs"
2020 select GPIO_EXTRA_HEADER
2024 select BOARD_LATE_INIT
2025 select SYS_CACHE_SHIFT_7
2026 select SYS_PCI_64BIT if PCI
2027 imply OF_HAS_PRIOR_STAGE
2029 config ARCH_OCTEONTX2
2030 bool "Support OcteonTX2 SoCs"
2033 select GPIO_EXTRA_HEADER
2037 select BOARD_LATE_INIT
2038 select SYS_CACHE_SHIFT_7
2039 select SYS_PCI_64BIT if PCI
2040 imply OF_HAS_PRIOR_STAGE
2042 config TARGET_THUNDERX_88XX
2043 bool "Support ThunderX 88xx"
2045 select GPIO_EXTRA_HEADER
2048 select SYS_CACHE_SHIFT_7
2051 bool "Support Aspeed SoCs"
2056 config TARGET_DURIAN
2057 bool "Support Phytium Durian Platform"
2059 select GPIO_EXTRA_HEADER
2061 Support for durian platform.
2062 It has 2GB Sdram, uart and pcie.
2064 config TARGET_POMELO
2065 bool "Support Phytium Pomelo Platform"
2077 select DM_ETH if NET
2080 Support for pomelo platform.
2081 It has 8GB Sdram, uart and pcie.
2083 config TARGET_PRESIDIO_ASIC
2084 bool "Support Cortina Presidio ASIC Platform"
2088 config TARGET_XENGUEST_ARM64
2089 bool "Xen guest ARM64"
2093 select LINUX_KERNEL_IMAGE_HEADER
2096 imply OF_HAS_PRIOR_STAGE
2100 config SUPPORT_PASSING_ATAGS
2101 bool "Support pre-devicetree ATAG-based booting"
2103 imply SETUP_MEMORY_TAGS
2105 Support for booting older Linux kernels, using ATAGs rather than
2106 passing a devicetree. This is option is rarely used, and the
2107 semantics are defined at
2108 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2110 config SETUP_MEMORY_TAGS
2111 bool "Pass memory size information via ATAG"
2112 depends on SUPPORT_PASSING_ATAGS
2115 bool "Pass Linux kernel cmdline via ATAG"
2116 depends on SUPPORT_PASSING_ATAGS
2119 bool "Pass initrd starting point and size via ATAG"
2120 depends on SUPPORT_PASSING_ATAGS
2123 bool "Pass system revision via ATAG"
2124 depends on SUPPORT_PASSING_ATAGS
2127 bool "Pass system serial number via ATAG"
2128 depends on SUPPORT_PASSING_ATAGS
2130 config STATIC_MACH_TYPE
2131 bool "Statically define the Machine ID number"
2133 When booting via ATAGs, enable this option if we know the correct
2134 machine ID number to use at compile time. Some systems will be
2135 passed the number dynamically by whatever loads U-Boot.
2138 int "Machine ID number"
2139 depends on STATIC_MACH_TYPE
2141 When booting via ATAGs, the machine type must be passed as a number.
2142 For the full list see https://www.arm.linux.org.uk/developer/machines
2144 config ARCH_SUPPORT_TFABOOT
2148 bool "Support for booting from TF-A"
2149 depends on ARCH_SUPPORT_TFABOOT
2151 Some platforms support the setup of secure registers (for instance
2152 for CPU errata handling) or provide secure services like PSCI.
2153 Those services could also be provided by other firmware parts
2154 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2155 does not need to (and cannot) execute this code.
2156 Enabling this option will make a U-Boot binary that is relying
2157 on other firmware layers to provide secure functionality.
2159 config TI_SECURE_DEVICE
2160 bool "HS Device Type Support"
2161 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2163 If a high secure (HS) device type is being used, this config
2164 must be set. This option impacts various aspects of the
2165 build system (to create signed boot images that can be
2166 authenticated) and the code. See the doc/README.ti-secure
2167 file for further details.
2169 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
2170 config ISW_ENTRY_ADDR
2171 hex "Address in memory or XIP address of bootloader entry point"
2172 default 0x402F4000 if AM43XX
2173 default 0x402F0400 if AM33XX
2174 default 0x40301350 if OMAP54XX
2176 After any reset, the boot ROM searches the boot media for a valid
2177 boot image. For non-XIP devices, the ROM then copies the image into
2178 internal memory. For all boot modes, after the ROM processes the
2179 boot image it eventually computes the entry point address depending
2180 on the device type (secure/non-secure), boot media (xip/non-xip) and
2184 config SYS_KWD_CONFIG
2185 string "kwbimage config file path"
2186 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2187 default "arch/arm/mach-mvebu/kwbimage.cfg"
2189 Path within the source directory to the kwbimage.cfg file to use
2190 when packaging the U-Boot image for use.
2192 source "arch/arm/mach-apple/Kconfig"
2194 source "arch/arm/mach-aspeed/Kconfig"
2196 source "arch/arm/mach-at91/Kconfig"
2198 source "arch/arm/mach-bcm283x/Kconfig"
2200 source "arch/arm/mach-bcmbca/Kconfig"
2202 source "arch/arm/mach-bcmstb/Kconfig"
2204 source "arch/arm/mach-davinci/Kconfig"
2206 source "arch/arm/mach-exynos/Kconfig"
2208 source "arch/arm/mach-highbank/Kconfig"
2210 source "arch/arm/mach-integrator/Kconfig"
2212 source "arch/arm/mach-ipq40xx/Kconfig"
2214 source "arch/arm/mach-k3/Kconfig"
2216 source "arch/arm/mach-keystone/Kconfig"
2218 source "arch/arm/mach-kirkwood/Kconfig"
2220 source "arch/arm/mach-lpc32xx/Kconfig"
2222 source "arch/arm/mach-mvebu/Kconfig"
2224 source "arch/arm/mach-octeontx/Kconfig"
2226 source "arch/arm/mach-octeontx2/Kconfig"
2228 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2230 source "arch/arm/mach-imx/mx3/Kconfig"
2232 source "arch/arm/mach-imx/mx5/Kconfig"
2234 source "arch/arm/mach-imx/mx6/Kconfig"
2236 source "arch/arm/mach-imx/mx7/Kconfig"
2238 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2240 source "arch/arm/mach-imx/imx8/Kconfig"
2242 source "arch/arm/mach-imx/imx8m/Kconfig"
2244 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2246 source "arch/arm/mach-imx/imxrt/Kconfig"
2248 source "arch/arm/mach-imx/mxs/Kconfig"
2250 source "arch/arm/mach-omap2/Kconfig"
2252 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2254 source "arch/arm/mach-orion5x/Kconfig"
2256 source "arch/arm/mach-owl/Kconfig"
2258 source "arch/arm/mach-rmobile/Kconfig"
2260 source "arch/arm/mach-meson/Kconfig"
2262 source "arch/arm/mach-mediatek/Kconfig"
2264 source "arch/arm/mach-qemu/Kconfig"
2266 source "arch/arm/mach-rockchip/Kconfig"
2268 source "arch/arm/mach-s5pc1xx/Kconfig"
2270 source "arch/arm/mach-snapdragon/Kconfig"
2272 source "arch/arm/mach-socfpga/Kconfig"
2274 source "arch/arm/mach-sti/Kconfig"
2276 source "arch/arm/mach-stm32/Kconfig"
2278 source "arch/arm/mach-stm32mp/Kconfig"
2280 source "arch/arm/mach-sunxi/Kconfig"
2282 source "arch/arm/mach-tegra/Kconfig"
2284 source "arch/arm/mach-u8500/Kconfig"
2286 source "arch/arm/mach-uniphier/Kconfig"
2288 source "arch/arm/cpu/armv7/vf610/Kconfig"
2290 source "arch/arm/mach-zynq/Kconfig"
2292 source "arch/arm/mach-zynqmp/Kconfig"
2294 source "arch/arm/mach-versal/Kconfig"
2296 source "arch/arm/mach-zynqmp-r5/Kconfig"
2298 source "arch/arm/cpu/armv7/Kconfig"
2300 source "arch/arm/cpu/armv8/Kconfig"
2302 source "arch/arm/mach-imx/Kconfig"
2304 source "arch/arm/mach-nexell/Kconfig"
2306 source "arch/arm/mach-npcm/Kconfig"
2308 source "board/armltd/total_compute/Kconfig"
2309 source "board/armltd/corstone1000/Kconfig"
2310 source "board/bosch/shc/Kconfig"
2311 source "board/bosch/guardian/Kconfig"
2312 source "board/Marvell/octeontx/Kconfig"
2313 source "board/Marvell/octeontx2/Kconfig"
2314 source "board/armltd/vexpress/Kconfig"
2315 source "board/armltd/vexpress64/Kconfig"
2316 source "board/cortina/presidio-asic/Kconfig"
2317 source "board/broadcom/bcm963158/Kconfig"
2318 source "board/broadcom/bcm96753ref/Kconfig"
2319 source "board/broadcom/bcm968360bg/Kconfig"
2320 source "board/broadcom/bcm968580xref/Kconfig"
2321 source "board/broadcom/bcmns3/Kconfig"
2322 source "board/cavium/thunderx/Kconfig"
2323 source "board/eets/pdu001/Kconfig"
2324 source "board/emulation/qemu-arm/Kconfig"
2325 source "board/freescale/ls2080aqds/Kconfig"
2326 source "board/freescale/ls2080ardb/Kconfig"
2327 source "board/freescale/ls1088a/Kconfig"
2328 source "board/freescale/ls1028a/Kconfig"
2329 source "board/freescale/ls1021aqds/Kconfig"
2330 source "board/freescale/ls1043aqds/Kconfig"
2331 source "board/freescale/ls1021atwr/Kconfig"
2332 source "board/freescale/ls1021atsn/Kconfig"
2333 source "board/freescale/ls1021aiot/Kconfig"
2334 source "board/freescale/ls1046aqds/Kconfig"
2335 source "board/freescale/ls1043ardb/Kconfig"
2336 source "board/freescale/ls1046ardb/Kconfig"
2337 source "board/freescale/ls1046afrwy/Kconfig"
2338 source "board/freescale/ls1012aqds/Kconfig"
2339 source "board/freescale/ls1012ardb/Kconfig"
2340 source "board/freescale/ls1012afrdm/Kconfig"
2341 source "board/freescale/lx2160a/Kconfig"
2342 source "board/grinn/chiliboard/Kconfig"
2343 source "board/hisilicon/hikey/Kconfig"
2344 source "board/hisilicon/hikey960/Kconfig"
2345 source "board/hisilicon/poplar/Kconfig"
2346 source "board/isee/igep003x/Kconfig"
2347 source "board/kontron/sl28/Kconfig"
2348 source "board/myir/mys_6ulx/Kconfig"
2349 source "board/seeed/npi_imx6ull/Kconfig"
2350 source "board/socionext/developerbox/Kconfig"
2351 source "board/st/stv0991/Kconfig"
2352 source "board/tcl/sl50/Kconfig"
2353 source "board/traverse/ten64/Kconfig"
2354 source "board/variscite/dart_6ul/Kconfig"
2355 source "board/vscom/baltos/Kconfig"
2356 source "board/phytium/durian/Kconfig"
2357 source "board/phytium/pomelo/Kconfig"
2358 source "board/xen/xenguest_arm64/Kconfig"
2360 source "arch/arm/Kconfig.debug"
2365 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
2366 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
2367 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64