1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
11 imply SPL_SEPARATE_BSS
14 bool "Enable support for CRC32 instruction"
18 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
19 This is faster than software crc32 calculation. This instruction may
20 not be present on all ARMv8.0, but is always present on ARMv8.1 and
23 config COUNTER_FREQUENCY
24 int "Timer clock frequency"
25 depends on ARM64 || CPU_V7A
26 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
27 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
28 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
29 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
30 default 100000000 if ARCH_ZYNQMP
33 For platforms with ARMv8-A and ARMv7-A which features a system
34 counter, those platforms needs software to program the counter
35 frequency. Setup time clock frequency for certain platform.
36 0 means no need to configure the system counter frequency.
37 For platforms needs the frequency set in U-Boot with a
38 pre-defined value, should have the macro defined as a non-zero value.
40 config POSITION_INDEPENDENT
41 bool "Generate position-independent pre-relocation code"
42 depends on ARM64 || CPU_V7A
44 U-Boot expects to be linked to a specific hard-coded address, and to
45 be loaded to and run from that address. This option lifts that
46 restriction, thus allowing the code to be loaded to and executed from
47 almost any 4K aligned address. This logic relies on the relocation
48 information that is embedded in the binary to support U-Boot
49 relocating itself to the top-of-RAM later during execution.
51 config INIT_SP_RELATIVE
52 bool "Specify the early stack pointer relative to the .bss section"
54 default n if ARCH_QEMU
55 default y if POSITION_INDEPENDENT
57 U-Boot typically uses a hard-coded value for the stack pointer
58 before relocation. Enable this option to instead calculate the
59 initial SP at run-time. This is useful to avoid hard-coding addresses
60 into U-Boot, so that it can be loaded and executed at arbitrary
61 addresses and thus avoid using arbitrary addresses at runtime.
63 If this option is enabled, the early stack pointer is set to
64 &_bss_start with a offset value added. The offset is specified by
65 SYS_INIT_SP_BSS_OFFSET.
67 config SYS_INIT_SP_BSS_OFFSET
68 int "Early stack offset from the .bss base address"
70 depends on INIT_SP_RELATIVE
73 This option's value is the offset added to &_bss_start in order to
74 calculate the stack pointer. This offset should be large enough so
75 that the early malloc region, global data (gd), and early stack usage
76 do not overlap any appended DTB.
78 config SPL_SYS_NO_VECTOR_TABLE
82 config LINUX_KERNEL_IMAGE_HEADER
86 Place a Linux kernel image header at the start of the U-Boot binary.
87 The format of the header is described in the Linux kernel source at
88 Documentation/arm64/booting.txt. This feature is useful since the
89 image header reports the amount of memory (BSS and similar) that
90 U-Boot needs to use, but which isn't part of the binary.
92 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
93 depends on LINUX_KERNEL_IMAGE_HEADER
96 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
97 TEXT_OFFSET value written to the Linux kernel image header.
109 ARM GICV3 Interrupt translation service (ITS).
110 Basic support for programming locality specific peripheral
111 interrupts (LPI) configuration tables and enable LPI tables.
112 LPI configuration table can be used by u-boot or Linux.
113 ARM GICV3 has limitation, once the LPI table is enabled, LPI
114 configuration table can not be re-programmed, unless GICV3 reset.
120 config DMA_ADDR_T_64BIT
130 config GPIO_EXTRA_HEADER
133 # Used for compatibility with asm files copied from the kernel
134 config ARM_ASM_UNIFIED
138 # Used for compatibility with asm files copied from the kernel
142 config SYS_ICACHE_OFF
143 bool "Do not enable icache"
145 Do not enable instruction cache in U-Boot.
147 config SPL_SYS_ICACHE_OFF
148 bool "Do not enable icache in SPL"
150 default SYS_ICACHE_OFF
152 Do not enable instruction cache in SPL.
154 config SYS_DCACHE_OFF
155 bool "Do not enable dcache"
157 Do not enable data cache in U-Boot.
159 config SPL_SYS_DCACHE_OFF
160 bool "Do not enable dcache in SPL"
162 default SYS_DCACHE_OFF
164 Do not enable data cache in SPL.
166 config SYS_ARM_CACHE_CP15
167 bool "CP15 based cache enabling support"
169 Select this if your processor suports enabling caches by using
173 bool "MMU-based Paged Memory Management Support"
174 select SYS_ARM_CACHE_CP15
176 Select if you want MMU-based virtualised addressing space
177 support via paged memory management.
180 bool 'Use the ARM v7 PMSA Compliant MPU'
182 Some ARM systems without an MMU have instead a Memory Protection
183 Unit (MPU) that defines the type and permissions for regions of
185 If your CPU has an MPU then you should choose 'y' here unless you
186 know that you do not want to use the MPU.
188 # If set, the workarounds for these ARM errata are applied early during U-Boot
189 # startup. Note that in general these options force the workarounds to be
190 # applied; no CPU-type/version detection exists, unlike the similar options in
191 # the Linux kernel. Do not set these options unless they apply! Also note that
192 # the following can be machine-specific errata. These do have ability to
193 # provide rudimentary version and machine-specific checks, but expect no
195 # CONFIG_ARM_ERRATA_430973
196 # CONFIG_ARM_ERRATA_454179
197 # CONFIG_ARM_ERRATA_621766
198 # CONFIG_ARM_ERRATA_798870
199 # CONFIG_ARM_ERRATA_801819
200 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
201 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
203 config ARM_ERRATA_430973
206 config ARM_ERRATA_454179
209 config ARM_ERRATA_621766
212 config ARM_ERRATA_716044
215 config ARM_ERRATA_725233
218 config ARM_ERRATA_742230
221 config ARM_ERRATA_743622
224 config ARM_ERRATA_751472
227 config ARM_ERRATA_761320
230 config ARM_ERRATA_773022
233 config ARM_ERRATA_774769
236 config ARM_ERRATA_794072
239 config ARM_ERRATA_798870
242 config ARM_ERRATA_801819
245 config ARM_ERRATA_826974
248 config ARM_ERRATA_828024
251 config ARM_ERRATA_829520
254 config ARM_ERRATA_833069
257 config ARM_ERRATA_833471
260 config ARM_ERRATA_845369
263 config ARM_ERRATA_852421
266 config ARM_ERRATA_852423
269 config ARM_ERRATA_855873
272 config ARM_CORTEX_A8_CVE_2017_5715
275 config ARM_CORTEX_A15_CVE_2017_5715
280 select SYS_CACHE_SHIFT_5
285 select SYS_CACHE_SHIFT_5
290 select SYS_CACHE_SHIFT_5
292 imply SPL_SEPARATE_BSS
296 select SYS_CACHE_SHIFT_5
301 select SYS_CACHE_SHIFT_5
303 imply SPL_SEPARATE_BSS
308 select SYS_CACHE_SHIFT_5
315 select SYS_CACHE_SHIFT_6
322 select SYS_CACHE_SHIFT_5
323 select SYS_THUMB_BUILD
329 select SYS_ARM_CACHE_CP15
331 select SYS_CACHE_SHIFT_6
334 default "arm720t" if CPU_ARM720T
335 default "arm920t" if CPU_ARM920T
336 default "arm926ejs" if CPU_ARM926EJS
337 default "arm946es" if CPU_ARM946ES
338 default "arm1136" if CPU_ARM1136
339 default "arm1176" if CPU_ARM1176
340 default "armv7" if CPU_V7A
341 default "armv7" if CPU_V7R
342 default "armv7m" if CPU_V7M
343 default "armv8" if ARM64
347 default 4 if CPU_ARM720T
348 default 4 if CPU_ARM920T
349 default 5 if CPU_ARM926EJS
350 default 5 if CPU_ARM946ES
351 default 6 if CPU_ARM1136
352 default 6 if CPU_ARM1176
359 prompt "Select the ARM data write cache policy"
360 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
361 default SYS_ARM_CACHE_WRITEBACK
363 config SYS_ARM_CACHE_WRITEBACK
364 bool "Write-back (WB)"
366 A write updates the cache only and marks the cache line as dirty.
367 External memory is updated only when the line is evicted or explicitly
370 config SYS_ARM_CACHE_WRITETHROUGH
371 bool "Write-through (WT)"
373 A write updates both the cache and the external memory system.
374 This does not mark the cache line as dirty.
376 config SYS_ARM_CACHE_WRITEALLOC
377 bool "Write allocation (WA)"
379 A cache line is allocated on a write miss. This means that executing a
380 store instruction on the processor might cause a burst read to occur.
381 There is a linefill to obtain the data for the cache line, before the
385 config ARCH_VERY_EARLY_INIT
388 config SPL_ARCH_VERY_EARLY_INIT
392 bool "Enable ARCH_CPU_INIT"
394 Some architectures require a call to arch_cpu_init().
395 Say Y here to enable it
397 config SYS_ARCH_TIMER
398 bool "ARM Generic Timer support"
399 depends on CPU_V7A || ARM64
402 The ARM Generic Timer (aka arch-timer) provides an architected
403 interface to a timer source on an SoC.
404 It is mandatory for ARMv8 implementation and widely available
408 bool "Support for ARM SMC Calling Convention (SMCCC)"
409 depends on CPU_V7A || ARM64
412 Say Y here if you want to enable ARM SMC Calling Convention.
413 This should be enabled if U-Boot needs to communicate with system
414 firmware (for example, PSCI) according to SMCCC.
417 bool "Support ARM semihosting"
419 Semihosting is a method for a target to communicate with a host
420 debugger. It uses special instructions which the debugger will trap
421 on and interpret. This allows U-Boot to read/write files, print to
422 the console, and execute arbitrary commands on the host system.
424 Enabling this option will add support for reading and writing files
425 on the host system. If you don't have a debugger attached then trying
426 to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
428 config SEMIHOSTING_FALLBACK
429 bool "Recover gracefully when semihosting fails"
430 depends on SEMIHOSTING && ARM64
433 Normally, if U-Boot makes a semihosting call and no debugger is
434 attached, then it will panic due to a synchronous abort
435 exception. This config adds an exception handler which will allow
436 U-Boot to recover. Say 'y' if unsure.
438 config SPL_SEMIHOSTING
439 bool "Support ARM semihosting in SPL"
442 Semihosting is a method for a target to communicate with a host
443 debugger. It uses special instructions which the debugger will trap
444 on and interpret. This allows U-Boot to read/write files, print to
445 the console, and execute arbitrary commands on the host system.
447 Enabling this option will add support for reading and writing files
448 on the host system. If you don't have a debugger attached then trying
449 to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
451 config SPL_SEMIHOSTING_FALLBACK
452 bool "Recover gracefully when semihosting fails in SPL"
453 depends on SPL_SEMIHOSTING && ARM64
454 select ARMV8_SPL_EXCEPTION_VECTORS
457 Normally, if U-Boot makes a semihosting call and no debugger is
458 attached, then it will panic due to a synchronous abort
459 exception. This config adds an exception handler which will allow
460 U-Boot to recover. Say 'y' if unsure.
462 config SYS_THUMB_BUILD
463 bool "Build U-Boot using the Thumb instruction set"
466 Use this flag to build U-Boot using the Thumb instruction set for
467 ARM architectures. Thumb instruction set provides better code
468 density. For ARM architectures that support Thumb2 this flag will
469 result in Thumb2 code generated by GCC.
471 config SPL_SYS_THUMB_BUILD
472 bool "Build SPL using the Thumb instruction set"
473 default y if SYS_THUMB_BUILD
474 depends on !ARM64 && SPL
476 Use this flag to build SPL using the Thumb instruction set for
477 ARM architectures. Thumb instruction set provides better code
478 density. For ARM architectures that support Thumb2 this flag will
479 result in Thumb2 code generated by GCC.
481 config TPL_SYS_THUMB_BUILD
482 bool "Build TPL using the Thumb instruction set"
483 default y if SYS_THUMB_BUILD
484 depends on TPL && !ARM64
486 Use this flag to build TPL using the Thumb instruction set for
487 ARM architectures. Thumb instruction set provides better code
488 density. For ARM architectures that support Thumb2 this flag will
489 result in Thumb2 code generated by GCC.
492 bool "ARM PL310 L2 cache controller"
494 Enable support for ARM PL310 L2 cache controller in U-Boot
496 config SPL_SYS_L2_PL310
497 bool "ARM PL310 L2 cache controller in SPL"
499 Enable support for ARM PL310 L2 cache controller in SPL
501 config SYS_L2CACHE_OFF
504 If SoC does not support L2CACHE or one does not want to enable
505 L2CACHE, choose this option.
507 config ENABLE_ARM_SOC_BOOT0_HOOK
508 bool "prepare BOOT0 header"
510 If the SoC's BOOT0 requires a header area filled with (magic)
511 values, then choose this option, and create a file included as
512 <asm/arch/boot0.h> which contains the required assembler code.
514 config USE_ARCH_MEMCPY
515 bool "Use an assembly optimized implementation of memcpy"
517 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
519 Enable the generation of an optimized version of memcpy.
520 Such an implementation may be faster under some conditions
521 but may increase the binary size.
523 config SPL_USE_ARCH_MEMCPY
524 bool "Use an assembly optimized implementation of memcpy for SPL"
525 default y if USE_ARCH_MEMCPY
528 Enable the generation of an optimized version of memcpy.
529 Such an implementation may be faster under some conditions
530 but may increase the binary size.
532 config TPL_USE_ARCH_MEMCPY
533 bool "Use an assembly optimized implementation of memcpy for TPL"
534 default y if USE_ARCH_MEMCPY
537 Enable the generation of an optimized version of memcpy.
538 Such an implementation may be faster under some conditions
539 but may increase the binary size.
541 config USE_ARCH_MEMMOVE
542 bool "Use an assembly optimized implementation of memmove" if !ARM64
543 default USE_ARCH_MEMCPY if ARM64
546 Enable the generation of an optimized version of memmove.
547 Such an implementation may be faster under some conditions
548 but may increase the binary size.
550 config SPL_USE_ARCH_MEMMOVE
551 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
552 default SPL_USE_ARCH_MEMCPY if ARM64
553 depends on SPL && ARM64
555 Enable the generation of an optimized version of memmove.
556 Such an implementation may be faster under some conditions
557 but may increase the binary size.
559 config TPL_USE_ARCH_MEMMOVE
560 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
561 default TPL_USE_ARCH_MEMCPY if ARM64
562 depends on TPL && ARM64
564 Enable the generation of an optimized version of memmove.
565 Such an implementation may be faster under some conditions
566 but may increase the binary size.
568 config USE_ARCH_MEMSET
569 bool "Use an assembly optimized implementation of memset"
571 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
573 Enable the generation of an optimized version of memset.
574 Such an implementation may be faster under some conditions
575 but may increase the binary size.
577 config SPL_USE_ARCH_MEMSET
578 bool "Use an assembly optimized implementation of memset for SPL"
579 default y if USE_ARCH_MEMSET
582 Enable the generation of an optimized version of memset.
583 Such an implementation may be faster under some conditions
584 but may increase the binary size.
586 config TPL_USE_ARCH_MEMSET
587 bool "Use an assembly optimized implementation of memset for TPL"
588 default y if USE_ARCH_MEMSET
591 Enable the generation of an optimized version of memset.
592 Such an implementation may be faster under some conditions
593 but may increase the binary size.
595 config ARM64_SUPPORT_AARCH32
596 bool "ARM64 system support AArch32 execution state"
598 default y if !TARGET_THUNDERX_88XX
600 This ARM64 system supports AArch32 execution state.
603 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
606 prompt "Target select"
611 select GPIO_EXTRA_HEADER
612 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
613 select SPL_SEPARATE_BSS if SPL
618 select GPIO_EXTRA_HEADER
619 select SPL_DM_SPI if SPL
622 Support for TI's DaVinci platform.
625 bool "Marvell Kirkwood"
626 select ARCH_MISC_INIT
627 select BOARD_EARLY_INIT_F
629 select GPIO_EXTRA_HEADER
633 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
639 select GPIO_EXTRA_HEADER
640 select SPL_DM_SPI if SPL
641 select SPL_DM_SPI_FLASH if SPL
642 select SPL_TIMER if SPL
652 select GPIO_EXTRA_HEADER
653 select SPL_SEPARATE_BSS if SPL
656 config TARGET_STV0991
657 bool "Support stv0991"
663 select GPIO_EXTRA_HEADER
670 bool "Broadcom BCM283X family"
674 select GPIO_EXTRA_HEADER
677 select SERIAL_SEARCH_ALL
682 bool "Broadcom BCM63158 family"
688 bool "Broadcom BCM6753 family"
695 bool "Broadcom BCM68360 family"
701 bool "Broadcom BCM6858 family"
707 bool "Broadcom BCM7XXX family"
710 select GPIO_EXTRA_HEADER
713 imply OF_HAS_PRIOR_STAGE
715 This enables support for Broadcom ARM-based set-top box
716 chipsets, including the 7445 family of chips.
719 bool "Broadcom broadband chip family"
723 config TARGET_VEXPRESS_CA9X4
724 bool "Support vexpress_ca9x4"
728 config TARGET_BCMCYGNUS
729 bool "Support bcmcygnus"
731 select GPIO_EXTRA_HEADER
733 imply BCM_SF2_ETH_GMAC
741 bool "Support Broadcom Northstar2"
743 select GPIO_EXTRA_HEADER
745 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
746 ARMv8 Cortex-A57 processors targeting a broad range of networking
750 bool "Support Broadcom NS3"
752 select BOARD_LATE_INIT
754 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
755 ARMv8 Cortex-A72 processors targeting a broad range of networking
759 bool "Samsung EXYNOS"
769 select GPIO_EXTRA_HEADER
770 imply SYS_THUMB_BUILD
775 bool "Samsung S5PC1XX"
781 select GPIO_EXTRA_HEADER
785 bool "Calxeda Highbank"
796 imply OF_HAS_PRIOR_STAGE
798 config ARCH_INTEGRATOR
799 bool "ARM Ltd. Integrator family"
802 select GPIO_EXTRA_HEADER
807 bool "Qualcomm IPQ40xx SoCs"
813 select GPIO_EXTRA_HEADER
827 select SYS_ARCH_TIMER
828 select SYS_THUMB_BUILD
834 bool "Texas Instruments' K3 Architecture"
839 config ARCH_OMAP2PLUS
842 select GPIO_EXTRA_HEADER
843 select SPL_BOARD_INIT if SPL
844 select SPL_STACK_R if SPL
846 imply TI_SYSC if DM && OF_CONTROL
849 imply SPL_SEPARATE_BSS
853 select GPIO_EXTRA_HEADER
854 imply DISTRO_DEFAULTS
857 Support for the Meson SoC family developed by Amlogic Inc.,
858 targeted at media players and tablet computers. We currently
859 support the S905 (GXBaby) 64-bit SoC.
864 select GPIO_EXTRA_HEADER
867 select SPL_LIBCOMMON_SUPPORT if SPL
868 select SPL_LIBGENERIC_SUPPORT if SPL
869 select SPL_OF_CONTROL if SPL
872 Support for the MediaTek SoCs family developed by MediaTek Inc.
873 Please refer to doc/README.mediatek for more information.
876 bool "NXP LPC32xx platform"
881 select GPIO_EXTRA_HEADER
887 bool "NXP i.MX8 platform"
889 select SYS_FSL_HAS_SEC
890 select SYS_FSL_SEC_COMPAT_4
891 select SYS_FSL_SEC_LE
893 select GPIO_EXTRA_HEADER
896 select ENABLE_ARM_SOC_BOOT0_HOOK
900 bool "NXP i.MX8M platform"
902 select GPIO_EXTRA_HEADER
904 select SYS_FSL_HAS_SEC
905 select SYS_FSL_SEC_COMPAT_4
906 select SYS_FSL_SEC_LE
914 bool "NXP i.MX8ULP platform"
920 select GPIO_EXTRA_HEADER
927 bool "NXP i.MX9 platform"
932 select GPIO_EXTRA_HEADER
939 bool "NXP i.MXRT platform"
943 select GPIO_EXTRA_HEADER
949 bool "NXP i.MX23 family"
951 select GPIO_EXTRA_HEADER
957 bool "NXP i.MX28 family"
959 select GPIO_EXTRA_HEADER
965 bool "NXP i.MX31 family"
967 select GPIO_EXTRA_HEADER
972 select BOARD_POSTCLK_INIT
974 select GPIO_EXTRA_HEADER
976 select SYS_FSL_HAS_SEC
977 select SYS_FSL_SEC_COMPAT_4
978 select SYS_FSL_SEC_LE
979 select ROM_UNIFIED_SECTIONS
981 imply SYS_THUMB_BUILD
985 select ARCH_MISC_INIT
987 select GPIO_EXTRA_HEADER
989 select SYS_FSL_HAS_SEC
990 select SYS_FSL_SEC_COMPAT_4
991 select SYS_FSL_SEC_LE
992 imply BOARD_EARLY_INIT_F
994 imply SYS_THUMB_BUILD
998 select BOARD_POSTCLK_INIT
1000 select GPIO_EXTRA_HEADER
1002 select SYS_FSL_HAS_SEC
1003 select SYS_FSL_SEC_COMPAT_4
1004 select SYS_FSL_SEC_LE
1005 select SYS_L2_PL310 if !SYS_L2CACHE_OFF
1007 imply SYS_THUMB_BUILD
1008 imply SPL_SEPARATE_BSS
1011 bool "Freescale MX5"
1012 select BOARD_EARLY_INIT_F
1014 select GPIO_EXTRA_HEADER
1019 bool "Nexell S5P4418/S5P6818 SoC"
1020 select ENABLE_ARM_SOC_BOOT0_HOOK
1022 select GPIO_EXTRA_HEADER
1025 bool "Support Nuvoton SoCs"
1045 select LINUX_KERNEL_IMAGE_HEADER
1046 select OF_BOARD_SETUP
1049 select POSITION_INDEPENDENT
1055 select SYSRESET_WATCHDOG
1056 select SYSRESET_WATCHDOG_AUTO
1060 imply DISTRO_DEFAULTS
1061 imply OF_HAS_PRIOR_STAGE
1064 bool "Actions Semi OWL SoCs"
1068 select GPIO_EXTRA_HEADER
1073 select SYS_RELOC_GD_ENV_ADDR
1077 bool "QEMU Virtual Platform"
1086 imply OF_HAS_PRIOR_STAGE
1089 bool "Renesas ARM SoCs"
1092 select GPIO_EXTRA_HEADER
1093 imply BOARD_EARLY_INIT_F
1096 imply SYS_THUMB_BUILD
1097 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1099 config ARCH_SNAPDRAGON
1100 bool "Qualcomm Snapdragon SoCs"
1105 select GPIO_EXTRA_HEADER
1114 bool "Altera SOCFPGA family"
1115 select ARCH_EARLY_INIT_R
1116 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1117 select ARM64 if TARGET_SOCFPGA_SOC64
1118 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1122 select GPIO_EXTRA_HEADER
1123 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1125 select SPL_DM_RESET if DM_RESET
1126 select SPL_DM_SERIAL
1127 select SPL_LIBCOMMON_SUPPORT
1128 select SPL_LIBGENERIC_SUPPORT
1129 select SPL_OF_CONTROL
1130 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1136 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1138 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1139 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1149 imply SPL_DM_SPI_FLASH
1150 imply SPL_LIBDISK_SUPPORT
1152 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1153 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1154 imply SPL_SPI_FLASH_SUPPORT
1159 bool "Support sunxi (Allwinner) SoCs"
1162 select CMD_MMC if MMC
1163 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1168 select DM_I2C if I2C
1169 select DM_SPI if SPI
1170 select DM_SPI_FLASH if SPI
1172 select DM_MMC if MMC
1173 select DM_SCSI if SCSI
1175 select GPIO_EXTRA_HEADER
1176 select OF_BOARD_SETUP
1180 select SPECIFY_CONSOLE_INDEX
1181 select SPL_SEPARATE_BSS if SPL
1182 select SPL_STACK_R if SPL
1183 select SPL_SYS_MALLOC_SIMPLE if SPL
1184 select SPL_SYS_THUMB_BUILD if !ARM64
1187 select SYS_THUMB_BUILD if !ARM64
1188 select USB if DISTRO_DEFAULTS
1189 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1190 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1191 select SPL_USE_TINY_PRINTF
1193 select SYS_RELOC_GD_ENV_ADDR
1194 imply BOARD_LATE_INIT
1197 imply CMD_UBI if MTD_RAW_NAND
1198 imply DISTRO_DEFAULTS
1201 imply OF_LIBFDT_OVERLAY
1202 imply PRE_CONSOLE_BUFFER
1204 imply SPL_LIBCOMMON_SUPPORT
1205 imply SPL_LIBGENERIC_SUPPORT
1206 imply SPL_MMC if MMC
1210 imply SYSRESET_WATCHDOG
1211 imply SYSRESET_WATCHDOG_AUTO
1216 bool "ST-Ericsson U8500 Series"
1220 select DM_MMC if MMC
1222 select DM_USB_GADGET if DM_USB
1226 imply AB8500_USB_PHY
1227 imply ARM_PL180_MMCI
1232 imply NOMADIK_MTU_TIMER
1237 imply SYS_THUMB_BUILD
1238 imply SYSRESET_SYSCON
1241 bool "Support Xilinx Versal Platform"
1245 select DM_ETH if NET
1246 select DM_MMC if MMC
1251 imply BOARD_LATE_INIT
1252 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1254 config ARCH_VERSAL_NET
1255 bool "Support Xilinx Keystone Platform"
1259 select DM_ETH if NET
1260 select DM_MMC if MMC
1263 imply BOARD_LATE_INIT
1264 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1267 bool "Freescale Vybrid"
1269 select GPIO_EXTRA_HEADER
1271 select SYS_FSL_ERRATUM_ESDHC111
1276 bool "Xilinx Zynq based platform"
1277 select ARM_TWD_TIMER
1281 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1283 select DM_ETH if NET
1284 select DM_MMC if MMC
1290 select SPL_BOARD_INIT if SPL
1291 select SPL_CLK if SPL
1292 select SPL_DM if SPL
1293 select SPL_DM_SPI if SPL
1294 select SPL_DM_SPI_FLASH if SPL
1295 select SPL_OF_CONTROL if SPL
1296 select SPL_SEPARATE_BSS if SPL
1297 select SPL_TIMER if SPL
1300 imply ARCH_EARLY_INIT_R
1301 imply BOARD_LATE_INIT
1305 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1308 config ARCH_ZYNQMP_R5
1309 bool "Xilinx ZynqMP R5 based platform"
1313 select DM_ETH if NET
1314 select DM_MMC if MMC
1321 bool "Xilinx ZynqMP based platform"
1325 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1326 select DM_ETH if NET
1328 select DM_MMC if MMC
1330 select DM_SPI if SPI
1331 select DM_SPI_FLASH if DM_SPI
1335 select SPL_BOARD_INIT if SPL
1336 select SPL_CLK if SPL
1337 select SPL_DM if SPL
1338 select SPL_DM_SPI if SPI && SPL_DM
1339 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1340 select SPL_DM_MAILBOX if SPL
1341 imply SPL_FIRMWARE if SPL
1342 select SPL_SEPARATE_BSS if SPL
1346 imply BOARD_LATE_INIT
1348 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1352 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1356 select GPIO_EXTRA_HEADER
1357 imply DISTRO_DEFAULTS
1360 config ARCH_VEXPRESS64
1361 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1369 select MTD_NOR_FLASH if MTD
1370 select FLASH_CFI_DRIVER if MTD
1371 select ENV_IS_IN_FLASH if MTD
1372 imply DISTRO_DEFAULTS
1374 config TARGET_CORSTONE1000
1375 bool "Support Corstone1000 Platform"
1380 config TARGET_TOTAL_COMPUTE
1381 bool "Support Total Compute Platform"
1389 config TARGET_LS2080A_EMU
1390 bool "Support ls2080a_emu"
1393 select ARMV8_MULTIENTRY
1394 select FSL_DDR_SYNC_REFRESH
1395 select GPIO_EXTRA_HEADER
1397 Support for Freescale LS2080A_EMU platform.
1398 The LS2080A Development System (EMULATOR) is a pre-silicon
1399 development platform that supports the QorIQ LS2080A
1400 Layerscape Architecture processor.
1402 config TARGET_LS1088AQDS
1403 bool "Support ls1088aqds"
1406 select ARMV8_MULTIENTRY
1407 select ARCH_SUPPORT_TFABOOT
1408 select BOARD_LATE_INIT
1409 select GPIO_EXTRA_HEADER
1411 select FSL_DDR_INTERACTIVE if !SD_BOOT
1413 Support for NXP LS1088AQDS platform.
1414 The LS1088A Development System (QDS) is a high-performance
1415 development platform that supports the QorIQ LS1088A
1416 Layerscape Architecture processor.
1418 config TARGET_LS2080AQDS
1419 bool "Support ls2080aqds"
1422 select ARMV8_MULTIENTRY
1423 select ARCH_SUPPORT_TFABOOT
1424 select BOARD_LATE_INIT
1425 select GPIO_EXTRA_HEADER
1430 select FSL_DDR_INTERACTIVE if !SPL
1432 Support for Freescale LS2080AQDS platform.
1433 The LS2080A Development System (QDS) is a high-performance
1434 development platform that supports the QorIQ LS2080A
1435 Layerscape Architecture processor.
1437 config TARGET_LS2080ARDB
1438 bool "Support ls2080ardb"
1441 select ARMV8_MULTIENTRY
1442 select ARCH_SUPPORT_TFABOOT
1443 select BOARD_LATE_INIT
1446 select FSL_DDR_INTERACTIVE if !SPL
1447 select GPIO_EXTRA_HEADER
1451 Support for Freescale LS2080ARDB platform.
1452 The LS2080A Reference design board (RDB) is a high-performance
1453 development platform that supports the QorIQ LS2080A
1454 Layerscape Architecture processor.
1456 config TARGET_LS2081ARDB
1457 bool "Support ls2081ardb"
1460 select ARMV8_MULTIENTRY
1461 select BOARD_LATE_INIT
1462 select GPIO_EXTRA_HEADER
1465 Support for Freescale LS2081ARDB platform.
1466 The LS2081A Reference design board (RDB) is a high-performance
1467 development platform that supports the QorIQ LS2081A/LS2041A
1468 Layerscape Architecture processor.
1470 config TARGET_LX2160ARDB
1471 bool "Support lx2160ardb"
1474 select ARMV8_MULTIENTRY
1475 select ARCH_SUPPORT_TFABOOT
1476 select BOARD_LATE_INIT
1477 select GPIO_EXTRA_HEADER
1479 Support for NXP LX2160ARDB platform.
1480 The lx2160ardb (LX2160A Reference design board (RDB)
1481 is a high-performance development platform that supports the
1482 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1484 config TARGET_LX2160AQDS
1485 bool "Support lx2160aqds"
1488 select ARMV8_MULTIENTRY
1489 select ARCH_SUPPORT_TFABOOT
1490 select BOARD_LATE_INIT
1491 select GPIO_EXTRA_HEADER
1493 Support for NXP LX2160AQDS platform.
1494 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1495 is a high-performance development platform that supports the
1496 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1498 config TARGET_LX2162AQDS
1499 bool "Support lx2162aqds"
1501 select ARCH_MISC_INIT
1503 select ARMV8_MULTIENTRY
1504 select ARCH_SUPPORT_TFABOOT
1505 select BOARD_LATE_INIT
1506 select GPIO_EXTRA_HEADER
1508 Support for NXP LX2162AQDS platform.
1509 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1512 bool "Support HiKey 96boards Consumer Edition Platform"
1517 select GPIO_EXTRA_HEADER
1520 select SPECIFY_CONSOLE_INDEX
1523 Support for HiKey 96boards platform. It features a HI6220
1524 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1526 config TARGET_HIKEY960
1527 bool "Support HiKey960 96boards Consumer Edition Platform"
1531 select GPIO_EXTRA_HEADER
1536 Support for HiKey960 96boards platform. It features a HI3660
1537 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1539 config TARGET_POPLAR
1540 bool "Support Poplar 96boards Enterprise Edition Platform"
1544 select GPIO_EXTRA_HEADER
1549 Support for Poplar 96boards EE platform. It features a HI3798cv200
1550 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1551 making it capable of running any commercial set-top solution based on
1554 config TARGET_LS1012AQDS
1555 bool "Support ls1012aqds"
1558 select ARCH_SUPPORT_TFABOOT
1559 select BOARD_LATE_INIT
1560 select GPIO_EXTRA_HEADER
1562 Support for Freescale LS1012AQDS platform.
1563 The LS1012A Development System (QDS) is a high-performance
1564 development platform that supports the QorIQ LS1012A
1565 Layerscape Architecture processor.
1567 config TARGET_LS1012ARDB
1568 bool "Support ls1012ardb"
1571 select ARCH_SUPPORT_TFABOOT
1572 select BOARD_LATE_INIT
1573 select GPIO_EXTRA_HEADER
1577 Support for Freescale LS1012ARDB platform.
1578 The LS1012A Reference design board (RDB) is a high-performance
1579 development platform that supports the QorIQ LS1012A
1580 Layerscape Architecture processor.
1582 config TARGET_LS1012A2G5RDB
1583 bool "Support ls1012a2g5rdb"
1586 select ARCH_SUPPORT_TFABOOT
1587 select BOARD_LATE_INIT
1588 select GPIO_EXTRA_HEADER
1591 Support for Freescale LS1012A2G5RDB platform.
1592 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1593 development platform that supports the QorIQ LS1012A
1594 Layerscape Architecture processor.
1596 config TARGET_LS1012AFRWY
1597 bool "Support ls1012afrwy"
1600 select ARCH_SUPPORT_TFABOOT
1601 select BOARD_LATE_INIT
1602 select GPIO_EXTRA_HEADER
1606 Support for Freescale LS1012AFRWY platform.
1607 The LS1012A FRWY board (FRWY) is a high-performance
1608 development platform that supports the QorIQ LS1012A
1609 Layerscape Architecture processor.
1611 config TARGET_LS1012AFRDM
1612 bool "Support ls1012afrdm"
1615 select ARCH_SUPPORT_TFABOOT
1616 select GPIO_EXTRA_HEADER
1618 Support for Freescale LS1012AFRDM platform.
1619 The LS1012A Freedom board (FRDM) is a high-performance
1620 development platform that supports the QorIQ LS1012A
1621 Layerscape Architecture processor.
1623 config TARGET_LS1028AQDS
1624 bool "Support ls1028aqds"
1627 select ARMV8_MULTIENTRY
1628 select ARCH_SUPPORT_TFABOOT
1629 select BOARD_LATE_INIT
1630 select GPIO_EXTRA_HEADER
1632 Support for Freescale LS1028AQDS platform
1633 The LS1028A Development System (QDS) is a high-performance
1634 development platform that supports the QorIQ LS1028A
1635 Layerscape Architecture processor.
1637 config TARGET_LS1028ARDB
1638 bool "Support ls1028ardb"
1641 select ARMV8_MULTIENTRY
1642 select ARCH_SUPPORT_TFABOOT
1643 select BOARD_LATE_INIT
1644 select GPIO_EXTRA_HEADER
1646 Support for Freescale LS1028ARDB platform
1647 The LS1028A Development System (RDB) is a high-performance
1648 development platform that supports the QorIQ LS1028A
1649 Layerscape Architecture processor.
1651 config TARGET_LS1088ARDB
1652 bool "Support ls1088ardb"
1655 select ARMV8_MULTIENTRY
1656 select ARCH_SUPPORT_TFABOOT
1657 select BOARD_LATE_INIT
1659 select FSL_DDR_INTERACTIVE if !SD_BOOT
1660 select GPIO_EXTRA_HEADER
1662 Support for NXP LS1088ARDB platform.
1663 The LS1088A Reference design board (RDB) is a high-performance
1664 development platform that supports the QorIQ LS1088A
1665 Layerscape Architecture processor.
1667 config TARGET_LS1021AQDS
1668 bool "Support ls1021aqds"
1670 select ARCH_SUPPORT_PSCI
1671 select BOARD_EARLY_INIT_F
1672 select BOARD_LATE_INIT
1674 select CPU_V7_HAS_NONSEC
1675 select CPU_V7_HAS_VIRT
1676 select LS1_DEEP_SLEEP
1679 select FSL_DDR_INTERACTIVE
1680 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1681 select GPIO_EXTRA_HEADER
1682 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1685 config TARGET_LS1021ATWR
1686 bool "Support ls1021atwr"
1688 select ARCH_SUPPORT_PSCI
1689 select BOARD_EARLY_INIT_F
1690 select BOARD_LATE_INIT
1692 select CPU_V7_HAS_NONSEC
1693 select CPU_V7_HAS_VIRT
1694 select LS1_DEEP_SLEEP
1696 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1697 select GPIO_EXTRA_HEADER
1700 config TARGET_PG_WCOM_SELI8
1701 bool "Support Hitachi-Powergrids SELI8 service unit card"
1703 select ARCH_SUPPORT_PSCI
1704 select BOARD_EARLY_INIT_F
1705 select BOARD_LATE_INIT
1707 select CPU_V7_HAS_NONSEC
1708 select CPU_V7_HAS_VIRT
1710 select FSL_DDR_INTERACTIVE
1711 select GPIO_EXTRA_HEADER
1715 Support for Hitachi-Powergrids SELI8 service unit card.
1716 SELI8 is a QorIQ LS1021a based service unit card used
1717 in XMC20 and FOX615 product families.
1719 config TARGET_PG_WCOM_EXPU1
1720 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1722 select ARCH_SUPPORT_PSCI
1723 select BOARD_EARLY_INIT_F
1724 select BOARD_LATE_INIT
1726 select CPU_V7_HAS_NONSEC
1727 select CPU_V7_HAS_VIRT
1729 select FSL_DDR_INTERACTIVE
1733 Support for Hitachi-Powergrids EXPU1 service unit card.
1734 EXPU1 is a QorIQ LS1021a based service unit card used
1735 in XMC20 and FOX615 product families.
1737 config TARGET_LS1021ATSN
1738 bool "Support ls1021atsn"
1740 select ARCH_SUPPORT_PSCI
1741 select BOARD_EARLY_INIT_F
1742 select BOARD_LATE_INIT
1744 select CPU_V7_HAS_NONSEC
1745 select CPU_V7_HAS_VIRT
1746 select LS1_DEEP_SLEEP
1748 select GPIO_EXTRA_HEADER
1751 config TARGET_LS1021AIOT
1752 bool "Support ls1021aiot"
1754 select ARCH_SUPPORT_PSCI
1755 select BOARD_LATE_INIT
1757 select CPU_V7_HAS_NONSEC
1758 select CPU_V7_HAS_VIRT
1760 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1761 select GPIO_EXTRA_HEADER
1764 Support for Freescale LS1021AIOT platform.
1765 The LS1021A Freescale board (IOT) is a high-performance
1766 development platform that supports the QorIQ LS1021A
1767 Layerscape Architecture processor.
1769 config TARGET_LS1043AQDS
1770 bool "Support ls1043aqds"
1773 select ARMV8_MULTIENTRY
1774 select ARCH_SUPPORT_TFABOOT
1775 select BOARD_EARLY_INIT_F
1776 select BOARD_LATE_INIT
1778 select FSL_DDR_INTERACTIVE if !SPL
1779 select FSL_DSPI if !SPL_NO_DSPI
1780 select DM_SPI_FLASH if FSL_DSPI
1781 select GPIO_EXTRA_HEADER
1785 Support for Freescale LS1043AQDS platform.
1787 config TARGET_LS1043ARDB
1788 bool "Support ls1043ardb"
1791 select ARMV8_MULTIENTRY
1792 select ARCH_SUPPORT_TFABOOT
1793 select BOARD_EARLY_INIT_F
1794 select BOARD_LATE_INIT
1796 select FSL_DSPI if !SPL_NO_DSPI
1797 select DM_SPI_FLASH if FSL_DSPI
1798 select GPIO_EXTRA_HEADER
1800 Support for Freescale LS1043ARDB platform.
1802 config TARGET_LS1046AQDS
1803 bool "Support ls1046aqds"
1806 select ARMV8_MULTIENTRY
1807 select ARCH_SUPPORT_TFABOOT
1808 select BOARD_EARLY_INIT_F
1809 select BOARD_LATE_INIT
1810 select DM_SPI_FLASH if DM_SPI
1812 select FSL_DDR_BIST if !SPL
1813 select FSL_DDR_INTERACTIVE if !SPL
1814 select FSL_DDR_INTERACTIVE if !SPL
1815 select GPIO_EXTRA_HEADER
1818 Support for Freescale LS1046AQDS platform.
1819 The LS1046A Development System (QDS) is a high-performance
1820 development platform that supports the QorIQ LS1046A
1821 Layerscape Architecture processor.
1823 config TARGET_LS1046ARDB
1824 bool "Support ls1046ardb"
1827 select ARMV8_MULTIENTRY
1828 select ARCH_SUPPORT_TFABOOT
1829 select BOARD_EARLY_INIT_F
1830 select BOARD_LATE_INIT
1831 select DM_SPI_FLASH if DM_SPI
1832 select POWER_MC34VR500
1835 select FSL_DDR_INTERACTIVE if !SPL
1836 select GPIO_EXTRA_HEADER
1839 Support for Freescale LS1046ARDB platform.
1840 The LS1046A Reference Design Board (RDB) is a high-performance
1841 development platform that supports the QorIQ LS1046A
1842 Layerscape Architecture processor.
1844 config TARGET_LS1046AFRWY
1845 bool "Support ls1046afrwy"
1848 select ARMV8_MULTIENTRY
1849 select ARCH_SUPPORT_TFABOOT
1850 select BOARD_EARLY_INIT_F
1851 select BOARD_LATE_INIT
1852 select DM_SPI_FLASH if DM_SPI
1853 select GPIO_EXTRA_HEADER
1856 Support for Freescale LS1046AFRWY platform.
1857 The LS1046A Freeway Board (FRWY) is a high-performance
1858 development platform that supports the QorIQ LS1046A
1859 Layerscape Architecture processor.
1865 select ARMV8_MULTIENTRY
1881 select GPIO_EXTRA_HEADER
1882 select SPL_DM if SPL
1883 select SPL_DM_SPI if SPL
1884 select SPL_DM_SPI_FLASH if SPL
1885 select SPL_DM_I2C if SPL
1886 select SPL_DM_MMC if SPL
1887 select SPL_DM_SERIAL if SPL
1889 Support for Kontron SMARC-sAL28 board.
1892 bool "Support ten64"
1894 select ARCH_MISC_INIT
1896 select ARMV8_MULTIENTRY
1897 select ARCH_SUPPORT_TFABOOT
1898 select BOARD_LATE_INIT
1900 select FSL_DDR_INTERACTIVE if !SD_BOOT
1901 select GPIO_EXTRA_HEADER
1903 Support for Traverse Technologies Ten64 board, based
1906 config ARCH_UNIPHIER
1907 bool "Socionext UniPhier SoCs"
1908 select BOARD_LATE_INIT
1917 select OF_BOARD_SETUP
1921 select SPL_BOARD_INIT if SPL
1922 select SPL_DM if SPL
1923 select SPL_LIBCOMMON_SUPPORT if SPL
1924 select SPL_LIBGENERIC_SUPPORT if SPL
1925 select SPL_OF_CONTROL if SPL
1926 select SPL_PINCTRL if SPL
1929 imply DISTRO_DEFAULTS
1932 Support for UniPhier SoC family developed by Socionext Inc.
1933 (formerly, System LSI Business Division of Panasonic Corporation)
1935 config ARCH_SYNQUACER
1936 bool "Socionext SynQuacer SoCs"
1942 select SYSRESET_PSCI
1945 Support for SynQuacer SoC family developed by Socionext Inc.
1946 This SoC is used on 96boards EE DeveloperBox.
1949 bool "Support STMicroelectronics STM32 MCU with cortex M"
1956 bool "Support STMicroelectronics SoCs"
1965 Support for STMicroelectronics STiH407/10 SoC family.
1966 This SoC is used on Linaro 96Board STiH410-B2260
1969 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1970 select ARCH_MISC_INIT
1971 select ARCH_SUPPORT_TFABOOT
1972 select BOARD_LATE_INIT
1981 select OF_SYSTEM_SETUP
1986 select SYS_THUMB_BUILD
1990 imply OF_LIBFDT_OVERLAY
1991 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1995 Support for STM32MP SoC family developed by STMicroelectronics,
1996 MPUs based on ARM cortex A core
1997 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1998 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
2000 SPL is the unsecure FSBL for the basic boot chain.
2002 config ARCH_ROCKCHIP
2003 bool "Support Rockchip SoCs"
2005 select BINMAN if SPL_OPTEE || SPL
2015 select ENABLE_ARM_SOC_BOOT0_HOOK
2018 select SPL_DM if SPL
2019 select SPL_DM_SPI if SPL
2020 select SPL_DM_SPI_FLASH if SPL
2022 select SYS_THUMB_BUILD if !ARM64
2025 imply DEBUG_UART_BOARD_INIT
2026 imply DISTRO_DEFAULTS
2028 imply SARADC_ROCKCHIP
2030 imply SPL_SYS_MALLOC_SIMPLE
2033 imply USB_FUNCTION_FASTBOOT
2035 config ARCH_OCTEONTX
2036 bool "Support OcteonTX SoCs"
2039 select GPIO_EXTRA_HEADER
2043 select BOARD_LATE_INIT
2044 select SYS_CACHE_SHIFT_7
2045 select SYS_PCI_64BIT if PCI
2046 imply OF_HAS_PRIOR_STAGE
2048 config ARCH_OCTEONTX2
2049 bool "Support OcteonTX2 SoCs"
2052 select GPIO_EXTRA_HEADER
2056 select BOARD_LATE_INIT
2057 select SYS_CACHE_SHIFT_7
2058 select SYS_PCI_64BIT if PCI
2059 imply OF_HAS_PRIOR_STAGE
2061 config TARGET_THUNDERX_88XX
2062 bool "Support ThunderX 88xx"
2064 select GPIO_EXTRA_HEADER
2067 select SYS_CACHE_SHIFT_7
2070 bool "Support Aspeed SoCs"
2075 config TARGET_DURIAN
2076 bool "Support Phytium Durian Platform"
2078 select GPIO_EXTRA_HEADER
2080 Support for durian platform.
2081 It has 2GB Sdram, uart and pcie.
2083 config TARGET_POMELO
2084 bool "Support Phytium Pomelo Platform"
2096 select DM_ETH if NET
2099 Support for pomelo platform.
2100 It has 8GB Sdram, uart and pcie.
2102 config TARGET_PRESIDIO_ASIC
2103 bool "Support Cortina Presidio ASIC Platform"
2107 config TARGET_XENGUEST_ARM64
2108 bool "Xen guest ARM64"
2112 select LINUX_KERNEL_IMAGE_HEADER
2115 imply OF_HAS_PRIOR_STAGE
2118 bool "Support HPE GXP SoCs"
2125 config SUPPORT_PASSING_ATAGS
2126 bool "Support pre-devicetree ATAG-based booting"
2128 imply SETUP_MEMORY_TAGS
2130 Support for booting older Linux kernels, using ATAGs rather than
2131 passing a devicetree. This is option is rarely used, and the
2132 semantics are defined at
2133 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2135 config SETUP_MEMORY_TAGS
2136 bool "Pass memory size information via ATAG"
2137 depends on SUPPORT_PASSING_ATAGS
2140 bool "Pass Linux kernel cmdline via ATAG"
2141 depends on SUPPORT_PASSING_ATAGS
2144 bool "Pass initrd starting point and size via ATAG"
2145 depends on SUPPORT_PASSING_ATAGS
2148 bool "Pass system revision via ATAG"
2149 depends on SUPPORT_PASSING_ATAGS
2152 bool "Pass system serial number via ATAG"
2153 depends on SUPPORT_PASSING_ATAGS
2155 config STATIC_MACH_TYPE
2156 bool "Statically define the Machine ID number"
2157 default y if TARGET_DS109 || TARGET_NOKIA_RX51 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2159 When booting via ATAGs, enable this option if we know the correct
2160 machine ID number to use at compile time. Some systems will be
2161 passed the number dynamically by whatever loads U-Boot.
2164 int "Machine ID number"
2165 depends on STATIC_MACH_TYPE
2166 default 527 if TARGET_DS109
2167 default 1955 if TARGET_NOKIA_RX51
2168 default 3036 if TARGET_DS414
2169 default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2171 When booting via ATAGs, the machine type must be passed as a number.
2172 For the full list see https://www.arm.linux.org.uk/developer/machines
2174 config ARCH_SUPPORT_TFABOOT
2178 bool "Support for booting from TF-A"
2179 depends on ARCH_SUPPORT_TFABOOT
2181 Some platforms support the setup of secure registers (for instance
2182 for CPU errata handling) or provide secure services like PSCI.
2183 Those services could also be provided by other firmware parts
2184 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2185 does not need to (and cannot) execute this code.
2186 Enabling this option will make a U-Boot binary that is relying
2187 on other firmware layers to provide secure functionality.
2189 config TI_SECURE_DEVICE
2190 bool "HS Device Type Support"
2191 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2193 If a high secure (HS) device type is being used, this config
2194 must be set. This option impacts various aspects of the
2195 build system (to create signed boot images that can be
2196 authenticated) and the code. See the doc/README.ti-secure
2197 file for further details.
2199 config SYS_KWD_CONFIG
2200 string "kwbimage config file path"
2201 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2202 default "arch/arm/mach-mvebu/kwbimage.cfg"
2204 Path within the source directory to the kwbimage.cfg file to use
2205 when packaging the U-Boot image for use.
2207 source "arch/arm/mach-apple/Kconfig"
2209 source "arch/arm/mach-aspeed/Kconfig"
2211 source "arch/arm/mach-at91/Kconfig"
2213 source "arch/arm/mach-bcm283x/Kconfig"
2215 source "arch/arm/mach-bcmbca/Kconfig"
2217 source "arch/arm/mach-bcmstb/Kconfig"
2219 source "arch/arm/mach-davinci/Kconfig"
2221 source "arch/arm/mach-exynos/Kconfig"
2223 source "arch/arm/mach-hpe/gxp/Kconfig"
2225 source "arch/arm/mach-highbank/Kconfig"
2227 source "arch/arm/mach-integrator/Kconfig"
2229 source "arch/arm/mach-ipq40xx/Kconfig"
2231 source "arch/arm/mach-k3/Kconfig"
2233 source "arch/arm/mach-keystone/Kconfig"
2235 source "arch/arm/mach-kirkwood/Kconfig"
2237 source "arch/arm/mach-lpc32xx/Kconfig"
2239 source "arch/arm/mach-mvebu/Kconfig"
2241 source "arch/arm/mach-octeontx/Kconfig"
2243 source "arch/arm/mach-octeontx2/Kconfig"
2245 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2247 source "arch/arm/mach-imx/mx3/Kconfig"
2249 source "arch/arm/mach-imx/mx5/Kconfig"
2251 source "arch/arm/mach-imx/mx6/Kconfig"
2253 source "arch/arm/mach-imx/mx7/Kconfig"
2255 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2257 source "arch/arm/mach-imx/imx8/Kconfig"
2259 source "arch/arm/mach-imx/imx8m/Kconfig"
2261 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2263 source "arch/arm/mach-imx/imx9/Kconfig"
2265 source "arch/arm/mach-imx/imxrt/Kconfig"
2267 source "arch/arm/mach-imx/mxs/Kconfig"
2269 source "arch/arm/mach-omap2/Kconfig"
2271 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2273 source "arch/arm/mach-orion5x/Kconfig"
2275 source "arch/arm/mach-owl/Kconfig"
2277 source "arch/arm/mach-rmobile/Kconfig"
2279 source "arch/arm/mach-meson/Kconfig"
2281 source "arch/arm/mach-mediatek/Kconfig"
2283 source "arch/arm/mach-qemu/Kconfig"
2285 source "arch/arm/mach-rockchip/Kconfig"
2287 source "arch/arm/mach-s5pc1xx/Kconfig"
2289 source "arch/arm/mach-snapdragon/Kconfig"
2291 source "arch/arm/mach-socfpga/Kconfig"
2293 source "arch/arm/mach-sti/Kconfig"
2295 source "arch/arm/mach-stm32/Kconfig"
2297 source "arch/arm/mach-stm32mp/Kconfig"
2299 source "arch/arm/mach-sunxi/Kconfig"
2301 source "arch/arm/mach-tegra/Kconfig"
2303 source "arch/arm/mach-u8500/Kconfig"
2305 source "arch/arm/mach-uniphier/Kconfig"
2307 source "arch/arm/cpu/armv7/vf610/Kconfig"
2309 source "arch/arm/mach-zynq/Kconfig"
2311 source "arch/arm/mach-zynqmp/Kconfig"
2313 source "arch/arm/mach-versal/Kconfig"
2315 source "arch/arm/mach-versal-net/Kconfig"
2317 source "arch/arm/mach-zynqmp-r5/Kconfig"
2319 source "arch/arm/cpu/armv7/Kconfig"
2321 source "arch/arm/cpu/armv8/Kconfig"
2323 source "arch/arm/mach-imx/Kconfig"
2325 source "arch/arm/mach-nexell/Kconfig"
2327 source "arch/arm/mach-npcm/Kconfig"
2329 source "board/armltd/total_compute/Kconfig"
2330 source "board/armltd/corstone1000/Kconfig"
2331 source "board/bosch/shc/Kconfig"
2332 source "board/bosch/guardian/Kconfig"
2333 source "board/Marvell/octeontx/Kconfig"
2334 source "board/Marvell/octeontx2/Kconfig"
2335 source "board/armltd/vexpress/Kconfig"
2336 source "board/armltd/vexpress64/Kconfig"
2337 source "board/cortina/presidio-asic/Kconfig"
2338 source "board/broadcom/bcm963158/Kconfig"
2339 source "board/broadcom/bcm96753ref/Kconfig"
2340 source "board/broadcom/bcm968360bg/Kconfig"
2341 source "board/broadcom/bcm968580xref/Kconfig"
2342 source "board/broadcom/bcmns3/Kconfig"
2343 source "board/cavium/thunderx/Kconfig"
2344 source "board/eets/pdu001/Kconfig"
2345 source "board/emulation/qemu-arm/Kconfig"
2346 source "board/freescale/ls2080aqds/Kconfig"
2347 source "board/freescale/ls2080ardb/Kconfig"
2348 source "board/freescale/ls1088a/Kconfig"
2349 source "board/freescale/ls1028a/Kconfig"
2350 source "board/freescale/ls1021aqds/Kconfig"
2351 source "board/freescale/ls1043aqds/Kconfig"
2352 source "board/freescale/ls1021atwr/Kconfig"
2353 source "board/freescale/ls1021atsn/Kconfig"
2354 source "board/freescale/ls1021aiot/Kconfig"
2355 source "board/freescale/ls1046aqds/Kconfig"
2356 source "board/freescale/ls1043ardb/Kconfig"
2357 source "board/freescale/ls1046ardb/Kconfig"
2358 source "board/freescale/ls1046afrwy/Kconfig"
2359 source "board/freescale/ls1012aqds/Kconfig"
2360 source "board/freescale/ls1012ardb/Kconfig"
2361 source "board/freescale/ls1012afrdm/Kconfig"
2362 source "board/freescale/lx2160a/Kconfig"
2363 source "board/grinn/chiliboard/Kconfig"
2364 source "board/hisilicon/hikey/Kconfig"
2365 source "board/hisilicon/hikey960/Kconfig"
2366 source "board/hisilicon/poplar/Kconfig"
2367 source "board/isee/igep003x/Kconfig"
2368 source "board/kontron/sl28/Kconfig"
2369 source "board/myir/mys_6ulx/Kconfig"
2370 source "board/siemens/common/Kconfig"
2371 source "board/seeed/npi_imx6ull/Kconfig"
2372 source "board/socionext/developerbox/Kconfig"
2373 source "board/st/stv0991/Kconfig"
2374 source "board/tcl/sl50/Kconfig"
2375 source "board/traverse/ten64/Kconfig"
2376 source "board/variscite/dart_6ul/Kconfig"
2377 source "board/vscom/baltos/Kconfig"
2378 source "board/phytium/durian/Kconfig"
2379 source "board/phytium/pomelo/Kconfig"
2380 source "board/xen/xenguest_arm64/Kconfig"
2382 source "arch/arm/Kconfig.debug"