4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_SUPPORTS_ATOMIC_RMW
10 select ARCH_USE_BUILTIN_BSWAP
11 select ARCH_USE_CMPXCHG_LOCKREF
12 select ARCH_WANT_IPC_PARSE_VERSION
13 select BUILDTIME_EXTABLE_SORT if MMU
14 select CLONE_BACKWARDS
15 select CPU_PM if (SUSPEND || CPU_IDLE)
16 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
17 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
18 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_IRQ_PROBE
21 select GENERIC_IRQ_SHOW
22 select GENERIC_PCI_IOMAP
23 select GENERIC_SCHED_CLOCK
24 select GENERIC_SMP_IDLE_THREAD
25 select GENERIC_STRNCPY_FROM_USER
26 select GENERIC_STRNLEN_USER
27 select HARDIRQS_SW_RESEND
28 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
30 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
31 select HAVE_ARCH_TRACEHOOK
33 select HAVE_CONTEXT_TRACKING
34 select HAVE_C_RECORDMCOUNT
35 select HAVE_CC_STACKPROTECTOR
36 select HAVE_DEBUG_KMEMLEAK
37 select HAVE_DMA_API_DEBUG
39 select HAVE_DMA_CONTIGUOUS if MMU
40 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
41 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
42 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
43 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
44 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
45 select HAVE_GENERIC_DMA_COHERENT
46 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
47 select HAVE_IDE if PCI || ISA || PCMCIA
48 select HAVE_IRQ_TIME_ACCOUNTING
49 select HAVE_KERNEL_GZIP
50 select HAVE_KERNEL_LZ4
51 select HAVE_KERNEL_LZMA
52 select HAVE_KERNEL_LZO
54 select HAVE_KPROBES if !XIP_KERNEL
55 select HAVE_KRETPROBES if (HAVE_KPROBES)
57 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
58 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
59 select HAVE_PERF_EVENTS
61 select HAVE_PERF_USER_STACK_DUMP
62 select HAVE_REGS_AND_STACK_ACCESS_API
63 select HAVE_SYSCALL_TRACEPOINTS
65 select HAVE_VIRT_CPU_ACCOUNTING_GEN
66 select IRQ_FORCED_THREADING
68 select MODULES_USE_ELF_REL
71 select OLD_SIGSUSPEND3
72 select PERF_USE_VMALLOC
74 select SYS_SUPPORTS_APM_EMULATION
75 # Above selects are sorted alphabetically; please add new ones
76 # according to that. Thanks.
78 The ARM series is a line of low-power-consumption RISC chip designs
79 licensed by ARM Ltd and targeted at embedded applications and
80 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
81 manufactured, but legacy ARM-based PC hardware remains popular in
82 Europe. There is an ARM Linux project with a web page at
83 <http://www.arm.linux.org.uk/>.
85 config ARM_HAS_SG_CHAIN
88 config NEED_SG_DMA_LENGTH
91 config ARM_DMA_USE_IOMMU
93 select ARM_HAS_SG_CHAIN
94 select NEED_SG_DMA_LENGTH
98 config ARM_DMA_IOMMU_ALIGNMENT
99 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
103 DMA mapping framework by default aligns all buffers to the smallest
104 PAGE_SIZE order which is greater than or equal to the requested buffer
105 size. This works well for buffers up to a few hundreds kilobytes, but
106 for larger buffers it just a waste of address space. Drivers which has
107 relatively small addressing window (like 64Mib) might run out of
108 virtual space with just a few allocations.
110 With this parameter you can specify the maximum PAGE_SIZE order for
111 DMA IOMMU buffers. Larger buffers will be aligned only to this
112 specified order. The order is expressed as a power of two multiplied
120 config MIGHT_HAVE_PCI
123 config SYS_SUPPORTS_APM_EMULATION
128 select GENERIC_ALLOCATOR
139 The Extended Industry Standard Architecture (EISA) bus was
140 developed as an open alternative to the IBM MicroChannel bus.
142 The EISA bus provided some of the features of the IBM MicroChannel
143 bus while maintaining backward compatibility with cards made for
144 the older ISA bus. The EISA bus saw limited use between 1988 and
145 1995 when it was made obsolete by the PCI bus.
147 Say Y here if you are building a kernel for an EISA-based machine.
154 config STACKTRACE_SUPPORT
158 config HAVE_LATENCYTOP_SUPPORT
163 config LOCKDEP_SUPPORT
167 config TRACE_IRQFLAGS_SUPPORT
171 config RWSEM_GENERIC_SPINLOCK
175 config RWSEM_XCHGADD_ALGORITHM
178 config ARCH_HAS_ILOG2_U32
181 config ARCH_HAS_ILOG2_U64
184 config ARCH_HAS_CPUFREQ
187 Internal node to signify that the ARCH has CPUFREQ support
188 and that the relevant menu configurations are displayed for
191 config ARCH_HAS_BANDGAP
194 config GENERIC_HWEIGHT
198 config GENERIC_CALIBRATE_DELAY
202 config ARCH_MAY_HAVE_PC_FDC
208 config NEED_DMA_MAP_STATE
211 config ARCH_HAS_DMA_SET_COHERENT_MASK
214 config GENERIC_ISA_DMA
220 config NEED_RET_TO_USER
228 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
229 default DRAM_BASE if REMAP_VECTORS_TO_RAM
232 The base address of exception vectors. This must be two pages
235 config ARM_PATCH_PHYS_VIRT
236 bool "Patch physical to virtual translations at runtime" if EMBEDDED
238 depends on !XIP_KERNEL && MMU
239 depends on !ARCH_REALVIEW || !SPARSEMEM
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 16MB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_GPIO_H
255 Select this when mach/gpio.h is required to provide special
256 definitions for this platform. The need for mach/gpio.h should
257 be avoided when possible.
259 config NEED_MACH_IO_H
262 Select this when mach/io.h is required to provide special
263 definitions for this platform. The need for mach/io.h should
264 be avoided when possible.
266 config NEED_MACH_MEMORY_H
269 Select this when mach/memory.h is required to provide special
270 definitions for this platform. The need for mach/memory.h should
271 be avoided when possible.
274 hex "Physical address of main memory" if MMU
275 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
276 default DRAM_BASE if !MMU
278 Please provide the physical address corresponding to the
279 location of main memory in your system.
285 source "init/Kconfig"
287 source "kernel/Kconfig.freezer"
292 bool "MMU-based Paged Memory Management Support"
295 Select if you want MMU-based virtualised addressing space
296 support by paged memory management. If unsure, say 'Y'.
299 # The "ARM system type" choice list is ordered alphabetically by option
300 # text. Please add new entries in the option alphabetic order.
303 prompt "ARM system type"
304 default ARCH_VERSATILE if !MMU
305 default ARCH_MULTIPLATFORM if MMU
307 config ARCH_MULTIPLATFORM
308 bool "Allow multiple platforms to be selected"
310 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_PATCH_PHYS_VIRT
314 select GENERIC_CLOCKEVENTS
315 select MIGHT_HAVE_PCI
316 select MULTI_IRQ_HANDLER
320 config ARCH_INTEGRATOR
321 bool "ARM Ltd. Integrator family"
322 select ARCH_HAS_CPUFREQ
324 select ARM_PATCH_PHYS_VIRT
327 select COMMON_CLK_VERSATILE
328 select GENERIC_CLOCKEVENTS
331 select MULTI_IRQ_HANDLER
332 select NEED_MACH_MEMORY_H
333 select PLAT_VERSATILE
336 select VERSATILE_FPGA_IRQ
338 Support for ARM's Integrator platform.
341 bool "ARM Ltd. RealView family"
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_TIMER_SP804
346 select COMMON_CLK_VERSATILE
347 select GENERIC_CLOCKEVENTS
348 select GPIO_PL061 if GPIOLIB
350 select NEED_MACH_MEMORY_H
351 select PLAT_VERSATILE
352 select PLAT_VERSATILE_CLCD
354 This enables support for ARM Ltd RealView boards.
356 config ARCH_VERSATILE
357 bool "ARM Ltd. Versatile family"
358 select ARCH_WANT_OPTIONAL_GPIOLIB
360 select ARM_TIMER_SP804
363 select GENERIC_CLOCKEVENTS
364 select HAVE_MACH_CLKDEV
366 select PLAT_VERSATILE
367 select PLAT_VERSATILE_CLCD
368 select PLAT_VERSATILE_CLOCK
369 select VERSATILE_FPGA_IRQ
371 This enables support for ARM Ltd Versatile board.
375 select ARCH_REQUIRE_GPIOLIB
378 select NEED_MACH_GPIO_H
379 select NEED_MACH_IO_H if PCCARD
381 select PINCTRL_AT91 if USE_OF
383 This enables support for systems based on Atmel
384 AT91RM9200 and AT91SAM9* processors.
387 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
388 select ARCH_REQUIRE_GPIOLIB
393 select GENERIC_CLOCKEVENTS
395 select MULTI_IRQ_HANDLER
398 Support for Cirrus Logic 711x/721x/731x based boards.
401 bool "Cortina Systems Gemini"
402 select ARCH_REQUIRE_GPIOLIB
405 select GENERIC_CLOCKEVENTS
407 Support for the Cortina Systems Gemini family SoCs
411 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_IO_H
415 select NEED_MACH_MEMORY_H
418 This is an evaluation board for the StrongARM processor available
419 from Digital. It has limited hardware on-board, including an
420 Ethernet interface, two PCMCIA sockets, two serial ports and a
424 bool "Energy Micro efm32"
426 select ARCH_REQUIRE_GPIOLIB
428 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
429 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
434 select GENERIC_CLOCKEVENTS
440 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
445 select ARCH_HAS_HOLES_MEMORYMODEL
446 select ARCH_REQUIRE_GPIOLIB
447 select ARCH_USES_GETTIMEOFFSET
452 select NEED_MACH_MEMORY_H
454 This enables support for the Cirrus EP93xx series of CPUs.
456 config ARCH_FOOTBRIDGE
460 select GENERIC_CLOCKEVENTS
462 select NEED_MACH_IO_H if !MMU
463 select NEED_MACH_MEMORY_H
465 Support for systems based on the DC21285 companion chip
466 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
469 bool "Hilscher NetX based"
473 select GENERIC_CLOCKEVENTS
475 This enables support for systems based on the Hilscher NetX Soc
481 select NEED_MACH_MEMORY_H
482 select NEED_RET_TO_USER
487 Support for Intel's IOP13XX (XScale) family of processors.
492 select ARCH_REQUIRE_GPIOLIB
495 select NEED_RET_TO_USER
499 Support for Intel's 80219 and IOP32X (XScale) family of
505 select ARCH_REQUIRE_GPIOLIB
508 select NEED_RET_TO_USER
512 Support for Intel's IOP33X (XScale) family of processors.
517 select ARCH_HAS_DMA_SET_COHERENT_MASK
518 select ARCH_SUPPORTS_BIG_ENDIAN
519 select ARCH_REQUIRE_GPIOLIB
522 select DMABOUNCE if PCI
523 select GENERIC_CLOCKEVENTS
524 select MIGHT_HAVE_PCI
525 select NEED_MACH_IO_H
526 select USB_EHCI_BIG_ENDIAN_DESC
527 select USB_EHCI_BIG_ENDIAN_MMIO
529 Support for Intel's IXP4XX (XScale) family of processors.
533 select ARCH_REQUIRE_GPIOLIB
535 select GENERIC_CLOCKEVENTS
536 select MIGHT_HAVE_PCI
540 select PLAT_ORION_LEGACY
542 Support for the Marvell Dove SoC 88AP510
545 bool "Marvell Kirkwood"
546 select ARCH_HAS_CPUFREQ
547 select ARCH_REQUIRE_GPIOLIB
549 select GENERIC_CLOCKEVENTS
554 select PINCTRL_KIRKWOOD
555 select PLAT_ORION_LEGACY
557 Support for the following Marvell Kirkwood series SoCs:
558 88F6180, 88F6192 and 88F6281.
561 bool "Marvell MV78xx0"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
567 select PLAT_ORION_LEGACY
569 Support for the following Marvell MV78xx0 series SoCs:
575 select ARCH_REQUIRE_GPIOLIB
577 select GENERIC_CLOCKEVENTS
580 select PLAT_ORION_LEGACY
582 Support for the following Marvell Orion 5x series SoCs:
583 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
584 Orion-2 (5281), Orion-1-90 (6183).
587 bool "Marvell PXA168/910/MMP2"
589 select ARCH_REQUIRE_GPIOLIB
591 select GENERIC_ALLOCATOR
592 select GENERIC_CLOCKEVENTS
595 select MULTI_IRQ_HANDLER
600 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
603 bool "Micrel/Kendin KS8695"
604 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
608 select NEED_MACH_MEMORY_H
610 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
611 System-on-Chip devices.
614 bool "Nuvoton W90X900 CPU"
615 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
621 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
622 At present, the w90x900 has been renamed nuc900, regarding
623 the ARM series product line, you can login the following
624 link address to know more.
626 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
627 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
631 select ARCH_REQUIRE_GPIOLIB
636 select GENERIC_CLOCKEVENTS
641 Support for the NXP LPC32XX family of processors
644 bool "PXA2xx/PXA3xx-based"
646 select ARCH_HAS_CPUFREQ
648 select ARCH_REQUIRE_GPIOLIB
649 select ARM_CPU_SUSPEND if PM
653 select GENERIC_CLOCKEVENTS
656 select MULTI_IRQ_HANDLER
660 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
665 select ARCH_REQUIRE_GPIOLIB
667 select GENERIC_CLOCKEVENTS
669 Support for Qualcomm MSM/QSD based systems. This runs on the
670 apps processor of the MSM/QSD and depends on a shared memory
671 interface to the modem processor which runs the baseband
672 stack and controls some vital subsystems
673 (clock and power control, etc).
675 config ARCH_SHMOBILE_LEGACY
676 bool "Renesas ARM SoCs (non-multiplatform)"
678 select ARM_PATCH_PHYS_VIRT
681 select GENERIC_CLOCKEVENTS
682 select HAVE_ARM_SCU if SMP
683 select HAVE_ARM_TWD if SMP
684 select HAVE_MACH_CLKDEV
686 select MIGHT_HAVE_CACHE_L2X0
687 select MULTI_IRQ_HANDLER
690 select PM_GENERIC_DOMAINS if PM
693 Support for Renesas ARM SoC platforms using a non-multiplatform
694 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
700 select ARCH_MAY_HAVE_PC_FDC
701 select ARCH_SPARSEMEM_ENABLE
702 select ARCH_USES_GETTIMEOFFSET
705 select HAVE_PATA_PLATFORM
707 select NEED_MACH_IO_H
708 select NEED_MACH_MEMORY_H
712 On the Acorn Risc-PC, Linux can support the internal IDE disk and
713 CD-ROM interface, serial and parallel port, and the floppy drive.
717 select ARCH_HAS_CPUFREQ
719 select ARCH_REQUIRE_GPIOLIB
720 select ARCH_SPARSEMEM_ENABLE
725 select GENERIC_CLOCKEVENTS
728 select NEED_MACH_MEMORY_H
731 Support for StrongARM 11x0 based boards.
734 bool "Samsung S3C24XX SoCs"
735 select ARCH_HAS_CPUFREQ
736 select ARCH_REQUIRE_GPIOLIB
738 select CLKSRC_SAMSUNG_PWM
739 select GENERIC_CLOCKEVENTS
741 select HAVE_S3C2410_I2C if I2C
742 select HAVE_S3C2410_WATCHDOG if WATCHDOG
743 select HAVE_S3C_RTC if RTC_CLASS
744 select MULTI_IRQ_HANDLER
745 select NEED_MACH_IO_H
748 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
749 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
750 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
751 Samsung SMDK2410 development board (and derivatives).
754 bool "Samsung S3C64XX"
755 select ARCH_HAS_CPUFREQ
756 select ARCH_REQUIRE_GPIOLIB
760 select CLKSRC_SAMSUNG_PWM
763 select GENERIC_CLOCKEVENTS
765 select HAVE_S3C2410_I2C if I2C
766 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 select PM_GENERIC_DOMAINS
772 select S3C_GPIO_TRACK
774 select SAMSUNG_WAKEMASK
775 select SAMSUNG_WDT_RESET
777 Samsung S3C64XX series based systems
780 bool "Samsung S5P6440 S5P6450"
782 select CLKSRC_SAMSUNG_PWM
784 select GENERIC_CLOCKEVENTS
786 select HAVE_S3C2410_I2C if I2C
787 select HAVE_S3C2410_WATCHDOG if WATCHDOG
788 select HAVE_S3C_RTC if RTC_CLASS
789 select NEED_MACH_GPIO_H
791 select SAMSUNG_WDT_RESET
793 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
797 bool "Samsung S5PC100"
798 select ARCH_REQUIRE_GPIOLIB
800 select CLKSRC_SAMSUNG_PWM
802 select GENERIC_CLOCKEVENTS
804 select HAVE_S3C2410_I2C if I2C
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select HAVE_S3C_RTC if RTC_CLASS
807 select NEED_MACH_GPIO_H
809 select SAMSUNG_WDT_RESET
811 Samsung S5PC100 series based systems
814 bool "Samsung S5PV210/S5PC110"
815 select ARCH_HAS_CPUFREQ
816 select ARCH_HAS_HOLES_MEMORYMODEL
817 select ARCH_SPARSEMEM_ENABLE
819 select CLKSRC_SAMSUNG_PWM
821 select GENERIC_CLOCKEVENTS
823 select HAVE_S3C2410_I2C if I2C
824 select HAVE_S3C2410_WATCHDOG if WATCHDOG
825 select HAVE_S3C_RTC if RTC_CLASS
826 select NEED_MACH_GPIO_H
827 select NEED_MACH_MEMORY_H
830 Samsung S5PV210/S5PC110 series based systems
833 bool "Samsung EXYNOS"
834 select ARCH_HAS_CPUFREQ
835 select ARCH_HAS_HOLES_MEMORYMODEL
836 select ARCH_REQUIRE_GPIOLIB
837 select ARCH_SPARSEMEM_ENABLE
841 select GENERIC_CLOCKEVENTS
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C2410_WATCHDOG if WATCHDOG
844 select HAVE_S3C_RTC if RTC_CLASS
845 select NEED_MACH_MEMORY_H
849 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
853 select ARCH_HAS_HOLES_MEMORYMODEL
854 select ARCH_REQUIRE_GPIOLIB
856 select GENERIC_ALLOCATOR
857 select GENERIC_CLOCKEVENTS
858 select GENERIC_IRQ_CHIP
864 Support for TI's DaVinci platform.
869 select ARCH_HAS_CPUFREQ
870 select ARCH_HAS_HOLES_MEMORYMODEL
872 select ARCH_REQUIRE_GPIOLIB
875 select GENERIC_CLOCKEVENTS
876 select GENERIC_IRQ_CHIP
879 select NEED_MACH_IO_H if PCCARD
880 select NEED_MACH_MEMORY_H
882 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
886 menu "Multiple platform selection"
887 depends on ARCH_MULTIPLATFORM
889 comment "CPU Core family selection"
891 config ARCH_MULTI_V4T
892 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
893 depends on !ARCH_MULTI_V6_V7
894 select ARCH_MULTI_V4_V5
895 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
896 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
897 CPU_ARM925T || CPU_ARM940T)
900 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
901 depends on !ARCH_MULTI_V6_V7
902 select ARCH_MULTI_V4_V5
903 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
904 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
905 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
907 config ARCH_MULTI_V4_V5
911 bool "ARMv6 based platforms (ARM11)"
912 select ARCH_MULTI_V6_V7
916 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
918 select ARCH_MULTI_V6_V7
922 config ARCH_MULTI_V6_V7
924 select MIGHT_HAVE_CACHE_L2X0
926 config ARCH_MULTI_CPU_AUTO
927 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
933 # This is sorted alphabetically by mach-* pathname. However, plat-*
934 # Kconfigs may be included either alphabetically (according to the
935 # plat- suffix) or along side the corresponding mach-* source.
937 source "arch/arm/mach-mvebu/Kconfig"
939 source "arch/arm/mach-at91/Kconfig"
941 source "arch/arm/mach-bcm/Kconfig"
943 source "arch/arm/mach-bcm2835/Kconfig"
945 source "arch/arm/mach-berlin/Kconfig"
947 source "arch/arm/mach-clps711x/Kconfig"
949 source "arch/arm/mach-cns3xxx/Kconfig"
951 source "arch/arm/mach-davinci/Kconfig"
953 source "arch/arm/mach-dove/Kconfig"
955 source "arch/arm/mach-ep93xx/Kconfig"
957 source "arch/arm/mach-footbridge/Kconfig"
959 source "arch/arm/mach-gemini/Kconfig"
961 source "arch/arm/mach-highbank/Kconfig"
963 source "arch/arm/mach-hisi/Kconfig"
965 source "arch/arm/mach-integrator/Kconfig"
967 source "arch/arm/mach-iop32x/Kconfig"
969 source "arch/arm/mach-iop33x/Kconfig"
971 source "arch/arm/mach-iop13xx/Kconfig"
973 source "arch/arm/mach-ixp4xx/Kconfig"
975 source "arch/arm/mach-keystone/Kconfig"
977 source "arch/arm/mach-kirkwood/Kconfig"
979 source "arch/arm/mach-ks8695/Kconfig"
981 source "arch/arm/mach-msm/Kconfig"
983 source "arch/arm/mach-moxart/Kconfig"
985 source "arch/arm/mach-mv78xx0/Kconfig"
987 source "arch/arm/mach-imx/Kconfig"
989 source "arch/arm/mach-mxs/Kconfig"
991 source "arch/arm/mach-netx/Kconfig"
993 source "arch/arm/mach-nomadik/Kconfig"
995 source "arch/arm/mach-nspire/Kconfig"
997 source "arch/arm/plat-omap/Kconfig"
999 source "arch/arm/mach-omap1/Kconfig"
1001 source "arch/arm/mach-omap2/Kconfig"
1003 source "arch/arm/mach-orion5x/Kconfig"
1005 source "arch/arm/mach-picoxcell/Kconfig"
1007 source "arch/arm/mach-pxa/Kconfig"
1008 source "arch/arm/plat-pxa/Kconfig"
1010 source "arch/arm/mach-mmp/Kconfig"
1012 source "arch/arm/mach-realview/Kconfig"
1014 source "arch/arm/mach-rockchip/Kconfig"
1016 source "arch/arm/mach-sa1100/Kconfig"
1018 source "arch/arm/plat-samsung/Kconfig"
1020 source "arch/arm/mach-socfpga/Kconfig"
1022 source "arch/arm/mach-spear/Kconfig"
1024 source "arch/arm/mach-sti/Kconfig"
1026 source "arch/arm/mach-s3c24xx/Kconfig"
1028 source "arch/arm/mach-s3c64xx/Kconfig"
1030 source "arch/arm/mach-s5p64x0/Kconfig"
1032 source "arch/arm/mach-s5pc100/Kconfig"
1034 source "arch/arm/mach-s5pv210/Kconfig"
1036 source "arch/arm/mach-exynos/Kconfig"
1038 source "arch/arm/mach-shmobile/Kconfig"
1040 source "arch/arm/mach-sunxi/Kconfig"
1042 source "arch/arm/mach-prima2/Kconfig"
1044 source "arch/arm/mach-tegra/Kconfig"
1046 source "arch/arm/mach-u300/Kconfig"
1048 source "arch/arm/mach-ux500/Kconfig"
1050 source "arch/arm/mach-versatile/Kconfig"
1052 source "arch/arm/mach-vexpress/Kconfig"
1053 source "arch/arm/plat-versatile/Kconfig"
1055 source "arch/arm/mach-virt/Kconfig"
1057 source "arch/arm/mach-vt8500/Kconfig"
1059 source "arch/arm/mach-w90x900/Kconfig"
1061 source "arch/arm/mach-zynq/Kconfig"
1063 # Definitions to make life easier
1069 select GENERIC_CLOCKEVENTS
1075 select GENERIC_IRQ_CHIP
1078 config PLAT_ORION_LEGACY
1085 config PLAT_VERSATILE
1088 config ARM_TIMER_SP804
1091 select CLKSRC_OF if OF
1093 source "arch/arm/firmware/Kconfig"
1095 source arch/arm/mm/Kconfig
1099 default 16 if ARCH_EP93XX
1103 bool "Enable iWMMXt support" if !CPU_PJ4
1104 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1105 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1107 Enable support for iWMMXt context switching at run time if
1108 running on a CPU that supports it.
1110 config MULTI_IRQ_HANDLER
1113 Allow each machine to specify it's own IRQ handler at run time.
1116 source "arch/arm/Kconfig-nommu"
1119 config PJ4B_ERRATA_4742
1120 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1121 depends on CPU_PJ4B && MACH_ARMADA_370
1124 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1125 Event (WFE) IDLE states, a specific timing sensitivity exists between
1126 the retiring WFI/WFE instructions and the newly issued subsequent
1127 instructions. This sensitivity can result in a CPU hang scenario.
1129 The software must insert either a Data Synchronization Barrier (DSB)
1130 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1133 config ARM_ERRATA_326103
1134 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1137 Executing a SWP instruction to read-only memory does not set bit 11
1138 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1139 treat the access as a read, preventing a COW from occurring and
1140 causing the faulting task to livelock.
1142 config ARM_ERRATA_411920
1143 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1144 depends on CPU_V6 || CPU_V6K
1146 Invalidation of the Instruction Cache operation can
1147 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1148 It does not affect the MPCore. This option enables the ARM Ltd.
1149 recommended workaround.
1151 config ARM_ERRATA_430973
1152 bool "ARM errata: Stale prediction on replaced interworking branch"
1155 This option enables the workaround for the 430973 Cortex-A8
1156 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1157 interworking branch is replaced with another code sequence at the
1158 same virtual address, whether due to self-modifying code or virtual
1159 to physical address re-mapping, Cortex-A8 does not recover from the
1160 stale interworking branch prediction. This results in Cortex-A8
1161 executing the new code sequence in the incorrect ARM or Thumb state.
1162 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1163 and also flushes the branch target cache at every context switch.
1164 Note that setting specific bits in the ACTLR register may not be
1165 available in non-secure mode.
1167 config ARM_ERRATA_458693
1168 bool "ARM errata: Processor deadlock when a false hazard is created"
1170 depends on !ARCH_MULTIPLATFORM
1172 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1173 erratum. For very specific sequences of memory operations, it is
1174 possible for a hazard condition intended for a cache line to instead
1175 be incorrectly associated with a different cache line. This false
1176 hazard might then cause a processor deadlock. The workaround enables
1177 the L1 caching of the NEON accesses and disables the PLD instruction
1178 in the ACTLR register. Note that setting specific bits in the ACTLR
1179 register may not be available in non-secure mode.
1181 config ARM_ERRATA_460075
1182 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1184 depends on !ARCH_MULTIPLATFORM
1186 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1187 erratum. Any asynchronous access to the L2 cache may encounter a
1188 situation in which recent store transactions to the L2 cache are lost
1189 and overwritten with stale memory contents from external memory. The
1190 workaround disables the write-allocate mode for the L2 cache via the
1191 ACTLR register. Note that setting specific bits in the ACTLR register
1192 may not be available in non-secure mode.
1194 config ARM_ERRATA_742230
1195 bool "ARM errata: DMB operation may be faulty"
1196 depends on CPU_V7 && SMP
1197 depends on !ARCH_MULTIPLATFORM
1199 This option enables the workaround for the 742230 Cortex-A9
1200 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1201 between two write operations may not ensure the correct visibility
1202 ordering of the two writes. This workaround sets a specific bit in
1203 the diagnostic register of the Cortex-A9 which causes the DMB
1204 instruction to behave as a DSB, ensuring the correct behaviour of
1207 config ARM_ERRATA_742231
1208 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1209 depends on CPU_V7 && SMP
1210 depends on !ARCH_MULTIPLATFORM
1212 This option enables the workaround for the 742231 Cortex-A9
1213 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1214 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1215 accessing some data located in the same cache line, may get corrupted
1216 data due to bad handling of the address hazard when the line gets
1217 replaced from one of the CPUs at the same time as another CPU is
1218 accessing it. This workaround sets specific bits in the diagnostic
1219 register of the Cortex-A9 which reduces the linefill issuing
1220 capabilities of the processor.
1222 config PL310_ERRATA_588369
1223 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1224 depends on CACHE_L2X0
1226 The PL310 L2 cache controller implements three types of Clean &
1227 Invalidate maintenance operations: by Physical Address
1228 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1229 They are architecturally defined to behave as the execution of a
1230 clean operation followed immediately by an invalidate operation,
1231 both performing to the same memory location. This functionality
1232 is not correctly implemented in PL310 as clean lines are not
1233 invalidated as a result of these operations.
1235 config ARM_ERRATA_643719
1236 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1237 depends on CPU_V7 && SMP
1239 This option enables the workaround for the 643719 Cortex-A9 (prior to
1240 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1241 register returns zero when it should return one. The workaround
1242 corrects this value, ensuring cache maintenance operations which use
1243 it behave as intended and avoiding data corruption.
1245 config ARM_ERRATA_720789
1246 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1249 This option enables the workaround for the 720789 Cortex-A9 (prior to
1250 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1251 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1252 As a consequence of this erratum, some TLB entries which should be
1253 invalidated are not, resulting in an incoherency in the system page
1254 tables. The workaround changes the TLB flushing routines to invalidate
1255 entries regardless of the ASID.
1257 config PL310_ERRATA_727915
1258 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1259 depends on CACHE_L2X0
1261 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1262 operation (offset 0x7FC). This operation runs in background so that
1263 PL310 can handle normal accesses while it is in progress. Under very
1264 rare circumstances, due to this erratum, write data can be lost when
1265 PL310 treats a cacheable write transaction during a Clean &
1266 Invalidate by Way operation.
1268 config ARM_ERRATA_743622
1269 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1271 depends on !ARCH_MULTIPLATFORM
1273 This option enables the workaround for the 743622 Cortex-A9
1274 (r2p*) erratum. Under very rare conditions, a faulty
1275 optimisation in the Cortex-A9 Store Buffer may lead to data
1276 corruption. This workaround sets a specific bit in the diagnostic
1277 register of the Cortex-A9 which disables the Store Buffer
1278 optimisation, preventing the defect from occurring. This has no
1279 visible impact on the overall performance or power consumption of the
1282 config ARM_ERRATA_751472
1283 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1285 depends on !ARCH_MULTIPLATFORM
1287 This option enables the workaround for the 751472 Cortex-A9 (prior
1288 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1289 completion of a following broadcasted operation if the second
1290 operation is received by a CPU before the ICIALLUIS has completed,
1291 potentially leading to corrupted entries in the cache or TLB.
1293 config PL310_ERRATA_753970
1294 bool "PL310 errata: cache sync operation may be faulty"
1295 depends on CACHE_PL310
1297 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1299 Under some condition the effect of cache sync operation on
1300 the store buffer still remains when the operation completes.
1301 This means that the store buffer is always asked to drain and
1302 this prevents it from merging any further writes. The workaround
1303 is to replace the normal offset of cache sync operation (0x730)
1304 by another offset targeting an unmapped PL310 register 0x740.
1305 This has the same effect as the cache sync operation: store buffer
1306 drain and waiting for all buffers empty.
1308 config ARM_ERRATA_754322
1309 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1312 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1313 r3p*) erratum. A speculative memory access may cause a page table walk
1314 which starts prior to an ASID switch but completes afterwards. This
1315 can populate the micro-TLB with a stale entry which may be hit with
1316 the new ASID. This workaround places two dsb instructions in the mm
1317 switching code so that no page table walks can cross the ASID switch.
1319 config ARM_ERRATA_754327
1320 bool "ARM errata: no automatic Store Buffer drain"
1321 depends on CPU_V7 && SMP
1323 This option enables the workaround for the 754327 Cortex-A9 (prior to
1324 r2p0) erratum. The Store Buffer does not have any automatic draining
1325 mechanism and therefore a livelock may occur if an external agent
1326 continuously polls a memory location waiting to observe an update.
1327 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1328 written polling loops from denying visibility of updates to memory.
1330 config ARM_ERRATA_364296
1331 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1334 This options enables the workaround for the 364296 ARM1136
1335 r0p2 erratum (possible cache data corruption with
1336 hit-under-miss enabled). It sets the undocumented bit 31 in
1337 the auxiliary control register and the FI bit in the control
1338 register, thus disabling hit-under-miss without putting the
1339 processor into full low interrupt latency mode. ARM11MPCore
1342 config ARM_ERRATA_764369
1343 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1344 depends on CPU_V7 && SMP
1346 This option enables the workaround for erratum 764369
1347 affecting Cortex-A9 MPCore with two or more processors (all
1348 current revisions). Under certain timing circumstances, a data
1349 cache line maintenance operation by MVA targeting an Inner
1350 Shareable memory region may fail to proceed up to either the
1351 Point of Coherency or to the Point of Unification of the
1352 system. This workaround adds a DSB instruction before the
1353 relevant cache maintenance functions and sets a specific bit
1354 in the diagnostic control register of the SCU.
1356 config PL310_ERRATA_769419
1357 bool "PL310 errata: no automatic Store Buffer drain"
1358 depends on CACHE_L2X0
1360 On revisions of the PL310 prior to r3p2, the Store Buffer does
1361 not automatically drain. This can cause normal, non-cacheable
1362 writes to be retained when the memory system is idle, leading
1363 to suboptimal I/O performance for drivers using coherent DMA.
1364 This option adds a write barrier to the cpu_idle loop so that,
1365 on systems with an outer cache, the store buffer is drained
1368 config ARM_ERRATA_775420
1369 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1372 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1373 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1374 operation aborts with MMU exception, it might cause the processor
1375 to deadlock. This workaround puts DSB before executing ISB if
1376 an abort may occur on cache maintenance.
1378 config ARM_ERRATA_798181
1379 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1380 depends on CPU_V7 && SMP
1382 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1383 adequately shooting down all use of the old entries. This
1384 option enables the Linux kernel workaround for this erratum
1385 which sends an IPI to the CPUs that are running the same ASID
1386 as the one being invalidated.
1388 config ARM_ERRATA_773022
1389 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1392 This option enables the workaround for the 773022 Cortex-A15
1393 (up to r0p4) erratum. In certain rare sequences of code, the
1394 loop buffer may deliver incorrect instructions. This
1395 workaround disables the loop buffer to avoid the erratum.
1399 source "arch/arm/common/Kconfig"
1409 Find out whether you have ISA slots on your motherboard. ISA is the
1410 name of a bus system, i.e. the way the CPU talks to the other stuff
1411 inside your box. Other bus systems are PCI, EISA, MicroChannel
1412 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1413 newer boards don't support it. If you have ISA, say Y, otherwise N.
1415 # Select ISA DMA controller support
1420 # Select ISA DMA interface
1425 bool "PCI support" if MIGHT_HAVE_PCI
1427 Find out whether you have a PCI motherboard. PCI is the name of a
1428 bus system, i.e. the way the CPU talks to the other stuff inside
1429 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1430 VESA. If you have PCI, say Y, otherwise N.
1436 config PCI_NANOENGINE
1437 bool "BSE nanoEngine PCI support"
1438 depends on SA1100_NANOENGINE
1440 Enable PCI on the BSE nanoEngine board.
1445 config PCI_HOST_ITE8152
1447 depends on PCI && MACH_ARMCORE
1451 source "drivers/pci/Kconfig"
1452 source "drivers/pci/pcie/Kconfig"
1454 source "drivers/pcmcia/Kconfig"
1458 menu "Kernel Features"
1463 This option should be selected by machines which have an SMP-
1466 The only effect of this option is to make the SMP-related
1467 options available to the user for configuration.
1470 bool "Symmetric Multi-Processing"
1471 depends on CPU_V6K || CPU_V7
1472 depends on GENERIC_CLOCKEVENTS
1474 depends on MMU || ARM_MPU
1476 This enables support for systems with more than one CPU. If you have
1477 a system with only one CPU, say N. If you have a system with more
1478 than one CPU, say Y.
1480 If you say N here, the kernel will run on uni- and multiprocessor
1481 machines, but will use only one CPU of a multiprocessor machine. If
1482 you say Y here, the kernel will run on many, but not all,
1483 uniprocessor machines. On a uniprocessor machine, the kernel
1484 will run faster if you say N here.
1486 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1487 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1488 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1490 If you don't know what to do here, say N.
1493 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1494 depends on SMP && !XIP_KERNEL && MMU
1497 SMP kernels contain instructions which fail on non-SMP processors.
1498 Enabling this option allows the kernel to modify itself to make
1499 these instructions safe. Disabling it allows about 1K of space
1502 If you don't know what to do here, say Y.
1504 config ARM_CPU_TOPOLOGY
1505 bool "Support cpu topology definition"
1506 depends on SMP && CPU_V7
1509 Support ARM cpu topology definition. The MPIDR register defines
1510 affinity between processors which is then used to describe the cpu
1511 topology of an ARM System.
1514 bool "Multi-core scheduler support"
1515 depends on ARM_CPU_TOPOLOGY
1517 Multi-core scheduler support improves the CPU scheduler's decision
1518 making when dealing with multi-core CPU chips at a cost of slightly
1519 increased overhead in some places. If unsure say N here.
1522 bool "SMT scheduler support"
1523 depends on ARM_CPU_TOPOLOGY
1525 Improves the CPU scheduler's decision making when dealing with
1526 MultiThreading at a cost of slightly increased overhead in some
1527 places. If unsure say N here.
1532 This option enables support for the ARM system coherency unit
1534 config HAVE_ARM_ARCH_TIMER
1535 bool "Architected timer support"
1537 select ARM_ARCH_TIMER
1538 select GENERIC_CLOCKEVENTS
1540 This option enables support for the ARM architected timer
1545 select CLKSRC_OF if OF
1547 This options enables support for the ARM timer and watchdog unit
1550 bool "Multi-Cluster Power Management"
1551 depends on CPU_V7 && SMP
1553 This option provides the common power management infrastructure
1554 for (multi-)cluster based systems, such as big.LITTLE based
1558 bool "big.LITTLE support (Experimental)"
1559 depends on CPU_V7 && SMP
1562 This option enables support selections for the big.LITTLE
1563 system architecture.
1566 bool "big.LITTLE switcher support"
1567 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1569 select ARM_CPU_SUSPEND
1571 The big.LITTLE "switcher" provides the core functionality to
1572 transparently handle transition between a cluster of A15's
1573 and a cluster of A7's in a big.LITTLE system.
1575 config BL_SWITCHER_DUMMY_IF
1576 tristate "Simple big.LITTLE switcher user interface"
1577 depends on BL_SWITCHER && DEBUG_KERNEL
1579 This is a simple and dummy char dev interface to control
1580 the big.LITTLE switcher core code. It is meant for
1581 debugging purposes only.
1584 prompt "Memory split"
1588 Select the desired split between kernel and user memory.
1590 If you are not absolutely sure what you are doing, leave this
1594 bool "3G/1G user/kernel split"
1596 bool "2G/2G user/kernel split"
1598 bool "1G/3G user/kernel split"
1603 default PHYS_OFFSET if !MMU
1604 default 0x40000000 if VMSPLIT_1G
1605 default 0x80000000 if VMSPLIT_2G
1609 int "Maximum number of CPUs (2-32)"
1615 bool "Support for hot-pluggable CPUs"
1618 Say Y here to experiment with turning CPUs off and on. CPUs
1619 can be controlled through /sys/devices/system/cpu.
1622 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1625 Say Y here if you want Linux to communicate with system firmware
1626 implementing the PSCI specification for CPU-centric power
1627 management operations described in ARM document number ARM DEN
1628 0022A ("Power State Coordination Interface System Software on
1631 # The GPIO number here must be sorted by descending number. In case of
1632 # a multiplatform kernel, we just want the highest value required by the
1633 # selected platforms.
1636 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1637 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1638 default 392 if ARCH_U8500
1639 default 352 if ARCH_VT8500
1640 default 288 if ARCH_SUNXI
1641 default 264 if MACH_H4700
1644 Maximum number of GPIOs in the system.
1646 If unsure, leave the default value.
1648 source kernel/Kconfig.preempt
1652 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1653 ARCH_S5PV210 || ARCH_EXYNOS4
1654 default AT91_TIMER_HZ if ARCH_AT91
1655 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1659 depends on HZ_FIXED = 0
1660 prompt "Timer frequency"
1684 default HZ_FIXED if HZ_FIXED != 0
1685 default 100 if HZ_100
1686 default 200 if HZ_200
1687 default 250 if HZ_250
1688 default 300 if HZ_300
1689 default 500 if HZ_500
1693 def_bool HIGH_RES_TIMERS
1695 config THUMB2_KERNEL
1696 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1697 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1698 default y if CPU_THUMBONLY
1700 select ARM_ASM_UNIFIED
1703 By enabling this option, the kernel will be compiled in
1704 Thumb-2 mode. A compiler/assembler that understand the unified
1705 ARM-Thumb syntax is needed.
1709 config THUMB2_AVOID_R_ARM_THM_JUMP11
1710 bool "Work around buggy Thumb-2 short branch relocations in gas"
1711 depends on THUMB2_KERNEL && MODULES
1714 Various binutils versions can resolve Thumb-2 branches to
1715 locally-defined, preemptible global symbols as short-range "b.n"
1716 branch instructions.
1718 This is a problem, because there's no guarantee the final
1719 destination of the symbol, or any candidate locations for a
1720 trampoline, are within range of the branch. For this reason, the
1721 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1722 relocation in modules at all, and it makes little sense to add
1725 The symptom is that the kernel fails with an "unsupported
1726 relocation" error when loading some modules.
1728 Until fixed tools are available, passing
1729 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1730 code which hits this problem, at the cost of a bit of extra runtime
1731 stack usage in some cases.
1733 The problem is described in more detail at:
1734 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1736 Only Thumb-2 kernels are affected.
1738 Unless you are sure your tools don't have this problem, say Y.
1740 config ARM_ASM_UNIFIED
1744 bool "Use the ARM EABI to compile the kernel"
1746 This option allows for the kernel to be compiled using the latest
1747 ARM ABI (aka EABI). This is only useful if you are using a user
1748 space environment that is also compiled with EABI.
1750 Since there are major incompatibilities between the legacy ABI and
1751 EABI, especially with regard to structure member alignment, this
1752 option also changes the kernel syscall calling convention to
1753 disambiguate both ABIs and allow for backward compatibility support
1754 (selected with CONFIG_OABI_COMPAT).
1756 To use this you need GCC version 4.0.0 or later.
1759 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1760 depends on AEABI && !THUMB2_KERNEL
1762 This option preserves the old syscall interface along with the
1763 new (ARM EABI) one. It also provides a compatibility layer to
1764 intercept syscalls that have structure arguments which layout
1765 in memory differs between the legacy ABI and the new ARM EABI
1766 (only for non "thumb" binaries). This option adds a tiny
1767 overhead to all syscalls and produces a slightly larger kernel.
1769 The seccomp filter system will not be available when this is
1770 selected, since there is no way yet to sensibly distinguish
1771 between calling conventions during filtering.
1773 If you know you'll be using only pure EABI user space then you
1774 can say N here. If this option is not selected and you attempt
1775 to execute a legacy ABI binary then the result will be
1776 UNPREDICTABLE (in fact it can be predicted that it won't work
1777 at all). If in doubt say N.
1779 config ARCH_HAS_HOLES_MEMORYMODEL
1782 config ARCH_SPARSEMEM_ENABLE
1785 config ARCH_SPARSEMEM_DEFAULT
1786 def_bool ARCH_SPARSEMEM_ENABLE
1788 config ARCH_SELECT_MEMORY_MODEL
1789 def_bool ARCH_SPARSEMEM_ENABLE
1791 config HAVE_ARCH_PFN_VALID
1792 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1795 bool "High Memory Support"
1798 The address space of ARM processors is only 4 Gigabytes large
1799 and it has to accommodate user address space, kernel address
1800 space as well as some memory mapped IO. That means that, if you
1801 have a large amount of physical memory and/or IO, not all of the
1802 memory can be "permanently mapped" by the kernel. The physical
1803 memory that is not permanently mapped is called "high memory".
1805 Depending on the selected kernel/user memory split, minimum
1806 vmalloc space and actual amount of RAM, you may not need this
1807 option which should result in a slightly faster kernel.
1812 bool "Allocate 2nd-level pagetables from highmem"
1815 config HW_PERF_EVENTS
1816 bool "Enable hardware performance counter support for perf events"
1817 depends on PERF_EVENTS
1820 Enable hardware performance counter support for perf events. If
1821 disabled, perf events will use software events only.
1823 config SYS_SUPPORTS_HUGETLBFS
1827 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1831 config ARCH_WANT_GENERAL_HUGETLB
1836 config FORCE_MAX_ZONEORDER
1837 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1838 range 11 64 if ARCH_SHMOBILE_LEGACY
1839 default "12" if SOC_AM33XX
1840 default "9" if SA1111 || ARCH_EFM32
1843 The kernel memory allocator divides physically contiguous memory
1844 blocks into "zones", where each zone is a power of two number of
1845 pages. This option selects the largest power of two that the kernel
1846 keeps in the memory allocator. If you need to allocate very large
1847 blocks of physically contiguous memory, then you may need to
1848 increase this value.
1850 This config option is actually maximum order plus one. For example,
1851 a value of 11 means that the largest free memory block is 2^10 pages.
1853 config ALIGNMENT_TRAP
1855 depends on CPU_CP15_MMU
1856 default y if !ARCH_EBSA110
1857 select HAVE_PROC_CPU if PROC_FS
1859 ARM processors cannot fetch/store information which is not
1860 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1861 address divisible by 4. On 32-bit ARM processors, these non-aligned
1862 fetch/store instructions will be emulated in software if you say
1863 here, which has a severe performance impact. This is necessary for
1864 correct operation of some network protocols. With an IP-only
1865 configuration it is safe to say N, otherwise say Y.
1867 config UACCESS_WITH_MEMCPY
1868 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1870 default y if CPU_FEROCEON
1872 Implement faster copy_to_user and clear_user methods for CPU
1873 cores where a 8-word STM instruction give significantly higher
1874 memory write throughput than a sequence of individual 32bit stores.
1876 A possible side effect is a slight increase in scheduling latency
1877 between threads sharing the same address space if they invoke
1878 such copy operations with large buffers.
1880 However, if the CPU data cache is using a write-allocate mode,
1881 this option is unlikely to provide any performance gain.
1885 prompt "Enable seccomp to safely compute untrusted bytecode"
1887 This kernel feature is useful for number crunching applications
1888 that may need to compute untrusted bytecode during their
1889 execution. By using pipes or other transports made available to
1890 the process as file descriptors supporting the read/write
1891 syscalls, it's possible to isolate those applications in
1892 their own address space using seccomp. Once seccomp is
1893 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1894 and the task is only allowed to execute a few safe syscalls
1895 defined by each seccomp mode.
1908 bool "Xen guest support on ARM (EXPERIMENTAL)"
1909 depends on ARM && AEABI && OF
1910 depends on CPU_V7 && !CPU_V6
1911 depends on !GENERIC_ATOMIC64
1915 select ARCH_DMA_ADDR_T_64BIT
1917 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1924 bool "Flattened Device Tree support"
1927 select OF_EARLY_FLATTREE
1929 Include support for flattened device tree machine descriptions.
1932 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1935 This is the traditional way of passing data to the kernel at boot
1936 time. If you are solely relying on the flattened device tree (or
1937 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1938 to remove ATAGS support from your kernel binary. If unsure,
1941 config DEPRECATED_PARAM_STRUCT
1942 bool "Provide old way to pass kernel parameters"
1945 This was deprecated in 2001 and announced to live on for 5 years.
1946 Some old boot loaders still use this way.
1948 # Compressed boot loader in ROM. Yes, we really want to ask about
1949 # TEXT and BSS so we preserve their values in the config files.
1950 config ZBOOT_ROM_TEXT
1951 hex "Compressed ROM boot loader base address"
1954 The physical address at which the ROM-able zImage is to be
1955 placed in the target. Platforms which normally make use of
1956 ROM-able zImage formats normally set this to a suitable
1957 value in their defconfig file.
1959 If ZBOOT_ROM is not enabled, this has no effect.
1961 config ZBOOT_ROM_BSS
1962 hex "Compressed ROM boot loader BSS address"
1965 The base address of an area of read/write memory in the target
1966 for the ROM-able zImage which must be available while the
1967 decompressor is running. It must be large enough to hold the
1968 entire decompressed kernel plus an additional 128 KiB.
1969 Platforms which normally make use of ROM-able zImage formats
1970 normally set this to a suitable value in their defconfig file.
1972 If ZBOOT_ROM is not enabled, this has no effect.
1975 bool "Compressed boot loader in ROM/flash"
1976 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1977 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1979 Say Y here if you intend to execute your compressed kernel image
1980 (zImage) directly from ROM or flash. If unsure, say N.
1983 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1984 depends on ZBOOT_ROM && ARCH_SH7372
1985 default ZBOOT_ROM_NONE
1987 Include experimental SD/MMC loading code in the ROM-able zImage.
1988 With this enabled it is possible to write the ROM-able zImage
1989 kernel image to an MMC or SD card and boot the kernel straight
1990 from the reset vector. At reset the processor Mask ROM will load
1991 the first part of the ROM-able zImage which in turn loads the
1992 rest the kernel image to RAM.
1994 config ZBOOT_ROM_NONE
1995 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1997 Do not load image from SD or MMC
1999 config ZBOOT_ROM_MMCIF
2000 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2002 Load image from MMCIF hardware block.
2004 config ZBOOT_ROM_SH_MOBILE_SDHI
2005 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2007 Load image from SDHI hardware block
2011 config ARM_APPENDED_DTB
2012 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2015 With this option, the boot code will look for a device tree binary
2016 (DTB) appended to zImage
2017 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2019 This is meant as a backward compatibility convenience for those
2020 systems with a bootloader that can't be upgraded to accommodate
2021 the documented boot protocol using a device tree.
2023 Beware that there is very little in terms of protection against
2024 this option being confused by leftover garbage in memory that might
2025 look like a DTB header after a reboot if no actual DTB is appended
2026 to zImage. Do not leave this option active in a production kernel
2027 if you don't intend to always append a DTB. Proper passing of the
2028 location into r2 of a bootloader provided DTB is always preferable
2031 config ARM_ATAG_DTB_COMPAT
2032 bool "Supplement the appended DTB with traditional ATAG information"
2033 depends on ARM_APPENDED_DTB
2035 Some old bootloaders can't be updated to a DTB capable one, yet
2036 they provide ATAGs with memory configuration, the ramdisk address,
2037 the kernel cmdline string, etc. Such information is dynamically
2038 provided by the bootloader and can't always be stored in a static
2039 DTB. To allow a device tree enabled kernel to be used with such
2040 bootloaders, this option allows zImage to extract the information
2041 from the ATAG list and store it at run time into the appended DTB.
2044 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2045 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2047 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2048 bool "Use bootloader kernel arguments if available"
2050 Uses the command-line options passed by the boot loader instead of
2051 the device tree bootargs property. If the boot loader doesn't provide
2052 any, the device tree bootargs property will be used.
2054 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2055 bool "Extend with bootloader kernel arguments"
2057 The command-line arguments provided by the boot loader will be
2058 appended to the the device tree bootargs property.
2063 string "Default kernel command string"
2066 On some architectures (EBSA110 and CATS), there is currently no way
2067 for the boot loader to pass arguments to the kernel. For these
2068 architectures, you should supply some command-line options at build
2069 time by entering them here. As a minimum, you should specify the
2070 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2073 prompt "Kernel command line type" if CMDLINE != ""
2074 default CMDLINE_FROM_BOOTLOADER
2077 config CMDLINE_FROM_BOOTLOADER
2078 bool "Use bootloader kernel arguments if available"
2080 Uses the command-line options passed by the boot loader. If
2081 the boot loader doesn't provide any, the default kernel command
2082 string provided in CMDLINE will be used.
2084 config CMDLINE_EXTEND
2085 bool "Extend bootloader kernel arguments"
2087 The command-line arguments provided by the boot loader will be
2088 appended to the default kernel command string.
2090 config CMDLINE_FORCE
2091 bool "Always use the default kernel command string"
2093 Always use the default kernel command string, even if the boot
2094 loader passes other arguments to the kernel.
2095 This is useful if you cannot or don't want to change the
2096 command-line options your boot loader passes to the kernel.
2100 bool "Kernel Execute-In-Place from ROM"
2101 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2103 Execute-In-Place allows the kernel to run from non-volatile storage
2104 directly addressable by the CPU, such as NOR flash. This saves RAM
2105 space since the text section of the kernel is not loaded from flash
2106 to RAM. Read-write sections, such as the data section and stack,
2107 are still copied to RAM. The XIP kernel is not compressed since
2108 it has to run directly from flash, so it will take more space to
2109 store it. The flash address used to link the kernel object files,
2110 and for storing it, is configuration dependent. Therefore, if you
2111 say Y here, you must know the proper physical address where to
2112 store the kernel image depending on your own flash memory usage.
2114 Also note that the make target becomes "make xipImage" rather than
2115 "make zImage" or "make Image". The final kernel binary to put in
2116 ROM memory will be arch/arm/boot/xipImage.
2120 config XIP_PHYS_ADDR
2121 hex "XIP Kernel Physical Location"
2122 depends on XIP_KERNEL
2123 default "0x00080000"
2125 This is the physical address in your flash memory the kernel will
2126 be linked for and stored to. This address is dependent on your
2130 bool "Kexec system call (EXPERIMENTAL)"
2131 depends on (!SMP || PM_SLEEP_SMP)
2133 kexec is a system call that implements the ability to shutdown your
2134 current kernel, and to start another kernel. It is like a reboot
2135 but it is independent of the system firmware. And like a reboot
2136 you can start any kernel with it, not just Linux.
2138 It is an ongoing process to be certain the hardware in a machine
2139 is properly shutdown, so do not be surprised if this code does not
2140 initially work for you.
2143 bool "Export atags in procfs"
2144 depends on ATAGS && KEXEC
2147 Should the atags used to boot the kernel be exported in an "atags"
2148 file in procfs. Useful with kexec.
2151 bool "Build kdump crash kernel (EXPERIMENTAL)"
2153 Generate crash dump after being started by kexec. This should
2154 be normally only set in special crash dump kernels which are
2155 loaded in the main kernel with kexec-tools into a specially
2156 reserved region and then later executed after a crash by
2157 kdump/kexec. The crash dump kernel must be compiled to a
2158 memory address not used by the main kernel
2160 For more details see Documentation/kdump/kdump.txt
2162 config AUTO_ZRELADDR
2163 bool "Auto calculation of the decompressed kernel image address"
2165 ZRELADDR is the physical address where the decompressed kernel
2166 image will be placed. If AUTO_ZRELADDR is selected, the address
2167 will be determined at run-time by masking the current IP with
2168 0xf8000000. This assumes the zImage being placed in the first 128MB
2169 from start of memory.
2173 menu "CPU Power Management"
2176 source "drivers/cpufreq/Kconfig"
2179 source "drivers/cpuidle/Kconfig"
2183 menu "Floating point emulation"
2185 comment "At least one emulation must be selected"
2188 bool "NWFPE math emulation"
2189 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2191 Say Y to include the NWFPE floating point emulator in the kernel.
2192 This is necessary to run most binaries. Linux does not currently
2193 support floating point hardware so you need to say Y here even if
2194 your machine has an FPA or floating point co-processor podule.
2196 You may say N here if you are going to load the Acorn FPEmulator
2197 early in the bootup.
2200 bool "Support extended precision"
2201 depends on FPE_NWFPE
2203 Say Y to include 80-bit support in the kernel floating-point
2204 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2205 Note that gcc does not generate 80-bit operations by default,
2206 so in most cases this option only enlarges the size of the
2207 floating point emulator without any good reason.
2209 You almost surely want to say N here.
2212 bool "FastFPE math emulation (EXPERIMENTAL)"
2213 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2215 Say Y here to include the FAST floating point emulator in the kernel.
2216 This is an experimental much faster emulator which now also has full
2217 precision for the mantissa. It does not support any exceptions.
2218 It is very simple, and approximately 3-6 times faster than NWFPE.
2220 It should be sufficient for most programs. It may be not suitable
2221 for scientific calculations, but you have to check this for yourself.
2222 If you do not feel you need a faster FP emulation you should better
2226 bool "VFP-format floating point maths"
2227 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2229 Say Y to include VFP support code in the kernel. This is needed
2230 if your hardware includes a VFP unit.
2232 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2233 release notes and additional status information.
2235 Say N if your target does not have VFP hardware.
2243 bool "Advanced SIMD (NEON) Extension support"
2244 depends on VFPv3 && CPU_V7
2246 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2249 config KERNEL_MODE_NEON
2250 bool "Support for NEON in kernel mode"
2251 depends on NEON && AEABI
2253 Say Y to include support for NEON in kernel mode.
2257 menu "Userspace binary formats"
2259 source "fs/Kconfig.binfmt"
2262 tristate "RISC OS personality"
2265 Say Y here to include the kernel code necessary if you want to run
2266 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2267 experimental; if this sounds frightening, say N and sleep in peace.
2268 You can also say M here to compile this support as a module (which
2269 will be called arthur).
2273 menu "Power management options"
2275 source "kernel/power/Kconfig"
2277 config ARCH_SUSPEND_POSSIBLE
2278 depends on !ARCH_S5PC100
2279 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2280 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2283 config ARM_CPU_SUSPEND
2288 source "net/Kconfig"
2290 source "drivers/Kconfig"
2294 source "arch/arm/Kconfig.debug"
2296 source "security/Kconfig"
2298 source "crypto/Kconfig"
2300 source "lib/Kconfig"
2302 source "arch/arm/kvm/Kconfig"