1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
15 select INIT_SP_RELATIVE
17 U-Boot expects to be linked to a specific hard-coded address, and to
18 be loaded to and run from that address. This option lifts that
19 restriction, thus allowing the code to be loaded to and executed
20 from almost any address. This logic relies on the relocation
21 information that is embedded in the binary to support U-Boot
22 relocating itself to the top-of-RAM later during execution.
24 config INIT_SP_RELATIVE
25 bool "Specify the early stack pointer relative to the .bss section"
27 U-Boot typically uses a hard-coded value for the stack pointer
28 before relocation. Enable this option to instead calculate the
29 initial SP at run-time. This is useful to avoid hard-coding addresses
30 into U-Boot, so that it can be loaded and executed at arbitrary
31 addresses and thus avoid using arbitrary addresses at runtime.
33 If this option is enabled, the early stack pointer is set to
34 &_bss_start with a offset value added. The offset is specified by
35 SYS_INIT_SP_BSS_OFFSET.
37 config SYS_INIT_SP_BSS_OFFSET
38 int "Early stack offset from the .bss base address"
39 depends on INIT_SP_RELATIVE
42 This option's value is the offset added to &_bss_start in order to
43 calculate the stack pointer. This offset should be large enough so
44 that the early malloc region, global data (gd), and early stack usage
45 do not overlap any appended DTB.
47 config LINUX_KERNEL_IMAGE_HEADER
50 Place a Linux kernel image header at the start of the U-Boot binary.
51 The format of the header is described in the Linux kernel source at
52 Documentation/arm64/booting.txt. This feature is useful since the
53 image header reports the amount of memory (BSS and similar) that
54 U-Boot needs to use, but which isn't part of the binary.
56 if LINUX_KERNEL_IMAGE_HEADER
57 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
60 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
61 TEXT_OFFSET value written to the Linux kernel image header.
68 ARM GICV3 Interrupt translation service (ITS).
69 Basic support for programming locality specific peripheral
70 interrupts (LPI) configuration tables and enable LPI tables.
71 LPI configuration table can be used by u-boot or Linux.
72 ARM GICV3 has limitation, once the LPI table is enabled, LPI
73 configuration table can not be re-programmed, unless GICV3 reset.
77 default y if ARM64 && !POSITION_INDEPENDENT
79 config DMA_ADDR_T_64BIT
89 # Used for compatibility with asm files copied from the kernel
90 config ARM_ASM_UNIFIED
94 # Used for compatibility with asm files copied from the kernel
99 bool "Do not enable icache"
102 Do not enable instruction cache in U-Boot.
104 config SPL_SYS_ICACHE_OFF
105 bool "Do not enable icache in SPL"
107 default SYS_ICACHE_OFF
109 Do not enable instruction cache in SPL.
111 config SYS_DCACHE_OFF
112 bool "Do not enable dcache"
115 Do not enable data cache in U-Boot.
117 config SPL_SYS_DCACHE_OFF
118 bool "Do not enable dcache in SPL"
120 default SYS_DCACHE_OFF
122 Do not enable data cache in SPL.
124 config SYS_ARM_CACHE_CP15
125 bool "CP15 based cache enabling support"
127 Select this if your processor suports enabling caches by using
131 bool "MMU-based Paged Memory Management Support"
132 select SYS_ARM_CACHE_CP15
134 Select if you want MMU-based virtualised addressing space
135 support via paged memory management.
138 bool 'Use the ARM v7 PMSA Compliant MPU'
140 Some ARM systems without an MMU have instead a Memory Protection
141 Unit (MPU) that defines the type and permissions for regions of
143 If your CPU has an MPU then you should choose 'y' here unless you
144 know that you do not want to use the MPU.
146 # If set, the workarounds for these ARM errata are applied early during U-Boot
147 # startup. Note that in general these options force the workarounds to be
148 # applied; no CPU-type/version detection exists, unlike the similar options in
149 # the Linux kernel. Do not set these options unless they apply! Also note that
150 # the following can be machine-specific errata. These do have ability to
151 # provide rudimentary version and machine-specific checks, but expect no
153 # CONFIG_ARM_ERRATA_430973
154 # CONFIG_ARM_ERRATA_454179
155 # CONFIG_ARM_ERRATA_621766
156 # CONFIG_ARM_ERRATA_798870
157 # CONFIG_ARM_ERRATA_801819
158 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
159 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
161 config ARM_ERRATA_430973
164 config ARM_ERRATA_454179
167 config ARM_ERRATA_621766
170 config ARM_ERRATA_716044
173 config ARM_ERRATA_725233
176 config ARM_ERRATA_742230
179 config ARM_ERRATA_743622
182 config ARM_ERRATA_751472
185 config ARM_ERRATA_761320
188 config ARM_ERRATA_773022
191 config ARM_ERRATA_774769
194 config ARM_ERRATA_794072
197 config ARM_ERRATA_798870
200 config ARM_ERRATA_801819
203 config ARM_ERRATA_826974
206 config ARM_ERRATA_828024
209 config ARM_ERRATA_829520
212 config ARM_ERRATA_833069
215 config ARM_ERRATA_833471
218 config ARM_ERRATA_845369
221 config ARM_ERRATA_852421
224 config ARM_ERRATA_852423
227 config ARM_ERRATA_855873
230 config ARM_CORTEX_A8_CVE_2017_5715
233 config ARM_CORTEX_A15_CVE_2017_5715
238 select SYS_CACHE_SHIFT_5
243 select SYS_CACHE_SHIFT_5
248 select SYS_CACHE_SHIFT_5
253 select SYS_CACHE_SHIFT_5
258 select SYS_CACHE_SHIFT_5
264 select SYS_CACHE_SHIFT_5
271 select SYS_CACHE_SHIFT_6
278 select SYS_CACHE_SHIFT_5
279 select SYS_THUMB_BUILD
285 select SYS_ARM_CACHE_CP15
287 select SYS_CACHE_SHIFT_6
291 select SYS_CACHE_SHIFT_5
296 select SYS_CACHE_SHIFT_5
300 default "arm720t" if CPU_ARM720T
301 default "arm920t" if CPU_ARM920T
302 default "arm926ejs" if CPU_ARM926EJS
303 default "arm946es" if CPU_ARM946ES
304 default "arm1136" if CPU_ARM1136
305 default "arm1176" if CPU_ARM1176
306 default "armv7" if CPU_V7A
307 default "armv7" if CPU_V7R
308 default "armv7m" if CPU_V7M
309 default "pxa" if CPU_PXA
310 default "sa1100" if CPU_SA1100
311 default "armv8" if ARM64
315 default 4 if CPU_ARM720T
316 default 4 if CPU_ARM920T
317 default 5 if CPU_ARM926EJS
318 default 5 if CPU_ARM946ES
319 default 6 if CPU_ARM1136
320 default 6 if CPU_ARM1176
325 default 4 if CPU_SA1100
328 config SYS_CACHE_SHIFT_5
331 config SYS_CACHE_SHIFT_6
334 config SYS_CACHE_SHIFT_7
337 config SYS_CACHELINE_SIZE
339 default 128 if SYS_CACHE_SHIFT_7
340 default 64 if SYS_CACHE_SHIFT_6
341 default 32 if SYS_CACHE_SHIFT_5
344 prompt "Select the ARM data write cache policy"
345 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
346 TARGET_BCMNSP || CPU_PXA || RZA1
347 default SYS_ARM_CACHE_WRITEBACK
349 config SYS_ARM_CACHE_WRITEBACK
350 bool "Write-back (WB)"
352 A write updates the cache only and marks the cache line as dirty.
353 External memory is updated only when the line is evicted or explicitly
356 config SYS_ARM_CACHE_WRITETHROUGH
357 bool "Write-through (WT)"
359 A write updates both the cache and the external memory system.
360 This does not mark the cache line as dirty.
362 config SYS_ARM_CACHE_WRITEALLOC
363 bool "Write allocation (WA)"
365 A cache line is allocated on a write miss. This means that executing a
366 store instruction on the processor might cause a burst read to occur.
367 There is a linefill to obtain the data for the cache line, before the
372 bool "Enable ARCH_CPU_INIT"
374 Some architectures require a call to arch_cpu_init().
375 Say Y here to enable it
377 config SYS_ARCH_TIMER
378 bool "ARM Generic Timer support"
379 depends on CPU_V7A || ARM64
382 The ARM Generic Timer (aka arch-timer) provides an architected
383 interface to a timer source on an SoC.
384 It is mandatory for ARMv8 implementation and widely available
388 bool "Support for ARM SMC Calling Convention (SMCCC)"
389 depends on CPU_V7A || ARM64
392 Say Y here if you want to enable ARM SMC Calling Convention.
393 This should be enabled if U-Boot needs to communicate with system
394 firmware (for example, PSCI) according to SMCCC.
397 bool "support boot from semihosting"
399 In emulated environments, semihosting is a way for
400 the hosted environment to call out to the emulator to
401 retrieve files from the host machine.
403 config SYS_THUMB_BUILD
404 bool "Build U-Boot using the Thumb instruction set"
407 Use this flag to build U-Boot using the Thumb instruction set for
408 ARM architectures. Thumb instruction set provides better code
409 density. For ARM architectures that support Thumb2 this flag will
410 result in Thumb2 code generated by GCC.
412 config SPL_SYS_THUMB_BUILD
413 bool "Build SPL using the Thumb instruction set"
414 default y if SYS_THUMB_BUILD
415 depends on !ARM64 && SPL
417 Use this flag to build SPL using the Thumb instruction set for
418 ARM architectures. Thumb instruction set provides better code
419 density. For ARM architectures that support Thumb2 this flag will
420 result in Thumb2 code generated by GCC.
422 config TPL_SYS_THUMB_BUILD
423 bool "Build TPL using the Thumb instruction set"
424 default y if SYS_THUMB_BUILD
425 depends on TPL && !ARM64
427 Use this flag to build TPL using the Thumb instruction set for
428 ARM architectures. Thumb instruction set provides better code
429 density. For ARM architectures that support Thumb2 this flag will
430 result in Thumb2 code generated by GCC.
433 config SYS_L2CACHE_OFF
436 If SoC does not support L2CACHE or one does not want to enable
437 L2CACHE, choose this option.
439 config ENABLE_ARM_SOC_BOOT0_HOOK
440 bool "prepare BOOT0 header"
442 If the SoC's BOOT0 requires a header area filled with (magic)
443 values, then choose this option, and create a file included as
444 <asm/arch/boot0.h> which contains the required assembler code.
446 config ARM_CORTEX_CPU_IS_UP
450 config USE_ARCH_MEMCPY
451 bool "Use an assembly optimized implementation of memcpy"
455 Enable the generation of an optimized version of memcpy.
456 Such an implementation may be faster under some conditions
457 but may increase the binary size.
459 config SPL_USE_ARCH_MEMCPY
460 bool "Use an assembly optimized implementation of memcpy for SPL"
461 default y if USE_ARCH_MEMCPY
462 depends on !ARM64 && SPL
464 Enable the generation of an optimized version of memcpy.
465 Such an implementation may be faster under some conditions
466 but may increase the binary size.
468 config TPL_USE_ARCH_MEMCPY
469 bool "Use an assembly optimized implementation of memcpy for TPL"
470 default y if USE_ARCH_MEMCPY
471 depends on !ARM64 && TPL
473 Enable the generation of an optimized version of memcpy.
474 Such an implementation may be faster under some conditions
475 but may increase the binary size.
477 config USE_ARCH_MEMSET
478 bool "Use an assembly optimized implementation of memset"
482 Enable the generation of an optimized version of memset.
483 Such an implementation may be faster under some conditions
484 but may increase the binary size.
486 config SPL_USE_ARCH_MEMSET
487 bool "Use an assembly optimized implementation of memset for SPL"
488 default y if USE_ARCH_MEMSET
489 depends on !ARM64 && SPL
491 Enable the generation of an optimized version of memset.
492 Such an implementation may be faster under some conditions
493 but may increase the binary size.
495 config TPL_USE_ARCH_MEMSET
496 bool "Use an assembly optimized implementation of memset for TPL"
497 default y if USE_ARCH_MEMSET
498 depends on !ARM64 && TPL
500 Enable the generation of an optimized version of memset.
501 Such an implementation may be faster under some conditions
502 but may increase the binary size.
504 config SET_STACK_SIZE
505 bool "Enable an option to set max stack size that can be used"
506 default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ
508 This will enable an option to set max stack size that can be
512 hex "Define max stack size that can be used by U-Boot"
513 depends on SET_STACK_SIZE
514 default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
515 default 0x1000000 if ARCH_ZYNQ
517 Define Max stack size that can be used by U-Boot so that the
518 initrd_high will be calculated as base stack pointer minus this
521 config ARM64_SUPPORT_AARCH32
522 bool "ARM64 system support AArch32 execution state"
524 default y if !TARGET_THUNDERX_88XX
526 This ARM64 system supports AArch32 execution state.
529 prompt "Target select"
534 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
535 select SPL_SEPARATE_BSS if SPL
537 config TARGET_EDB93XX
538 bool "Support edb93xx"
542 config TARGET_ASPENITE
543 bool "Support aspenite"
547 bool "Support gplugd"
553 select SPL_DM_SPI if SPL
556 Support for TI's DaVinci platform.
559 bool "Marvell Kirkwood"
560 select ARCH_MISC_INIT
561 select BOARD_EARLY_INIT_F
565 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
571 select SPL_DM_SPI if SPL
572 select SPL_DM_SPI_FLASH if SPL
587 config TARGET_SPEAR300
588 bool "Support spear300"
589 select BOARD_EARLY_INIT_F
594 config TARGET_SPEAR310
595 bool "Support spear310"
596 select BOARD_EARLY_INIT_F
601 config TARGET_SPEAR320
602 bool "Support spear320"
603 select BOARD_EARLY_INIT_F
608 config TARGET_SPEAR600
609 bool "Support spear600"
610 select BOARD_EARLY_INIT_F
615 config TARGET_STV0991
616 bool "Support stv0991"
629 select BOARD_LATE_INIT
638 config TARGET_MX35PDK
639 bool "Support mx35pdk"
640 select BOARD_LATE_INIT
644 bool "Broadcom BCM283X family"
650 select SERIAL_SEARCH_ALL
655 bool "Broadcom BCM63158 family"
661 bool "Broadcom BCM68360 family"
667 bool "Broadcom BCM6858 family"
672 config TARGET_VEXPRESS_CA15_TC2
673 bool "Support vexpress_ca15_tc2"
675 select CPU_V7_HAS_NONSEC
676 select CPU_V7_HAS_VIRT
680 bool "Broadcom BCM7XXX family"
684 select OF_PRIOR_STAGE
687 This enables support for Broadcom ARM-based set-top box
688 chipsets, including the 7445 family of chips.
690 config TARGET_VEXPRESS_CA5X2
691 bool "Support vexpress_ca5x2"
695 config TARGET_VEXPRESS_CA9X4
696 bool "Support vexpress_ca9x4"
700 config TARGET_BCM23550_W1D
701 bool "Support bcm23550_w1d"
706 config TARGET_BCM28155_AP
707 bool "Support bcm28155_ap"
712 config TARGET_BCMCYGNUS
713 bool "Support bcmcygnus"
716 imply BCM_SF2_ETH_GMAC
724 bool "Support bcmnsp"
728 bool "Support Broadcom Northstar2"
731 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
732 ARMv8 Cortex-A57 processors targeting a broad range of networking
736 bool "Samsung EXYNOS"
745 imply SYS_THUMB_BUILD
750 bool "Samsung S5PC1XX"
759 bool "Calxeda Highbank"
763 config ARCH_INTEGRATOR
764 bool "ARM Ltd. Integrator family"
771 bool "Qualcomm IPQ40xx SoCs"
786 select SYS_ARCH_TIMER
787 select SYS_THUMB_BUILD
793 bool "Texas Instruments' K3 Architecture"
798 config ARCH_OMAP2PLUS
801 select SPL_BOARD_INIT if SPL
802 select SPL_STACK_R if SPL
808 imply DISTRO_DEFAULTS
811 Support for the Meson SoC family developed by Amlogic Inc.,
812 targeted at media players and tablet computers. We currently
813 support the S905 (GXBaby) 64-bit SoC.
820 select SPL_LIBCOMMON_SUPPORT if SPL
821 select SPL_LIBGENERIC_SUPPORT if SPL
822 select SPL_OF_CONTROL if SPL
825 Support for the MediaTek SoCs family developed by MediaTek Inc.
826 Please refer to doc/README.mediatek for more information.
829 bool "NXP LPC32xx platform"
839 bool "NXP i.MX8 platform"
843 select ENABLE_ARM_SOC_BOOT0_HOOK
846 bool "NXP i.MX8M platform"
853 bool "NXP i.MXRT platform"
861 bool "NXP i.MX23 family"
872 bool "NXP i.MX28 family"
878 bool "NXP i.MX31 family"
884 select ROM_UNIFIED_SECTIONS
886 imply SYS_THUMB_BUILD
890 select ARCH_MISC_INIT
892 select SYS_FSL_HAS_SEC if IMX_HAB
893 select SYS_FSL_SEC_COMPAT_4
894 select SYS_FSL_SEC_LE
895 imply BOARD_EARLY_INIT_F
897 imply SYS_THUMB_BUILD
902 select SYS_FSL_HAS_SEC
903 select SYS_FSL_SEC_COMPAT_4
904 select SYS_FSL_SEC_LE
906 imply SYS_THUMB_BUILD
910 default "arch/arm/mach-omap2/u-boot-spl.lds"
915 select BOARD_EARLY_INIT_F
920 bool "Actions Semi OWL SoCs"
928 select SYS_RELOC_GD_ENV_ADDR
932 bool "QEMU Virtual Platform"
933 select ARCH_SUPPORT_TFABOOT
943 bool "Renesas ARM SoCs"
944 select BOARD_EARLY_INIT_F if !RZA1
949 imply SYS_THUMB_BUILD
950 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
952 config TARGET_S32V234EVB
953 bool "Support s32v234evb"
955 select SYS_FSL_ERRATUM_ESDHC111
957 config ARCH_SNAPDRAGON
958 bool "Qualcomm Snapdragon SoCs"
971 bool "Altera SOCFPGA family"
972 select ARCH_EARLY_INIT_R
973 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
974 select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
975 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
978 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
980 select SPL_DM_RESET if DM_RESET
982 select SPL_LIBCOMMON_SUPPORT
983 select SPL_LIBGENERIC_SUPPORT
984 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
985 select SPL_OF_CONTROL
986 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
987 select SPL_SERIAL_SUPPORT
989 select SPL_WATCHDOG_SUPPORT
992 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
994 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
995 select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
1005 imply SPL_DM_SPI_FLASH
1006 imply SPL_LIBDISK_SUPPORT
1007 imply SPL_MMC_SUPPORT
1008 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1009 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1010 imply SPL_SPI_FLASH_SUPPORT
1011 imply SPL_SPI_SUPPORT
1015 bool "Support sunxi (Allwinner) SoCs"
1018 select CMD_MMC if MMC
1019 select CMD_USB if DISTRO_DEFAULTS
1025 select DM_MMC if MMC
1026 select DM_SCSI if SCSI
1028 select DM_USB if DISTRO_DEFAULTS
1029 select OF_BOARD_SETUP
1032 select SPECIFY_CONSOLE_INDEX
1033 select SPL_STACK_R if SPL
1034 select SPL_SYS_MALLOC_SIMPLE if SPL
1035 select SPL_SYS_THUMB_BUILD if !ARM64
1038 select SYS_THUMB_BUILD if !ARM64
1039 select USB if DISTRO_DEFAULTS
1040 select USB_KEYBOARD if DISTRO_DEFAULTS
1041 select USB_STORAGE if DISTRO_DEFAULTS
1042 select SPL_USE_TINY_PRINTF
1044 select SYS_RELOC_GD_ENV_ADDR
1047 imply CMD_UBI if MTD_RAW_NAND
1048 imply DISTRO_DEFAULTS
1051 imply OF_LIBFDT_OVERLAY
1052 imply PRE_CONSOLE_BUFFER
1053 imply SPL_GPIO_SUPPORT
1054 imply SPL_LIBCOMMON_SUPPORT
1055 imply SPL_LIBGENERIC_SUPPORT
1056 imply SPL_MMC_SUPPORT if MMC
1057 imply SPL_POWER_SUPPORT
1058 imply SPL_SERIAL_SUPPORT
1062 bool "ST-Ericsson U8500 Series"
1066 select DM_MMC if MMC
1068 select DM_USB if USB
1072 imply ARM_PL180_MMCI
1074 imply NOMADIK_MTU_TIMER
1077 imply SYSRESET_SYSCON
1080 bool "Support Xilinx Versal Platform"
1084 select DM_ETH if NET
1085 select DM_MMC if MMC
1088 imply BOARD_LATE_INIT
1091 bool "Freescale Vybrid"
1093 select SYS_FSL_ERRATUM_ESDHC111
1098 bool "Xilinx Zynq based platform"
1103 select DM_ETH if NET
1104 select DM_MMC if MMC
1108 select DM_USB if USB
1111 select SPL_BOARD_INIT if SPL
1112 select SPL_CLK if SPL
1113 select SPL_DM if SPL
1114 select SPL_DM_SPI if SPL
1115 select SPL_DM_SPI_FLASH if SPL
1116 select SPL_OF_CONTROL if SPL
1117 select SPL_SEPARATE_BSS if SPL
1119 imply ARCH_EARLY_INIT_R
1120 imply BOARD_LATE_INIT
1126 config ARCH_ZYNQMP_R5
1127 bool "Xilinx ZynqMP R5 based platform"
1131 select DM_ETH if NET
1132 select DM_MMC if MMC
1139 bool "Xilinx ZynqMP based platform"
1143 select DM_ETH if NET
1145 select DM_MMC if MMC
1147 select DM_SPI if SPI
1148 select DM_SPI_FLASH if DM_SPI
1149 select DM_USB if USB
1152 select SPL_BOARD_INIT if SPL
1153 select SPL_CLK if SPL
1154 select SPL_DM_SPI if SPI
1155 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1156 select SPL_DM_MAILBOX if SPL
1157 select SPL_FIRMWARE if SPL
1158 select SPL_SEPARATE_BSS if SPL
1161 imply BOARD_LATE_INIT
1169 imply DISTRO_DEFAULTS
1172 config TARGET_VEXPRESS64_AEMV8A
1173 bool "Support vexpress_aemv8a"
1177 config TARGET_VEXPRESS64_BASE_FVP
1178 bool "Support Versatile Express ARMv8a FVP BASE model"
1183 config TARGET_VEXPRESS64_JUNO
1184 bool "Support Versatile Express Juno Development Platform"
1199 config TARGET_LS2080A_EMU
1200 bool "Support ls2080a_emu"
1203 select ARMV8_MULTIENTRY
1204 select FSL_DDR_SYNC_REFRESH
1206 Support for Freescale LS2080A_EMU platform.
1207 The LS2080A Development System (EMULATOR) is a pre-silicon
1208 development platform that supports the QorIQ LS2080A
1209 Layerscape Architecture processor.
1211 config TARGET_LS2080A_SIMU
1212 bool "Support ls2080a_simu"
1215 select ARMV8_MULTIENTRY
1216 select BOARD_LATE_INIT
1218 Support for Freescale LS2080A_SIMU platform.
1219 The LS2080A Development System (QDS) is a pre silicon
1220 development platform that supports the QorIQ LS2080A
1221 Layerscape Architecture processor.
1223 config TARGET_LS1088AQDS
1224 bool "Support ls1088aqds"
1227 select ARMV8_MULTIENTRY
1228 select ARCH_SUPPORT_TFABOOT
1229 select BOARD_LATE_INIT
1231 select FSL_DDR_INTERACTIVE if !SD_BOOT
1233 Support for NXP LS1088AQDS platform.
1234 The LS1088A Development System (QDS) is a high-performance
1235 development platform that supports the QorIQ LS1088A
1236 Layerscape Architecture processor.
1238 config TARGET_LS2080AQDS
1239 bool "Support ls2080aqds"
1242 select ARMV8_MULTIENTRY
1243 select ARCH_SUPPORT_TFABOOT
1244 select BOARD_LATE_INIT
1249 select FSL_DDR_INTERACTIVE if !SPL
1251 Support for Freescale LS2080AQDS platform.
1252 The LS2080A Development System (QDS) is a high-performance
1253 development platform that supports the QorIQ LS2080A
1254 Layerscape Architecture processor.
1256 config TARGET_LS2080ARDB
1257 bool "Support ls2080ardb"
1260 select ARMV8_MULTIENTRY
1261 select ARCH_SUPPORT_TFABOOT
1262 select BOARD_LATE_INIT
1265 select FSL_DDR_INTERACTIVE if !SPL
1269 Support for Freescale LS2080ARDB platform.
1270 The LS2080A Reference design board (RDB) is a high-performance
1271 development platform that supports the QorIQ LS2080A
1272 Layerscape Architecture processor.
1274 config TARGET_LS2081ARDB
1275 bool "Support ls2081ardb"
1278 select ARMV8_MULTIENTRY
1279 select BOARD_LATE_INIT
1282 Support for Freescale LS2081ARDB platform.
1283 The LS2081A Reference design board (RDB) is a high-performance
1284 development platform that supports the QorIQ LS2081A/LS2041A
1285 Layerscape Architecture processor.
1287 config TARGET_LX2160ARDB
1288 bool "Support lx2160ardb"
1291 select ARMV8_MULTIENTRY
1292 select ARCH_SUPPORT_TFABOOT
1293 select BOARD_LATE_INIT
1295 Support for NXP LX2160ARDB platform.
1296 The lx2160ardb (LX2160A Reference design board (RDB)
1297 is a high-performance development platform that supports the
1298 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1300 config TARGET_LX2160AQDS
1301 bool "Support lx2160aqds"
1304 select ARMV8_MULTIENTRY
1305 select ARCH_SUPPORT_TFABOOT
1306 select BOARD_LATE_INIT
1308 Support for NXP LX2160AQDS platform.
1309 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1310 is a high-performance development platform that supports the
1311 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1314 bool "Support HiKey 96boards Consumer Edition Platform"
1321 select SPECIFY_CONSOLE_INDEX
1324 Support for HiKey 96boards platform. It features a HI6220
1325 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1327 config TARGET_HIKEY960
1328 bool "Support HiKey960 96boards Consumer Edition Platform"
1336 Support for HiKey960 96boards platform. It features a HI3660
1337 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1339 config TARGET_POPLAR
1340 bool "Support Poplar 96boards Enterprise Edition Platform"
1349 Support for Poplar 96boards EE platform. It features a HI3798cv200
1350 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1351 making it capable of running any commercial set-top solution based on
1354 config TARGET_LS1012AQDS
1355 bool "Support ls1012aqds"
1358 select ARCH_SUPPORT_TFABOOT
1359 select BOARD_LATE_INIT
1361 Support for Freescale LS1012AQDS platform.
1362 The LS1012A Development System (QDS) is a high-performance
1363 development platform that supports the QorIQ LS1012A
1364 Layerscape Architecture processor.
1366 config TARGET_LS1012ARDB
1367 bool "Support ls1012ardb"
1370 select ARCH_SUPPORT_TFABOOT
1371 select BOARD_LATE_INIT
1375 Support for Freescale LS1012ARDB platform.
1376 The LS1012A Reference design board (RDB) is a high-performance
1377 development platform that supports the QorIQ LS1012A
1378 Layerscape Architecture processor.
1380 config TARGET_LS1012A2G5RDB
1381 bool "Support ls1012a2g5rdb"
1384 select ARCH_SUPPORT_TFABOOT
1385 select BOARD_LATE_INIT
1388 Support for Freescale LS1012A2G5RDB platform.
1389 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1390 development platform that supports the QorIQ LS1012A
1391 Layerscape Architecture processor.
1393 config TARGET_LS1012AFRWY
1394 bool "Support ls1012afrwy"
1397 select ARCH_SUPPORT_TFABOOT
1398 select BOARD_LATE_INIT
1402 Support for Freescale LS1012AFRWY platform.
1403 The LS1012A FRWY board (FRWY) is a high-performance
1404 development platform that supports the QorIQ LS1012A
1405 Layerscape Architecture processor.
1407 config TARGET_LS1012AFRDM
1408 bool "Support ls1012afrdm"
1411 select ARCH_SUPPORT_TFABOOT
1413 Support for Freescale LS1012AFRDM platform.
1414 The LS1012A Freedom board (FRDM) is a high-performance
1415 development platform that supports the QorIQ LS1012A
1416 Layerscape Architecture processor.
1418 config TARGET_LS1028AQDS
1419 bool "Support ls1028aqds"
1422 select ARMV8_MULTIENTRY
1423 select ARCH_SUPPORT_TFABOOT
1424 select BOARD_LATE_INIT
1426 Support for Freescale LS1028AQDS platform
1427 The LS1028A Development System (QDS) is a high-performance
1428 development platform that supports the QorIQ LS1028A
1429 Layerscape Architecture processor.
1431 config TARGET_LS1028ARDB
1432 bool "Support ls1028ardb"
1435 select ARMV8_MULTIENTRY
1436 select ARCH_SUPPORT_TFABOOT
1437 select BOARD_LATE_INIT
1439 Support for Freescale LS1028ARDB platform
1440 The LS1028A Development System (RDB) is a high-performance
1441 development platform that supports the QorIQ LS1028A
1442 Layerscape Architecture processor.
1444 config TARGET_LS1088ARDB
1445 bool "Support ls1088ardb"
1448 select ARMV8_MULTIENTRY
1449 select ARCH_SUPPORT_TFABOOT
1450 select BOARD_LATE_INIT
1452 select FSL_DDR_INTERACTIVE if !SD_BOOT
1454 Support for NXP LS1088ARDB platform.
1455 The LS1088A Reference design board (RDB) is a high-performance
1456 development platform that supports the QorIQ LS1088A
1457 Layerscape Architecture processor.
1459 config TARGET_LS1021AQDS
1460 bool "Support ls1021aqds"
1462 select ARCH_SUPPORT_PSCI
1463 select BOARD_EARLY_INIT_F
1464 select BOARD_LATE_INIT
1466 select CPU_V7_HAS_NONSEC
1467 select CPU_V7_HAS_VIRT
1468 select LS1_DEEP_SLEEP
1471 select FSL_DDR_INTERACTIVE
1472 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1473 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1476 config TARGET_LS1021ATWR
1477 bool "Support ls1021atwr"
1479 select ARCH_SUPPORT_PSCI
1480 select BOARD_EARLY_INIT_F
1481 select BOARD_LATE_INIT
1483 select CPU_V7_HAS_NONSEC
1484 select CPU_V7_HAS_VIRT
1485 select LS1_DEEP_SLEEP
1487 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1490 config TARGET_LS1021ATSN
1491 bool "Support ls1021atsn"
1493 select ARCH_SUPPORT_PSCI
1494 select BOARD_EARLY_INIT_F
1495 select BOARD_LATE_INIT
1497 select CPU_V7_HAS_NONSEC
1498 select CPU_V7_HAS_VIRT
1499 select LS1_DEEP_SLEEP
1503 config TARGET_LS1021AIOT
1504 bool "Support ls1021aiot"
1506 select ARCH_SUPPORT_PSCI
1507 select BOARD_LATE_INIT
1509 select CPU_V7_HAS_NONSEC
1510 select CPU_V7_HAS_VIRT
1512 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1515 Support for Freescale LS1021AIOT platform.
1516 The LS1021A Freescale board (IOT) is a high-performance
1517 development platform that supports the QorIQ LS1021A
1518 Layerscape Architecture processor.
1520 config TARGET_LS1043AQDS
1521 bool "Support ls1043aqds"
1524 select ARMV8_MULTIENTRY
1525 select ARCH_SUPPORT_TFABOOT
1526 select BOARD_EARLY_INIT_F
1527 select BOARD_LATE_INIT
1529 select FSL_DDR_INTERACTIVE if !SPL
1530 select FSL_DSPI if !SPL_NO_DSPI
1531 select DM_SPI_FLASH if FSL_DSPI
1535 Support for Freescale LS1043AQDS platform.
1537 config TARGET_LS1043ARDB
1538 bool "Support ls1043ardb"
1541 select ARMV8_MULTIENTRY
1542 select ARCH_SUPPORT_TFABOOT
1543 select BOARD_EARLY_INIT_F
1544 select BOARD_LATE_INIT
1546 select FSL_DSPI if !SPL_NO_DSPI
1547 select DM_SPI_FLASH if FSL_DSPI
1549 Support for Freescale LS1043ARDB platform.
1551 config TARGET_LS1046AQDS
1552 bool "Support ls1046aqds"
1555 select ARMV8_MULTIENTRY
1556 select ARCH_SUPPORT_TFABOOT
1557 select BOARD_EARLY_INIT_F
1558 select BOARD_LATE_INIT
1559 select DM_SPI_FLASH if DM_SPI
1561 select FSL_DDR_BIST if !SPL
1562 select FSL_DDR_INTERACTIVE if !SPL
1563 select FSL_DDR_INTERACTIVE if !SPL
1566 Support for Freescale LS1046AQDS platform.
1567 The LS1046A Development System (QDS) is a high-performance
1568 development platform that supports the QorIQ LS1046A
1569 Layerscape Architecture processor.
1571 config TARGET_LS1046ARDB
1572 bool "Support ls1046ardb"
1575 select ARMV8_MULTIENTRY
1576 select ARCH_SUPPORT_TFABOOT
1577 select BOARD_EARLY_INIT_F
1578 select BOARD_LATE_INIT
1579 select DM_SPI_FLASH if DM_SPI
1580 select POWER_MC34VR500
1583 select FSL_DDR_INTERACTIVE if !SPL
1586 Support for Freescale LS1046ARDB platform.
1587 The LS1046A Reference Design Board (RDB) is a high-performance
1588 development platform that supports the QorIQ LS1046A
1589 Layerscape Architecture processor.
1591 config TARGET_LS1046AFRWY
1592 bool "Support ls1046afrwy"
1595 select ARMV8_MULTIENTRY
1596 select ARCH_SUPPORT_TFABOOT
1597 select BOARD_EARLY_INIT_F
1598 select BOARD_LATE_INIT
1599 select DM_SPI_FLASH if DM_SPI
1602 Support for Freescale LS1046AFRWY platform.
1603 The LS1046A Freeway Board (FRWY) is a high-performance
1604 development platform that supports the QorIQ LS1046A
1605 Layerscape Architecture processor.
1607 config TARGET_COLIBRI_PXA270
1608 bool "Support colibri_pxa270"
1611 config ARCH_UNIPHIER
1612 bool "Socionext UniPhier SoCs"
1613 select BOARD_LATE_INIT
1623 select OF_BOARD_SETUP
1627 select SPL_BOARD_INIT if SPL
1628 select SPL_DM if SPL
1629 select SPL_LIBCOMMON_SUPPORT if SPL
1630 select SPL_LIBGENERIC_SUPPORT if SPL
1631 select SPL_OF_CONTROL if SPL
1632 select SPL_PINCTRL if SPL
1635 imply DISTRO_DEFAULTS
1638 Support for UniPhier SoC family developed by Socionext Inc.
1639 (formerly, System LSI Business Division of Panasonic Corporation)
1642 bool "Support STMicroelectronics STM32 MCU with cortex M"
1649 bool "Support STMicrolectronics SoCs"
1658 Support for STMicroelectronics STiH407/10 SoC family.
1659 This SoC is used on Linaro 96Board STiH410-B2260
1662 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1663 select ARCH_MISC_INIT
1664 select ARCH_SUPPORT_TFABOOT
1665 select BOARD_LATE_INIT
1674 select OF_SYSTEM_SETUP
1680 select SYS_THUMB_BUILD
1684 imply OF_LIBFDT_OVERLAY
1685 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1688 Support for STM32MP SoC family developed by STMicroelectronics,
1689 MPUs based on ARM cortex A core
1690 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1691 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1693 SPL is the unsecure FSBL for the basic boot chain.
1695 config ARCH_ROCKCHIP
1696 bool "Support Rockchip SoCs"
1698 select BINMAN if !ARM64
1708 select DM_USB if USB
1709 select ENABLE_ARM_SOC_BOOT0_HOOK
1712 select SPL_DM if SPL
1713 select SPL_DM_SPI if SPL
1714 select SPL_DM_SPI_FLASH if SPL
1716 select SYS_THUMB_BUILD if !ARM64
1719 imply DEBUG_UART_BOARD_INIT
1720 imply DISTRO_DEFAULTS
1722 imply SARADC_ROCKCHIP
1724 imply SPL_SYS_MALLOC_SIMPLE
1727 imply USB_FUNCTION_FASTBOOT
1729 config TARGET_THUNDERX_88XX
1730 bool "Support ThunderX 88xx"
1734 select SYS_CACHE_SHIFT_7
1737 bool "Support Aspeed SoCs"
1742 config TARGET_DURIAN
1743 bool "Support Phytium Durian Platform"
1746 Support for durian platform.
1747 It has 2GB Sdram, uart and pcie.
1749 config TARGET_PRESIDIO_ASIC
1750 bool "Support Cortina Presidio ASIC Platform"
1755 config ARCH_SUPPORT_TFABOOT
1759 bool "Support for booting from TF-A"
1760 depends on ARCH_SUPPORT_TFABOOT
1763 Enabling this will make a U-Boot binary that is capable of being
1764 booted via TF-A (Trusted Firmware for Cortex-A).
1766 config TI_SECURE_DEVICE
1767 bool "HS Device Type Support"
1768 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1770 If a high secure (HS) device type is being used, this config
1771 must be set. This option impacts various aspects of the
1772 build system (to create signed boot images that can be
1773 authenticated) and the code. See the doc/README.ti-secure
1774 file for further details.
1776 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1777 config ISW_ENTRY_ADDR
1778 hex "Address in memory or XIP address of bootloader entry point"
1779 default 0x402F4000 if AM43XX
1780 default 0x402F0400 if AM33XX
1781 default 0x40301350 if OMAP54XX
1783 After any reset, the boot ROM searches the boot media for a valid
1784 boot image. For non-XIP devices, the ROM then copies the image into
1785 internal memory. For all boot modes, after the ROM processes the
1786 boot image it eventually computes the entry point address depending
1787 on the device type (secure/non-secure), boot media (xip/non-xip) and
1791 source "arch/arm/mach-aspeed/Kconfig"
1793 source "arch/arm/mach-at91/Kconfig"
1795 source "arch/arm/mach-bcm283x/Kconfig"
1797 source "arch/arm/mach-bcmstb/Kconfig"
1799 source "arch/arm/mach-davinci/Kconfig"
1801 source "arch/arm/mach-exynos/Kconfig"
1803 source "arch/arm/mach-highbank/Kconfig"
1805 source "arch/arm/mach-integrator/Kconfig"
1807 source "arch/arm/mach-ipq40xx/Kconfig"
1809 source "arch/arm/mach-k3/Kconfig"
1811 source "arch/arm/mach-keystone/Kconfig"
1813 source "arch/arm/mach-kirkwood/Kconfig"
1815 source "arch/arm/mach-lpc32xx/Kconfig"
1817 source "arch/arm/mach-mvebu/Kconfig"
1819 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1821 source "arch/arm/mach-imx/mx2/Kconfig"
1823 source "arch/arm/mach-imx/mx3/Kconfig"
1825 source "arch/arm/mach-imx/mx5/Kconfig"
1827 source "arch/arm/mach-imx/mx6/Kconfig"
1829 source "arch/arm/mach-imx/mx7/Kconfig"
1831 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1833 source "arch/arm/mach-imx/imx8/Kconfig"
1835 source "arch/arm/mach-imx/imx8m/Kconfig"
1837 source "arch/arm/mach-imx/imxrt/Kconfig"
1839 source "arch/arm/mach-imx/mxs/Kconfig"
1841 source "arch/arm/mach-omap2/Kconfig"
1843 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1845 source "arch/arm/mach-orion5x/Kconfig"
1847 source "arch/arm/mach-owl/Kconfig"
1849 source "arch/arm/mach-rmobile/Kconfig"
1851 source "arch/arm/mach-meson/Kconfig"
1853 source "arch/arm/mach-mediatek/Kconfig"
1855 source "arch/arm/mach-qemu/Kconfig"
1857 source "arch/arm/mach-rockchip/Kconfig"
1859 source "arch/arm/mach-s5pc1xx/Kconfig"
1861 source "arch/arm/mach-snapdragon/Kconfig"
1863 source "arch/arm/mach-socfpga/Kconfig"
1865 source "arch/arm/mach-sti/Kconfig"
1867 source "arch/arm/mach-stm32/Kconfig"
1869 source "arch/arm/mach-stm32mp/Kconfig"
1871 source "arch/arm/mach-sunxi/Kconfig"
1873 source "arch/arm/mach-tegra/Kconfig"
1875 source "arch/arm/mach-u8500/Kconfig"
1877 source "arch/arm/mach-uniphier/Kconfig"
1879 source "arch/arm/cpu/armv7/vf610/Kconfig"
1881 source "arch/arm/mach-zynq/Kconfig"
1883 source "arch/arm/mach-zynqmp/Kconfig"
1885 source "arch/arm/mach-versal/Kconfig"
1887 source "arch/arm/mach-zynqmp-r5/Kconfig"
1889 source "arch/arm/cpu/armv7/Kconfig"
1891 source "arch/arm/cpu/armv8/Kconfig"
1893 source "arch/arm/mach-imx/Kconfig"
1895 source "board/bosch/shc/Kconfig"
1896 source "board/bosch/guardian/Kconfig"
1897 source "board/CarMediaLab/flea3/Kconfig"
1898 source "board/Marvell/aspenite/Kconfig"
1899 source "board/Marvell/gplugd/Kconfig"
1900 source "board/armadeus/apf27/Kconfig"
1901 source "board/armltd/vexpress/Kconfig"
1902 source "board/armltd/vexpress64/Kconfig"
1903 source "board/cortina/presidio-asic/Kconfig"
1904 source "board/broadcom/bcm23550_w1d/Kconfig"
1905 source "board/broadcom/bcm28155_ap/Kconfig"
1906 source "board/broadcom/bcm963158/Kconfig"
1907 source "board/broadcom/bcm968360bg/Kconfig"
1908 source "board/broadcom/bcm968580xref/Kconfig"
1909 source "board/broadcom/bcmcygnus/Kconfig"
1910 source "board/broadcom/bcmnsp/Kconfig"
1911 source "board/broadcom/bcmns2/Kconfig"
1912 source "board/cavium/thunderx/Kconfig"
1913 source "board/cirrus/edb93xx/Kconfig"
1914 source "board/eets/pdu001/Kconfig"
1915 source "board/emulation/qemu-arm/Kconfig"
1916 source "board/freescale/ls2080a/Kconfig"
1917 source "board/freescale/ls2080aqds/Kconfig"
1918 source "board/freescale/ls2080ardb/Kconfig"
1919 source "board/freescale/ls1088a/Kconfig"
1920 source "board/freescale/ls1028a/Kconfig"
1921 source "board/freescale/ls1021aqds/Kconfig"
1922 source "board/freescale/ls1043aqds/Kconfig"
1923 source "board/freescale/ls1021atwr/Kconfig"
1924 source "board/freescale/ls1021atsn/Kconfig"
1925 source "board/freescale/ls1021aiot/Kconfig"
1926 source "board/freescale/ls1046aqds/Kconfig"
1927 source "board/freescale/ls1043ardb/Kconfig"
1928 source "board/freescale/ls1046ardb/Kconfig"
1929 source "board/freescale/ls1046afrwy/Kconfig"
1930 source "board/freescale/ls1012aqds/Kconfig"
1931 source "board/freescale/ls1012ardb/Kconfig"
1932 source "board/freescale/ls1012afrdm/Kconfig"
1933 source "board/freescale/lx2160a/Kconfig"
1934 source "board/freescale/mx35pdk/Kconfig"
1935 source "board/freescale/s32v234evb/Kconfig"
1936 source "board/grinn/chiliboard/Kconfig"
1937 source "board/hisilicon/hikey/Kconfig"
1938 source "board/hisilicon/hikey960/Kconfig"
1939 source "board/hisilicon/poplar/Kconfig"
1940 source "board/isee/igep003x/Kconfig"
1941 source "board/spear/spear300/Kconfig"
1942 source "board/spear/spear310/Kconfig"
1943 source "board/spear/spear320/Kconfig"
1944 source "board/spear/spear600/Kconfig"
1945 source "board/spear/x600/Kconfig"
1946 source "board/st/stv0991/Kconfig"
1947 source "board/tcl/sl50/Kconfig"
1948 source "board/toradex/colibri_pxa270/Kconfig"
1949 source "board/variscite/dart_6ul/Kconfig"
1950 source "board/vscom/baltos/Kconfig"
1951 source "board/xilinx/Kconfig"
1952 source "board/xilinx/zynq/Kconfig"
1953 source "board/xilinx/zynqmp/Kconfig"
1954 source "board/phytium/durian/Kconfig"
1956 source "arch/arm/Kconfig.debug"
1961 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
1962 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
1963 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64