1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
17 be loaded to and run from that address. This option lifts that
18 restriction, thus allowing the code to be loaded to and executed from
19 almost any 4K aligned address. This logic relies on the relocation
20 information that is embedded in the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
23 config INIT_SP_RELATIVE
24 bool "Specify the early stack pointer relative to the .bss section"
25 default n if ARCH_QEMU
26 default y if POSITION_INDEPENDENT
28 U-Boot typically uses a hard-coded value for the stack pointer
29 before relocation. Enable this option to instead calculate the
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that it can be loaded and executed at arbitrary
32 addresses and thus avoid using arbitrary addresses at runtime.
34 If this option is enabled, the early stack pointer is set to
35 &_bss_start with a offset value added. The offset is specified by
36 SYS_INIT_SP_BSS_OFFSET.
38 config SYS_INIT_SP_BSS_OFFSET
39 int "Early stack offset from the .bss base address"
40 depends on INIT_SP_RELATIVE
43 This option's value is the offset added to &_bss_start in order to
44 calculate the stack pointer. This offset should be large enough so
45 that the early malloc region, global data (gd), and early stack usage
46 do not overlap any appended DTB.
48 config LINUX_KERNEL_IMAGE_HEADER
51 Place a Linux kernel image header at the start of the U-Boot binary.
52 The format of the header is described in the Linux kernel source at
53 Documentation/arm64/booting.txt. This feature is useful since the
54 image header reports the amount of memory (BSS and similar) that
55 U-Boot needs to use, but which isn't part of the binary.
57 if LINUX_KERNEL_IMAGE_HEADER
58 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
61 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
62 TEXT_OFFSET value written to the Linux kernel image header.
72 ARM GICV3 Interrupt translation service (ITS).
73 Basic support for programming locality specific peripheral
74 interrupts (LPI) configuration tables and enable LPI tables.
75 LPI configuration table can be used by u-boot or Linux.
76 ARM GICV3 has limitation, once the LPI table is enabled, LPI
77 configuration table can not be re-programmed, unless GICV3 reset.
83 config DMA_ADDR_T_64BIT
93 config GPIO_EXTRA_HEADER
96 # Used for compatibility with asm files copied from the kernel
97 config ARM_ASM_UNIFIED
101 # Used for compatibility with asm files copied from the kernel
105 config SYS_ICACHE_OFF
106 bool "Do not enable icache"
109 Do not enable instruction cache in U-Boot.
111 config SPL_SYS_ICACHE_OFF
112 bool "Do not enable icache in SPL"
114 default SYS_ICACHE_OFF
116 Do not enable instruction cache in SPL.
118 config SYS_DCACHE_OFF
119 bool "Do not enable dcache"
122 Do not enable data cache in U-Boot.
124 config SPL_SYS_DCACHE_OFF
125 bool "Do not enable dcache in SPL"
127 default SYS_DCACHE_OFF
129 Do not enable data cache in SPL.
131 config SYS_ARM_CACHE_CP15
132 bool "CP15 based cache enabling support"
134 Select this if your processor suports enabling caches by using
138 bool "MMU-based Paged Memory Management Support"
139 select SYS_ARM_CACHE_CP15
141 Select if you want MMU-based virtualised addressing space
142 support via paged memory management.
145 bool 'Use the ARM v7 PMSA Compliant MPU'
147 Some ARM systems without an MMU have instead a Memory Protection
148 Unit (MPU) that defines the type and permissions for regions of
150 If your CPU has an MPU then you should choose 'y' here unless you
151 know that you do not want to use the MPU.
153 # If set, the workarounds for these ARM errata are applied early during U-Boot
154 # startup. Note that in general these options force the workarounds to be
155 # applied; no CPU-type/version detection exists, unlike the similar options in
156 # the Linux kernel. Do not set these options unless they apply! Also note that
157 # the following can be machine-specific errata. These do have ability to
158 # provide rudimentary version and machine-specific checks, but expect no
160 # CONFIG_ARM_ERRATA_430973
161 # CONFIG_ARM_ERRATA_454179
162 # CONFIG_ARM_ERRATA_621766
163 # CONFIG_ARM_ERRATA_798870
164 # CONFIG_ARM_ERRATA_801819
165 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
166 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
168 config ARM_ERRATA_430973
171 config ARM_ERRATA_454179
174 config ARM_ERRATA_621766
177 config ARM_ERRATA_716044
180 config ARM_ERRATA_725233
183 config ARM_ERRATA_742230
186 config ARM_ERRATA_743622
189 config ARM_ERRATA_751472
192 config ARM_ERRATA_761320
195 config ARM_ERRATA_773022
198 config ARM_ERRATA_774769
201 config ARM_ERRATA_794072
204 config ARM_ERRATA_798870
207 config ARM_ERRATA_801819
210 config ARM_ERRATA_826974
213 config ARM_ERRATA_828024
216 config ARM_ERRATA_829520
219 config ARM_ERRATA_833069
222 config ARM_ERRATA_833471
225 config ARM_ERRATA_845369
228 config ARM_ERRATA_852421
231 config ARM_ERRATA_852423
234 config ARM_ERRATA_855873
237 config ARM_CORTEX_A8_CVE_2017_5715
240 config ARM_CORTEX_A15_CVE_2017_5715
245 select SYS_CACHE_SHIFT_5
250 select SYS_CACHE_SHIFT_5
255 select SYS_CACHE_SHIFT_5
260 select SYS_CACHE_SHIFT_5
265 select SYS_CACHE_SHIFT_5
271 select SYS_CACHE_SHIFT_5
278 select SYS_CACHE_SHIFT_6
285 select SYS_CACHE_SHIFT_5
286 select SYS_THUMB_BUILD
292 select SYS_ARM_CACHE_CP15
294 select SYS_CACHE_SHIFT_6
298 select SYS_CACHE_SHIFT_5
303 select SYS_CACHE_SHIFT_5
307 default "arm720t" if CPU_ARM720T
308 default "arm920t" if CPU_ARM920T
309 default "arm926ejs" if CPU_ARM926EJS
310 default "arm946es" if CPU_ARM946ES
311 default "arm1136" if CPU_ARM1136
312 default "arm1176" if CPU_ARM1176
313 default "armv7" if CPU_V7A
314 default "armv7" if CPU_V7R
315 default "armv7m" if CPU_V7M
316 default "pxa" if CPU_PXA
317 default "sa1100" if CPU_SA1100
318 default "armv8" if ARM64
322 default 4 if CPU_ARM720T
323 default 4 if CPU_ARM920T
324 default 5 if CPU_ARM926EJS
325 default 5 if CPU_ARM946ES
326 default 6 if CPU_ARM1136
327 default 6 if CPU_ARM1176
332 default 4 if CPU_SA1100
335 config SYS_CACHE_SHIFT_5
338 config SYS_CACHE_SHIFT_6
341 config SYS_CACHE_SHIFT_7
344 config SYS_CACHELINE_SIZE
346 default 128 if SYS_CACHE_SHIFT_7
347 default 64 if SYS_CACHE_SHIFT_6
348 default 32 if SYS_CACHE_SHIFT_5
351 prompt "Select the ARM data write cache policy"
352 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
354 default SYS_ARM_CACHE_WRITEBACK
356 config SYS_ARM_CACHE_WRITEBACK
357 bool "Write-back (WB)"
359 A write updates the cache only and marks the cache line as dirty.
360 External memory is updated only when the line is evicted or explicitly
363 config SYS_ARM_CACHE_WRITETHROUGH
364 bool "Write-through (WT)"
366 A write updates both the cache and the external memory system.
367 This does not mark the cache line as dirty.
369 config SYS_ARM_CACHE_WRITEALLOC
370 bool "Write allocation (WA)"
372 A cache line is allocated on a write miss. This means that executing a
373 store instruction on the processor might cause a burst read to occur.
374 There is a linefill to obtain the data for the cache line, before the
379 bool "Enable ARCH_CPU_INIT"
381 Some architectures require a call to arch_cpu_init().
382 Say Y here to enable it
384 config SYS_ARCH_TIMER
385 bool "ARM Generic Timer support"
386 depends on CPU_V7A || ARM64
389 The ARM Generic Timer (aka arch-timer) provides an architected
390 interface to a timer source on an SoC.
391 It is mandatory for ARMv8 implementation and widely available
395 bool "Support for ARM SMC Calling Convention (SMCCC)"
396 depends on CPU_V7A || ARM64
399 Say Y here if you want to enable ARM SMC Calling Convention.
400 This should be enabled if U-Boot needs to communicate with system
401 firmware (for example, PSCI) according to SMCCC.
404 bool "support boot from semihosting"
406 In emulated environments, semihosting is a way for
407 the hosted environment to call out to the emulator to
408 retrieve files from the host machine.
410 config SYS_THUMB_BUILD
411 bool "Build U-Boot using the Thumb instruction set"
414 Use this flag to build U-Boot using the Thumb instruction set for
415 ARM architectures. Thumb instruction set provides better code
416 density. For ARM architectures that support Thumb2 this flag will
417 result in Thumb2 code generated by GCC.
419 config SPL_SYS_THUMB_BUILD
420 bool "Build SPL using the Thumb instruction set"
421 default y if SYS_THUMB_BUILD
422 depends on !ARM64 && SPL
424 Use this flag to build SPL using the Thumb instruction set for
425 ARM architectures. Thumb instruction set provides better code
426 density. For ARM architectures that support Thumb2 this flag will
427 result in Thumb2 code generated by GCC.
429 config TPL_SYS_THUMB_BUILD
430 bool "Build TPL using the Thumb instruction set"
431 default y if SYS_THUMB_BUILD
432 depends on TPL && !ARM64
434 Use this flag to build TPL using the Thumb instruction set for
435 ARM architectures. Thumb instruction set provides better code
436 density. For ARM architectures that support Thumb2 this flag will
437 result in Thumb2 code generated by GCC.
440 config SYS_L2CACHE_OFF
443 If SoC does not support L2CACHE or one does not want to enable
444 L2CACHE, choose this option.
446 config ENABLE_ARM_SOC_BOOT0_HOOK
447 bool "prepare BOOT0 header"
449 If the SoC's BOOT0 requires a header area filled with (magic)
450 values, then choose this option, and create a file included as
451 <asm/arch/boot0.h> which contains the required assembler code.
453 config ARM_CORTEX_CPU_IS_UP
457 config USE_ARCH_MEMCPY
458 bool "Use an assembly optimized implementation of memcpy"
462 Enable the generation of an optimized version of memcpy.
463 Such an implementation may be faster under some conditions
464 but may increase the binary size.
466 config SPL_USE_ARCH_MEMCPY
467 bool "Use an assembly optimized implementation of memcpy for SPL"
468 default y if USE_ARCH_MEMCPY
469 depends on !ARM64 && SPL
471 Enable the generation of an optimized version of memcpy.
472 Such an implementation may be faster under some conditions
473 but may increase the binary size.
475 config TPL_USE_ARCH_MEMCPY
476 bool "Use an assembly optimized implementation of memcpy for TPL"
477 default y if USE_ARCH_MEMCPY
478 depends on !ARM64 && TPL
480 Enable the generation of an optimized version of memcpy.
481 Such an implementation may be faster under some conditions
482 but may increase the binary size.
484 config USE_ARCH_MEMSET
485 bool "Use an assembly optimized implementation of memset"
489 Enable the generation of an optimized version of memset.
490 Such an implementation may be faster under some conditions
491 but may increase the binary size.
493 config SPL_USE_ARCH_MEMSET
494 bool "Use an assembly optimized implementation of memset for SPL"
495 default y if USE_ARCH_MEMSET
496 depends on !ARM64 && SPL
498 Enable the generation of an optimized version of memset.
499 Such an implementation may be faster under some conditions
500 but may increase the binary size.
502 config TPL_USE_ARCH_MEMSET
503 bool "Use an assembly optimized implementation of memset for TPL"
504 default y if USE_ARCH_MEMSET
505 depends on !ARM64 && TPL
507 Enable the generation of an optimized version of memset.
508 Such an implementation may be faster under some conditions
509 but may increase the binary size.
511 config ARM64_SUPPORT_AARCH32
512 bool "ARM64 system support AArch32 execution state"
514 default y if !TARGET_THUNDERX_88XX
516 This ARM64 system supports AArch32 execution state.
519 prompt "Target select"
524 select GPIO_EXTRA_HEADER
525 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
526 select SPL_SEPARATE_BSS if SPL
528 config TARGET_ASPENITE
529 bool "Support aspenite"
531 select GPIO_EXTRA_HEADER
536 select GPIO_EXTRA_HEADER
537 select SPL_DM_SPI if SPL
540 Support for TI's DaVinci platform.
543 bool "Marvell Kirkwood"
544 select ARCH_MISC_INIT
545 select BOARD_EARLY_INIT_F
547 select GPIO_EXTRA_HEADER
550 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
556 select GPIO_EXTRA_HEADER
557 select SPL_DM_SPI if SPL
558 select SPL_DM_SPI_FLASH if SPL
567 select GPIO_EXTRA_HEADER
569 config TARGET_SPEAR300
570 bool "Support spear300"
571 select BOARD_EARLY_INIT_F
573 select GPIO_EXTRA_HEADER
577 config TARGET_SPEAR310
578 bool "Support spear310"
579 select BOARD_EARLY_INIT_F
581 select GPIO_EXTRA_HEADER
585 config TARGET_SPEAR320
586 bool "Support spear320"
587 select BOARD_EARLY_INIT_F
589 select GPIO_EXTRA_HEADER
593 config TARGET_SPEAR600
594 bool "Support spear600"
595 select BOARD_EARLY_INIT_F
597 select GPIO_EXTRA_HEADER
601 config TARGET_STV0991
602 bool "Support stv0991"
608 select GPIO_EXTRA_HEADER
616 select BOARD_LATE_INIT
618 select GPIO_EXTRA_HEADER
625 select GPIO_EXTRA_HEADER
628 bool "Broadcom BCM283X family"
632 select GPIO_EXTRA_HEADER
635 select SERIAL_SEARCH_ALL
640 bool "Broadcom BCM63158 family"
646 bool "Broadcom BCM68360 family"
652 bool "Broadcom BCM6858 family"
658 bool "Broadcom BCM7XXX family"
661 select GPIO_EXTRA_HEADER
663 select OF_PRIOR_STAGE
666 This enables support for Broadcom ARM-based set-top box
667 chipsets, including the 7445 family of chips.
669 config TARGET_BCMCYGNUS
670 bool "Support bcmcygnus"
672 select GPIO_EXTRA_HEADER
674 imply BCM_SF2_ETH_GMAC
682 bool "Support Broadcom Northstar2"
684 select GPIO_EXTRA_HEADER
686 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
687 ARMv8 Cortex-A57 processors targeting a broad range of networking
691 bool "Support Broadcom NS3"
693 select BOARD_LATE_INIT
695 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
696 ARMv8 Cortex-A72 processors targeting a broad range of networking
700 bool "Samsung EXYNOS"
709 select GPIO_EXTRA_HEADER
710 imply SYS_THUMB_BUILD
715 bool "Samsung S5PC1XX"
721 select GPIO_EXTRA_HEADER
725 bool "Calxeda Highbank"
738 config ARCH_INTEGRATOR
739 bool "ARM Ltd. Integrator family"
742 select GPIO_EXTRA_HEADER
747 bool "Qualcomm IPQ40xx SoCs"
753 select GPIO_EXTRA_HEADER
765 select GPIO_EXTRA_HEADER
767 select SYS_ARCH_TIMER
768 select SYS_THUMB_BUILD
774 bool "Texas Instruments' K3 Architecture"
779 config ARCH_OMAP2PLUS
782 select GPIO_EXTRA_HEADER
783 select SPL_BOARD_INIT if SPL
784 select SPL_STACK_R if SPL
786 imply TI_SYSC if DM && OF_CONTROL
791 select GPIO_EXTRA_HEADER
792 imply DISTRO_DEFAULTS
795 Support for the Meson SoC family developed by Amlogic Inc.,
796 targeted at media players and tablet computers. We currently
797 support the S905 (GXBaby) 64-bit SoC.
802 select GPIO_EXTRA_HEADER
805 select SPL_LIBCOMMON_SUPPORT if SPL
806 select SPL_LIBGENERIC_SUPPORT if SPL
807 select SPL_OF_CONTROL if SPL
810 Support for the MediaTek SoCs family developed by MediaTek Inc.
811 Please refer to doc/README.mediatek for more information.
814 bool "NXP LPC32xx platform"
819 select GPIO_EXTRA_HEADER
825 bool "NXP i.MX8 platform"
828 select GPIO_EXTRA_HEADER
830 select ENABLE_ARM_SOC_BOOT0_HOOK
833 bool "NXP i.MX8M platform"
835 select GPIO_EXTRA_HEADER
836 select SYS_FSL_HAS_SEC if IMX_HAB
837 select SYS_FSL_SEC_COMPAT_4
838 select SYS_FSL_SEC_LE
844 bool "NXP i.MXRT platform"
848 select GPIO_EXTRA_HEADER
853 bool "NXP i.MX23 family"
855 select GPIO_EXTRA_HEADER
862 select GPIO_EXTRA_HEADER
866 bool "NXP i.MX28 family"
868 select GPIO_EXTRA_HEADER
873 bool "NXP i.MX31 family"
875 select GPIO_EXTRA_HEADER
880 select GPIO_EXTRA_HEADER
881 select SYS_FSL_HAS_SEC if IMX_HAB
882 select SYS_FSL_SEC_COMPAT_4
883 select SYS_FSL_SEC_LE
884 select ROM_UNIFIED_SECTIONS
886 imply SYS_THUMB_BUILD
890 select ARCH_MISC_INIT
892 select GPIO_EXTRA_HEADER
893 select SYS_FSL_HAS_SEC if IMX_HAB
894 select SYS_FSL_SEC_COMPAT_4
895 select SYS_FSL_SEC_LE
896 imply BOARD_EARLY_INIT_F
898 imply SYS_THUMB_BUILD
903 select GPIO_EXTRA_HEADER
904 select SYS_FSL_HAS_SEC
905 select SYS_FSL_SEC_COMPAT_4
906 select SYS_FSL_SEC_LE
908 imply SYS_THUMB_BUILD
912 default "arch/arm/mach-omap2/u-boot-spl.lds"
917 select BOARD_EARLY_INIT_F
919 select GPIO_EXTRA_HEADER
923 bool "Nexell S5P4418/S5P6818 SoC"
924 select ENABLE_ARM_SOC_BOOT0_HOOK
926 select GPIO_EXTRA_HEADER
929 bool "Actions Semi OWL SoCs"
933 select GPIO_EXTRA_HEADER
938 select SYS_RELOC_GD_ENV_ADDR
942 bool "QEMU Virtual Platform"
953 bool "Renesas ARM SoCs"
956 select GPIO_EXTRA_HEADER
957 imply BOARD_EARLY_INIT_F
960 imply SYS_THUMB_BUILD
961 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
963 config ARCH_SNAPDRAGON
964 bool "Qualcomm Snapdragon SoCs"
969 select GPIO_EXTRA_HEADER
978 bool "Altera SOCFPGA family"
979 select ARCH_EARLY_INIT_R
980 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
981 select ARM64 if TARGET_SOCFPGA_SOC64
982 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
985 select GPIO_EXTRA_HEADER
986 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
988 select SPL_DM_RESET if DM_RESET
990 select SPL_LIBCOMMON_SUPPORT
991 select SPL_LIBGENERIC_SUPPORT
992 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
993 select SPL_OF_CONTROL
994 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
995 select SPL_SERIAL_SUPPORT
997 select SPL_WATCHDOG_SUPPORT
1000 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1002 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1003 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1013 imply SPL_DM_SPI_FLASH
1014 imply SPL_LIBDISK_SUPPORT
1015 imply SPL_MMC_SUPPORT
1016 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1017 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1018 imply SPL_SPI_FLASH_SUPPORT
1019 imply SPL_SPI_SUPPORT
1023 bool "Support sunxi (Allwinner) SoCs"
1026 select CMD_MMC if MMC
1027 select CMD_USB if DISTRO_DEFAULTS
1033 select DM_MMC if MMC
1034 select DM_SCSI if SCSI
1036 select DM_USB if DISTRO_DEFAULTS
1037 select GPIO_EXTRA_HEADER
1038 select OF_BOARD_SETUP
1041 select SPECIFY_CONSOLE_INDEX
1042 select SPL_STACK_R if SPL
1043 select SPL_SYS_MALLOC_SIMPLE if SPL
1044 select SPL_SYS_THUMB_BUILD if !ARM64
1047 select SYS_THUMB_BUILD if !ARM64
1048 select USB if DISTRO_DEFAULTS
1049 select USB_KEYBOARD if DISTRO_DEFAULTS
1050 select USB_STORAGE if DISTRO_DEFAULTS
1051 select SPL_USE_TINY_PRINTF
1053 select SYS_RELOC_GD_ENV_ADDR
1054 imply BOARD_LATE_INIT
1057 imply CMD_UBI if MTD_RAW_NAND
1058 imply DISTRO_DEFAULTS
1061 imply OF_LIBFDT_OVERLAY
1062 imply PRE_CONSOLE_BUFFER
1063 imply SPL_GPIO_SUPPORT
1064 imply SPL_LIBCOMMON_SUPPORT
1065 imply SPL_LIBGENERIC_SUPPORT
1066 imply SPL_MMC_SUPPORT if MMC
1067 imply SPL_POWER_SUPPORT
1068 imply SPL_SERIAL_SUPPORT
1072 bool "ST-Ericsson U8500 Series"
1076 select DM_MMC if MMC
1078 select DM_USB if USB
1082 imply ARM_PL180_MMCI
1084 imply NOMADIK_MTU_TIMER
1087 imply SYSRESET_SYSCON
1090 bool "Support Xilinx Versal Platform"
1094 select DM_ETH if NET
1095 select DM_MMC if MMC
1097 select GPIO_EXTRA_HEADER
1099 imply BOARD_LATE_INIT
1100 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1103 bool "Freescale Vybrid"
1105 select GPIO_EXTRA_HEADER
1106 select SYS_FSL_ERRATUM_ESDHC111
1111 bool "Xilinx Zynq based platform"
1116 select DM_ETH if NET
1117 select DM_MMC if MMC
1121 select DM_USB if USB
1122 select GPIO_EXTRA_HEADER
1125 select SPL_BOARD_INIT if SPL
1126 select SPL_CLK if SPL
1127 select SPL_DM if SPL
1128 select SPL_DM_SPI if SPL
1129 select SPL_DM_SPI_FLASH if SPL
1130 select SPL_OF_CONTROL if SPL
1131 select SPL_SEPARATE_BSS if SPL
1133 imply ARCH_EARLY_INIT_R
1134 imply BOARD_LATE_INIT
1138 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1141 config ARCH_ZYNQMP_R5
1142 bool "Xilinx ZynqMP R5 based platform"
1146 select DM_ETH if NET
1147 select DM_MMC if MMC
1149 select GPIO_EXTRA_HEADER
1155 bool "Xilinx ZynqMP based platform"
1159 select DM_ETH if NET
1161 select DM_MMC if MMC
1163 select DM_SPI if SPI
1164 select DM_SPI_FLASH if DM_SPI
1165 select DM_USB if USB
1167 select GPIO_EXTRA_HEADER
1169 select SPL_BOARD_INIT if SPL
1170 select SPL_CLK if SPL
1171 select SPL_DM if SPL
1172 select SPL_DM_SPI if SPI && SPL_DM
1173 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1174 select SPL_DM_MAILBOX if SPL
1175 select SPL_FIRMWARE if SPL
1176 select SPL_SEPARATE_BSS if SPL
1179 imply BOARD_LATE_INIT
1181 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1188 select GPIO_EXTRA_HEADER
1189 imply DISTRO_DEFAULTS
1192 config TARGET_VEXPRESS64_AEMV8A
1193 bool "Support vexpress_aemv8a"
1195 select GPIO_EXTRA_HEADER
1198 config TARGET_VEXPRESS64_BASE_FVP
1199 bool "Support Versatile Express ARMv8a FVP BASE model"
1201 select GPIO_EXTRA_HEADER
1205 config TARGET_VEXPRESS64_JUNO
1206 bool "Support Versatile Express Juno Development Platform"
1208 select GPIO_EXTRA_HEADER
1222 config TARGET_TOTAL_COMPUTE
1223 bool "Support Total Compute Platform"
1231 config TARGET_LS2080A_EMU
1232 bool "Support ls2080a_emu"
1235 select ARMV8_MULTIENTRY
1236 select FSL_DDR_SYNC_REFRESH
1237 select GPIO_EXTRA_HEADER
1239 Support for Freescale LS2080A_EMU platform.
1240 The LS2080A Development System (EMULATOR) is a pre-silicon
1241 development platform that supports the QorIQ LS2080A
1242 Layerscape Architecture processor.
1244 config TARGET_LS1088AQDS
1245 bool "Support ls1088aqds"
1248 select ARMV8_MULTIENTRY
1249 select ARCH_SUPPORT_TFABOOT
1250 select BOARD_LATE_INIT
1251 select GPIO_EXTRA_HEADER
1253 select FSL_DDR_INTERACTIVE if !SD_BOOT
1255 Support for NXP LS1088AQDS platform.
1256 The LS1088A Development System (QDS) is a high-performance
1257 development platform that supports the QorIQ LS1088A
1258 Layerscape Architecture processor.
1260 config TARGET_LS2080AQDS
1261 bool "Support ls2080aqds"
1264 select ARMV8_MULTIENTRY
1265 select ARCH_SUPPORT_TFABOOT
1266 select BOARD_LATE_INIT
1267 select GPIO_EXTRA_HEADER
1272 select FSL_DDR_INTERACTIVE if !SPL
1274 Support for Freescale LS2080AQDS platform.
1275 The LS2080A Development System (QDS) is a high-performance
1276 development platform that supports the QorIQ LS2080A
1277 Layerscape Architecture processor.
1279 config TARGET_LS2080ARDB
1280 bool "Support ls2080ardb"
1283 select ARMV8_MULTIENTRY
1284 select ARCH_SUPPORT_TFABOOT
1285 select BOARD_LATE_INIT
1288 select FSL_DDR_INTERACTIVE if !SPL
1289 select GPIO_EXTRA_HEADER
1293 Support for Freescale LS2080ARDB platform.
1294 The LS2080A Reference design board (RDB) is a high-performance
1295 development platform that supports the QorIQ LS2080A
1296 Layerscape Architecture processor.
1298 config TARGET_LS2081ARDB
1299 bool "Support ls2081ardb"
1302 select ARMV8_MULTIENTRY
1303 select BOARD_LATE_INIT
1304 select GPIO_EXTRA_HEADER
1307 Support for Freescale LS2081ARDB platform.
1308 The LS2081A Reference design board (RDB) is a high-performance
1309 development platform that supports the QorIQ LS2081A/LS2041A
1310 Layerscape Architecture processor.
1312 config TARGET_LX2160ARDB
1313 bool "Support lx2160ardb"
1316 select ARMV8_MULTIENTRY
1317 select ARCH_SUPPORT_TFABOOT
1318 select BOARD_LATE_INIT
1319 select GPIO_EXTRA_HEADER
1321 Support for NXP LX2160ARDB platform.
1322 The lx2160ardb (LX2160A Reference design board (RDB)
1323 is a high-performance development platform that supports the
1324 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1326 config TARGET_LX2160AQDS
1327 bool "Support lx2160aqds"
1330 select ARMV8_MULTIENTRY
1331 select ARCH_SUPPORT_TFABOOT
1332 select BOARD_LATE_INIT
1333 select GPIO_EXTRA_HEADER
1335 Support for NXP LX2160AQDS platform.
1336 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1337 is a high-performance development platform that supports the
1338 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1340 config TARGET_LX2162AQDS
1341 bool "Support lx2162aqds"
1343 select ARCH_MISC_INIT
1345 select ARMV8_MULTIENTRY
1346 select ARCH_SUPPORT_TFABOOT
1347 select BOARD_LATE_INIT
1348 select GPIO_EXTRA_HEADER
1350 Support for NXP LX2162AQDS platform.
1351 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1354 bool "Support HiKey 96boards Consumer Edition Platform"
1359 select GPIO_EXTRA_HEADER
1362 select SPECIFY_CONSOLE_INDEX
1365 Support for HiKey 96boards platform. It features a HI6220
1366 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1368 config TARGET_HIKEY960
1369 bool "Support HiKey960 96boards Consumer Edition Platform"
1373 select GPIO_EXTRA_HEADER
1378 Support for HiKey960 96boards platform. It features a HI3660
1379 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1381 config TARGET_POPLAR
1382 bool "Support Poplar 96boards Enterprise Edition Platform"
1387 select GPIO_EXTRA_HEADER
1392 Support for Poplar 96boards EE platform. It features a HI3798cv200
1393 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1394 making it capable of running any commercial set-top solution based on
1397 config TARGET_LS1012AQDS
1398 bool "Support ls1012aqds"
1401 select ARCH_SUPPORT_TFABOOT
1402 select BOARD_LATE_INIT
1403 select GPIO_EXTRA_HEADER
1405 Support for Freescale LS1012AQDS platform.
1406 The LS1012A Development System (QDS) is a high-performance
1407 development platform that supports the QorIQ LS1012A
1408 Layerscape Architecture processor.
1410 config TARGET_LS1012ARDB
1411 bool "Support ls1012ardb"
1414 select ARCH_SUPPORT_TFABOOT
1415 select BOARD_LATE_INIT
1416 select GPIO_EXTRA_HEADER
1420 Support for Freescale LS1012ARDB platform.
1421 The LS1012A Reference design board (RDB) is a high-performance
1422 development platform that supports the QorIQ LS1012A
1423 Layerscape Architecture processor.
1425 config TARGET_LS1012A2G5RDB
1426 bool "Support ls1012a2g5rdb"
1429 select ARCH_SUPPORT_TFABOOT
1430 select BOARD_LATE_INIT
1431 select GPIO_EXTRA_HEADER
1434 Support for Freescale LS1012A2G5RDB platform.
1435 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1436 development platform that supports the QorIQ LS1012A
1437 Layerscape Architecture processor.
1439 config TARGET_LS1012AFRWY
1440 bool "Support ls1012afrwy"
1443 select ARCH_SUPPORT_TFABOOT
1444 select BOARD_LATE_INIT
1445 select GPIO_EXTRA_HEADER
1449 Support for Freescale LS1012AFRWY platform.
1450 The LS1012A FRWY board (FRWY) is a high-performance
1451 development platform that supports the QorIQ LS1012A
1452 Layerscape Architecture processor.
1454 config TARGET_LS1012AFRDM
1455 bool "Support ls1012afrdm"
1458 select ARCH_SUPPORT_TFABOOT
1459 select GPIO_EXTRA_HEADER
1461 Support for Freescale LS1012AFRDM platform.
1462 The LS1012A Freedom board (FRDM) is a high-performance
1463 development platform that supports the QorIQ LS1012A
1464 Layerscape Architecture processor.
1466 config TARGET_LS1028AQDS
1467 bool "Support ls1028aqds"
1470 select ARMV8_MULTIENTRY
1471 select ARCH_SUPPORT_TFABOOT
1472 select BOARD_LATE_INIT
1473 select GPIO_EXTRA_HEADER
1475 Support for Freescale LS1028AQDS platform
1476 The LS1028A Development System (QDS) is a high-performance
1477 development platform that supports the QorIQ LS1028A
1478 Layerscape Architecture processor.
1480 config TARGET_LS1028ARDB
1481 bool "Support ls1028ardb"
1484 select ARMV8_MULTIENTRY
1485 select ARCH_SUPPORT_TFABOOT
1486 select BOARD_LATE_INIT
1487 select GPIO_EXTRA_HEADER
1489 Support for Freescale LS1028ARDB platform
1490 The LS1028A Development System (RDB) is a high-performance
1491 development platform that supports the QorIQ LS1028A
1492 Layerscape Architecture processor.
1494 config TARGET_LS1088ARDB
1495 bool "Support ls1088ardb"
1498 select ARMV8_MULTIENTRY
1499 select ARCH_SUPPORT_TFABOOT
1500 select BOARD_LATE_INIT
1502 select FSL_DDR_INTERACTIVE if !SD_BOOT
1503 select GPIO_EXTRA_HEADER
1505 Support for NXP LS1088ARDB platform.
1506 The LS1088A Reference design board (RDB) is a high-performance
1507 development platform that supports the QorIQ LS1088A
1508 Layerscape Architecture processor.
1510 config TARGET_LS1021AQDS
1511 bool "Support ls1021aqds"
1513 select ARCH_SUPPORT_PSCI
1514 select BOARD_EARLY_INIT_F
1515 select BOARD_LATE_INIT
1517 select CPU_V7_HAS_NONSEC
1518 select CPU_V7_HAS_VIRT
1519 select LS1_DEEP_SLEEP
1522 select FSL_DDR_INTERACTIVE
1523 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1524 select GPIO_EXTRA_HEADER
1525 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1528 config TARGET_LS1021ATWR
1529 bool "Support ls1021atwr"
1531 select ARCH_SUPPORT_PSCI
1532 select BOARD_EARLY_INIT_F
1533 select BOARD_LATE_INIT
1535 select CPU_V7_HAS_NONSEC
1536 select CPU_V7_HAS_VIRT
1537 select LS1_DEEP_SLEEP
1539 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1540 select GPIO_EXTRA_HEADER
1543 config TARGET_PG_WCOM_SELI8
1544 bool "Support Hitachi-Powergrids SELI8 service unit card"
1546 select ARCH_SUPPORT_PSCI
1547 select BOARD_EARLY_INIT_F
1548 select BOARD_LATE_INIT
1550 select CPU_V7_HAS_NONSEC
1551 select CPU_V7_HAS_VIRT
1553 select FSL_DDR_INTERACTIVE
1554 select GPIO_EXTRA_HEADER
1558 Support for Hitachi-Powergrids SELI8 service unit card.
1559 SELI8 is a QorIQ LS1021a based service unit card used
1560 in XMC20 and FOX615 product families.
1562 config TARGET_PG_WCOM_EXPU1
1563 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1565 select ARCH_SUPPORT_PSCI
1566 select BOARD_EARLY_INIT_F
1567 select BOARD_LATE_INIT
1569 select CPU_V7_HAS_NONSEC
1570 select CPU_V7_HAS_VIRT
1572 select FSL_DDR_INTERACTIVE
1576 Support for Hitachi-Powergrids EXPU1 service unit card.
1577 EXPU1 is a QorIQ LS1021a based service unit card used
1578 in XMC20 and FOX615 product families.
1580 config TARGET_LS1021ATSN
1581 bool "Support ls1021atsn"
1583 select ARCH_SUPPORT_PSCI
1584 select BOARD_EARLY_INIT_F
1585 select BOARD_LATE_INIT
1587 select CPU_V7_HAS_NONSEC
1588 select CPU_V7_HAS_VIRT
1589 select LS1_DEEP_SLEEP
1591 select GPIO_EXTRA_HEADER
1594 config TARGET_LS1021AIOT
1595 bool "Support ls1021aiot"
1597 select ARCH_SUPPORT_PSCI
1598 select BOARD_LATE_INIT
1600 select CPU_V7_HAS_NONSEC
1601 select CPU_V7_HAS_VIRT
1603 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1604 select GPIO_EXTRA_HEADER
1607 Support for Freescale LS1021AIOT platform.
1608 The LS1021A Freescale board (IOT) is a high-performance
1609 development platform that supports the QorIQ LS1021A
1610 Layerscape Architecture processor.
1612 config TARGET_LS1043AQDS
1613 bool "Support ls1043aqds"
1616 select ARMV8_MULTIENTRY
1617 select ARCH_SUPPORT_TFABOOT
1618 select BOARD_EARLY_INIT_F
1619 select BOARD_LATE_INIT
1621 select FSL_DDR_INTERACTIVE if !SPL
1622 select FSL_DSPI if !SPL_NO_DSPI
1623 select DM_SPI_FLASH if FSL_DSPI
1624 select GPIO_EXTRA_HEADER
1628 Support for Freescale LS1043AQDS platform.
1630 config TARGET_LS1043ARDB
1631 bool "Support ls1043ardb"
1634 select ARMV8_MULTIENTRY
1635 select ARCH_SUPPORT_TFABOOT
1636 select BOARD_EARLY_INIT_F
1637 select BOARD_LATE_INIT
1639 select FSL_DSPI if !SPL_NO_DSPI
1640 select DM_SPI_FLASH if FSL_DSPI
1641 select GPIO_EXTRA_HEADER
1643 Support for Freescale LS1043ARDB platform.
1645 config TARGET_LS1046AQDS
1646 bool "Support ls1046aqds"
1649 select ARMV8_MULTIENTRY
1650 select ARCH_SUPPORT_TFABOOT
1651 select BOARD_EARLY_INIT_F
1652 select BOARD_LATE_INIT
1653 select DM_SPI_FLASH if DM_SPI
1655 select FSL_DDR_BIST if !SPL
1656 select FSL_DDR_INTERACTIVE if !SPL
1657 select FSL_DDR_INTERACTIVE if !SPL
1658 select GPIO_EXTRA_HEADER
1661 Support for Freescale LS1046AQDS platform.
1662 The LS1046A Development System (QDS) is a high-performance
1663 development platform that supports the QorIQ LS1046A
1664 Layerscape Architecture processor.
1666 config TARGET_LS1046ARDB
1667 bool "Support ls1046ardb"
1670 select ARMV8_MULTIENTRY
1671 select ARCH_SUPPORT_TFABOOT
1672 select BOARD_EARLY_INIT_F
1673 select BOARD_LATE_INIT
1674 select DM_SPI_FLASH if DM_SPI
1675 select POWER_MC34VR500
1678 select FSL_DDR_INTERACTIVE if !SPL
1679 select GPIO_EXTRA_HEADER
1682 Support for Freescale LS1046ARDB platform.
1683 The LS1046A Reference Design Board (RDB) is a high-performance
1684 development platform that supports the QorIQ LS1046A
1685 Layerscape Architecture processor.
1687 config TARGET_LS1046AFRWY
1688 bool "Support ls1046afrwy"
1691 select ARMV8_MULTIENTRY
1692 select ARCH_SUPPORT_TFABOOT
1693 select BOARD_EARLY_INIT_F
1694 select BOARD_LATE_INIT
1695 select DM_SPI_FLASH if DM_SPI
1696 select GPIO_EXTRA_HEADER
1699 Support for Freescale LS1046AFRWY platform.
1700 The LS1046A Freeway Board (FRWY) is a high-performance
1701 development platform that supports the QorIQ LS1046A
1702 Layerscape Architecture processor.
1708 select ARMV8_MULTIENTRY
1725 select GPIO_EXTRA_HEADER
1726 select SPL_DM if SPL
1727 select SPL_DM_SPI if SPL
1728 select SPL_DM_SPI_FLASH if SPL
1729 select SPL_DM_I2C if SPL
1730 select SPL_DM_MMC if SPL
1731 select SPL_DM_SERIAL if SPL
1733 Support for Kontron SMARC-sAL28 board.
1735 config TARGET_COLIBRI_PXA270
1736 bool "Support colibri_pxa270"
1738 select GPIO_EXTRA_HEADER
1740 config ARCH_UNIPHIER
1741 bool "Socionext UniPhier SoCs"
1742 select BOARD_LATE_INIT
1752 select OF_BOARD_SETUP
1756 select SPL_BOARD_INIT if SPL
1757 select SPL_DM if SPL
1758 select SPL_LIBCOMMON_SUPPORT if SPL
1759 select SPL_LIBGENERIC_SUPPORT if SPL
1760 select SPL_OF_CONTROL if SPL
1761 select SPL_PINCTRL if SPL
1764 imply DISTRO_DEFAULTS
1767 Support for UniPhier SoC family developed by Socionext Inc.
1768 (formerly, System LSI Business Division of Panasonic Corporation)
1770 config ARCH_SYNQUACER
1771 bool "Socionext SynQuacer SoCs"
1777 select SYSRESET_PSCI
1780 Support for SynQuacer SoC family developed by Socionext Inc.
1781 This SoC is used on 96boards EE DeveloperBox.
1784 bool "Support STMicroelectronics STM32 MCU with cortex M"
1788 select GPIO_EXTRA_HEADER
1792 bool "Support STMicrolectronics SoCs"
1801 Support for STMicroelectronics STiH407/10 SoC family.
1802 This SoC is used on Linaro 96Board STiH410-B2260
1805 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1806 select ARCH_MISC_INIT
1807 select ARCH_SUPPORT_TFABOOT
1808 select BOARD_LATE_INIT
1814 select GPIO_EXTRA_HEADER
1818 select OF_SYSTEM_SETUP
1824 select SYS_THUMB_BUILD
1828 imply OF_LIBFDT_OVERLAY
1829 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1832 Support for STM32MP SoC family developed by STMicroelectronics,
1833 MPUs based on ARM cortex A core
1834 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1835 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1837 SPL is the unsecure FSBL for the basic boot chain.
1839 config ARCH_ROCKCHIP
1840 bool "Support Rockchip SoCs"
1842 select BINMAN if SPL_OPTEE
1852 select DM_USB if USB
1853 select ENABLE_ARM_SOC_BOOT0_HOOK
1856 select SPL_DM if SPL
1857 select SPL_DM_SPI if SPL
1858 select SPL_DM_SPI_FLASH if SPL
1860 select SYS_THUMB_BUILD if !ARM64
1863 imply DEBUG_UART_BOARD_INIT
1864 imply DISTRO_DEFAULTS
1866 imply SARADC_ROCKCHIP
1868 imply SPL_SYS_MALLOC_SIMPLE
1871 imply USB_FUNCTION_FASTBOOT
1873 config ARCH_OCTEONTX
1874 bool "Support OcteonTX SoCs"
1877 select GPIO_EXTRA_HEADER
1881 select BOARD_LATE_INIT
1882 select SYS_CACHE_SHIFT_7
1884 config ARCH_OCTEONTX2
1885 bool "Support OcteonTX2 SoCs"
1888 select GPIO_EXTRA_HEADER
1892 select BOARD_LATE_INIT
1893 select SYS_CACHE_SHIFT_7
1895 config TARGET_THUNDERX_88XX
1896 bool "Support ThunderX 88xx"
1898 select GPIO_EXTRA_HEADER
1901 select SYS_CACHE_SHIFT_7
1904 bool "Support Aspeed SoCs"
1909 config TARGET_DURIAN
1910 bool "Support Phytium Durian Platform"
1912 select GPIO_EXTRA_HEADER
1914 Support for durian platform.
1915 It has 2GB Sdram, uart and pcie.
1917 config TARGET_PRESIDIO_ASIC
1918 bool "Support Cortina Presidio ASIC Platform"
1921 config TARGET_XENGUEST_ARM64
1922 bool "Xen guest ARM64"
1926 select LINUX_KERNEL_IMAGE_HEADER
1931 config ARCH_SUPPORT_TFABOOT
1935 bool "Support for booting from TF-A"
1936 depends on ARCH_SUPPORT_TFABOOT
1939 Some platforms support the setup of secure registers (for instance
1940 for CPU errata handling) or provide secure services like PSCI.
1941 Those services could also be provided by other firmware parts
1942 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
1943 does not need to (and cannot) execute this code.
1944 Enabling this option will make a U-Boot binary that is relying
1945 on other firmware layers to provide secure functionality.
1947 config TI_SECURE_DEVICE
1948 bool "HS Device Type Support"
1949 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1951 If a high secure (HS) device type is being used, this config
1952 must be set. This option impacts various aspects of the
1953 build system (to create signed boot images that can be
1954 authenticated) and the code. See the doc/README.ti-secure
1955 file for further details.
1957 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1958 config ISW_ENTRY_ADDR
1959 hex "Address in memory or XIP address of bootloader entry point"
1960 default 0x402F4000 if AM43XX
1961 default 0x402F0400 if AM33XX
1962 default 0x40301350 if OMAP54XX
1964 After any reset, the boot ROM searches the boot media for a valid
1965 boot image. For non-XIP devices, the ROM then copies the image into
1966 internal memory. For all boot modes, after the ROM processes the
1967 boot image it eventually computes the entry point address depending
1968 on the device type (secure/non-secure), boot media (xip/non-xip) and
1972 source "arch/arm/mach-aspeed/Kconfig"
1974 source "arch/arm/mach-at91/Kconfig"
1976 source "arch/arm/mach-bcm283x/Kconfig"
1978 source "arch/arm/mach-bcmstb/Kconfig"
1980 source "arch/arm/mach-davinci/Kconfig"
1982 source "arch/arm/mach-exynos/Kconfig"
1984 source "arch/arm/mach-highbank/Kconfig"
1986 source "arch/arm/mach-integrator/Kconfig"
1988 source "arch/arm/mach-ipq40xx/Kconfig"
1990 source "arch/arm/mach-k3/Kconfig"
1992 source "arch/arm/mach-keystone/Kconfig"
1994 source "arch/arm/mach-kirkwood/Kconfig"
1996 source "arch/arm/mach-lpc32xx/Kconfig"
1998 source "arch/arm/mach-mvebu/Kconfig"
2000 source "arch/arm/mach-octeontx/Kconfig"
2002 source "arch/arm/mach-octeontx2/Kconfig"
2004 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2006 source "arch/arm/mach-imx/mx2/Kconfig"
2008 source "arch/arm/mach-imx/mx3/Kconfig"
2010 source "arch/arm/mach-imx/mx5/Kconfig"
2012 source "arch/arm/mach-imx/mx6/Kconfig"
2014 source "arch/arm/mach-imx/mx7/Kconfig"
2016 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2018 source "arch/arm/mach-imx/imx8/Kconfig"
2020 source "arch/arm/mach-imx/imx8m/Kconfig"
2022 source "arch/arm/mach-imx/imxrt/Kconfig"
2024 source "arch/arm/mach-imx/mxs/Kconfig"
2026 source "arch/arm/mach-omap2/Kconfig"
2028 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2030 source "arch/arm/mach-orion5x/Kconfig"
2032 source "arch/arm/mach-owl/Kconfig"
2034 source "arch/arm/mach-rmobile/Kconfig"
2036 source "arch/arm/mach-meson/Kconfig"
2038 source "arch/arm/mach-mediatek/Kconfig"
2040 source "arch/arm/mach-qemu/Kconfig"
2042 source "arch/arm/mach-rockchip/Kconfig"
2044 source "arch/arm/mach-s5pc1xx/Kconfig"
2046 source "arch/arm/mach-snapdragon/Kconfig"
2048 source "arch/arm/mach-socfpga/Kconfig"
2050 source "arch/arm/mach-sti/Kconfig"
2052 source "arch/arm/mach-stm32/Kconfig"
2054 source "arch/arm/mach-stm32mp/Kconfig"
2056 source "arch/arm/mach-sunxi/Kconfig"
2058 source "arch/arm/mach-tegra/Kconfig"
2060 source "arch/arm/mach-u8500/Kconfig"
2062 source "arch/arm/mach-uniphier/Kconfig"
2064 source "arch/arm/cpu/armv7/vf610/Kconfig"
2066 source "arch/arm/mach-zynq/Kconfig"
2068 source "arch/arm/mach-zynqmp/Kconfig"
2070 source "arch/arm/mach-versal/Kconfig"
2072 source "arch/arm/mach-zynqmp-r5/Kconfig"
2074 source "arch/arm/cpu/armv7/Kconfig"
2076 source "arch/arm/cpu/armv8/Kconfig"
2078 source "arch/arm/mach-imx/Kconfig"
2080 source "arch/arm/mach-nexell/Kconfig"
2082 source "board/armltd/total_compute/Kconfig"
2084 source "board/bosch/shc/Kconfig"
2085 source "board/bosch/guardian/Kconfig"
2086 source "board/CarMediaLab/flea3/Kconfig"
2087 source "board/Marvell/aspenite/Kconfig"
2088 source "board/Marvell/octeontx/Kconfig"
2089 source "board/Marvell/octeontx2/Kconfig"
2090 source "board/armltd/vexpress64/Kconfig"
2091 source "board/cortina/presidio-asic/Kconfig"
2092 source "board/broadcom/bcm963158/Kconfig"
2093 source "board/broadcom/bcm968360bg/Kconfig"
2094 source "board/broadcom/bcm968580xref/Kconfig"
2095 source "board/broadcom/bcmns3/Kconfig"
2096 source "board/cavium/thunderx/Kconfig"
2097 source "board/eets/pdu001/Kconfig"
2098 source "board/emulation/qemu-arm/Kconfig"
2099 source "board/freescale/ls2080aqds/Kconfig"
2100 source "board/freescale/ls2080ardb/Kconfig"
2101 source "board/freescale/ls1088a/Kconfig"
2102 source "board/freescale/ls1028a/Kconfig"
2103 source "board/freescale/ls1021aqds/Kconfig"
2104 source "board/freescale/ls1043aqds/Kconfig"
2105 source "board/freescale/ls1021atwr/Kconfig"
2106 source "board/freescale/ls1021atsn/Kconfig"
2107 source "board/freescale/ls1021aiot/Kconfig"
2108 source "board/freescale/ls1046aqds/Kconfig"
2109 source "board/freescale/ls1043ardb/Kconfig"
2110 source "board/freescale/ls1046ardb/Kconfig"
2111 source "board/freescale/ls1046afrwy/Kconfig"
2112 source "board/freescale/ls1012aqds/Kconfig"
2113 source "board/freescale/ls1012ardb/Kconfig"
2114 source "board/freescale/ls1012afrdm/Kconfig"
2115 source "board/freescale/lx2160a/Kconfig"
2116 source "board/grinn/chiliboard/Kconfig"
2117 source "board/hisilicon/hikey/Kconfig"
2118 source "board/hisilicon/hikey960/Kconfig"
2119 source "board/hisilicon/poplar/Kconfig"
2120 source "board/isee/igep003x/Kconfig"
2121 source "board/kontron/sl28/Kconfig"
2122 source "board/myir/mys_6ulx/Kconfig"
2123 source "board/seeed/npi_imx6ull/Kconfig"
2124 source "board/socionext/developerbox/Kconfig"
2125 source "board/spear/spear300/Kconfig"
2126 source "board/spear/spear310/Kconfig"
2127 source "board/spear/spear320/Kconfig"
2128 source "board/spear/spear600/Kconfig"
2129 source "board/spear/x600/Kconfig"
2130 source "board/st/stv0991/Kconfig"
2131 source "board/tcl/sl50/Kconfig"
2132 source "board/toradex/colibri_pxa270/Kconfig"
2133 source "board/variscite/dart_6ul/Kconfig"
2134 source "board/vscom/baltos/Kconfig"
2135 source "board/phytium/durian/Kconfig"
2136 source "board/xen/xenguest_arm64/Kconfig"
2137 source "board/keymile/Kconfig"
2139 source "arch/arm/Kconfig.debug"
2144 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
2145 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
2146 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64