1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
17 be loaded to and run from that address. This option lifts that
18 restriction, thus allowing the code to be loaded to and executed from
19 almost any 4K aligned address. This logic relies on the relocation
20 information that is embedded in the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
23 config INIT_SP_RELATIVE
24 bool "Specify the early stack pointer relative to the .bss section"
25 default n if ARCH_QEMU
26 default y if POSITION_INDEPENDENT
28 U-Boot typically uses a hard-coded value for the stack pointer
29 before relocation. Enable this option to instead calculate the
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that it can be loaded and executed at arbitrary
32 addresses and thus avoid using arbitrary addresses at runtime.
34 If this option is enabled, the early stack pointer is set to
35 &_bss_start with a offset value added. The offset is specified by
36 SYS_INIT_SP_BSS_OFFSET.
38 config SYS_INIT_SP_BSS_OFFSET
39 int "Early stack offset from the .bss base address"
40 depends on INIT_SP_RELATIVE
43 This option's value is the offset added to &_bss_start in order to
44 calculate the stack pointer. This offset should be large enough so
45 that the early malloc region, global data (gd), and early stack usage
46 do not overlap any appended DTB.
48 config LINUX_KERNEL_IMAGE_HEADER
51 Place a Linux kernel image header at the start of the U-Boot binary.
52 The format of the header is described in the Linux kernel source at
53 Documentation/arm64/booting.txt. This feature is useful since the
54 image header reports the amount of memory (BSS and similar) that
55 U-Boot needs to use, but which isn't part of the binary.
57 if LINUX_KERNEL_IMAGE_HEADER
58 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
61 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
62 TEXT_OFFSET value written to the Linux kernel image header.
72 ARM GICV3 Interrupt translation service (ITS).
73 Basic support for programming locality specific peripheral
74 interrupts (LPI) configuration tables and enable LPI tables.
75 LPI configuration table can be used by u-boot or Linux.
76 ARM GICV3 has limitation, once the LPI table is enabled, LPI
77 configuration table can not be re-programmed, unless GICV3 reset.
83 config DMA_ADDR_T_64BIT
93 config GPIO_EXTRA_HEADER
96 # Used for compatibility with asm files copied from the kernel
97 config ARM_ASM_UNIFIED
101 # Used for compatibility with asm files copied from the kernel
105 config SYS_ICACHE_OFF
106 bool "Do not enable icache"
109 Do not enable instruction cache in U-Boot.
111 config SPL_SYS_ICACHE_OFF
112 bool "Do not enable icache in SPL"
114 default SYS_ICACHE_OFF
116 Do not enable instruction cache in SPL.
118 config SYS_DCACHE_OFF
119 bool "Do not enable dcache"
122 Do not enable data cache in U-Boot.
124 config SPL_SYS_DCACHE_OFF
125 bool "Do not enable dcache in SPL"
127 default SYS_DCACHE_OFF
129 Do not enable data cache in SPL.
131 config SYS_ARM_CACHE_CP15
132 bool "CP15 based cache enabling support"
134 Select this if your processor suports enabling caches by using
138 bool "MMU-based Paged Memory Management Support"
139 select SYS_ARM_CACHE_CP15
141 Select if you want MMU-based virtualised addressing space
142 support via paged memory management.
145 bool 'Use the ARM v7 PMSA Compliant MPU'
147 Some ARM systems without an MMU have instead a Memory Protection
148 Unit (MPU) that defines the type and permissions for regions of
150 If your CPU has an MPU then you should choose 'y' here unless you
151 know that you do not want to use the MPU.
153 # If set, the workarounds for these ARM errata are applied early during U-Boot
154 # startup. Note that in general these options force the workarounds to be
155 # applied; no CPU-type/version detection exists, unlike the similar options in
156 # the Linux kernel. Do not set these options unless they apply! Also note that
157 # the following can be machine-specific errata. These do have ability to
158 # provide rudimentary version and machine-specific checks, but expect no
160 # CONFIG_ARM_ERRATA_430973
161 # CONFIG_ARM_ERRATA_454179
162 # CONFIG_ARM_ERRATA_621766
163 # CONFIG_ARM_ERRATA_798870
164 # CONFIG_ARM_ERRATA_801819
165 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
166 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
168 config ARM_ERRATA_430973
171 config ARM_ERRATA_454179
174 config ARM_ERRATA_621766
177 config ARM_ERRATA_716044
180 config ARM_ERRATA_725233
183 config ARM_ERRATA_742230
186 config ARM_ERRATA_743622
189 config ARM_ERRATA_751472
192 config ARM_ERRATA_761320
195 config ARM_ERRATA_773022
198 config ARM_ERRATA_774769
201 config ARM_ERRATA_794072
204 config ARM_ERRATA_798870
207 config ARM_ERRATA_801819
210 config ARM_ERRATA_826974
213 config ARM_ERRATA_828024
216 config ARM_ERRATA_829520
219 config ARM_ERRATA_833069
222 config ARM_ERRATA_833471
225 config ARM_ERRATA_845369
228 config ARM_ERRATA_852421
231 config ARM_ERRATA_852423
234 config ARM_ERRATA_855873
237 config ARM_CORTEX_A8_CVE_2017_5715
240 config ARM_CORTEX_A15_CVE_2017_5715
245 select SYS_CACHE_SHIFT_5
250 select SYS_CACHE_SHIFT_5
255 select SYS_CACHE_SHIFT_5
260 select SYS_CACHE_SHIFT_5
265 select SYS_CACHE_SHIFT_5
271 select SYS_CACHE_SHIFT_5
278 select SYS_CACHE_SHIFT_6
285 select SYS_CACHE_SHIFT_5
286 select SYS_THUMB_BUILD
292 select SYS_ARM_CACHE_CP15
294 select SYS_CACHE_SHIFT_6
298 select SYS_CACHE_SHIFT_5
303 select SYS_CACHE_SHIFT_5
307 default "arm720t" if CPU_ARM720T
308 default "arm920t" if CPU_ARM920T
309 default "arm926ejs" if CPU_ARM926EJS
310 default "arm946es" if CPU_ARM946ES
311 default "arm1136" if CPU_ARM1136
312 default "arm1176" if CPU_ARM1176
313 default "armv7" if CPU_V7A
314 default "armv7" if CPU_V7R
315 default "armv7m" if CPU_V7M
316 default "pxa" if CPU_PXA
317 default "sa1100" if CPU_SA1100
318 default "armv8" if ARM64
322 default 4 if CPU_ARM720T
323 default 4 if CPU_ARM920T
324 default 5 if CPU_ARM926EJS
325 default 5 if CPU_ARM946ES
326 default 6 if CPU_ARM1136
327 default 6 if CPU_ARM1176
332 default 4 if CPU_SA1100
335 config SYS_CACHE_SHIFT_5
338 config SYS_CACHE_SHIFT_6
341 config SYS_CACHE_SHIFT_7
344 config SYS_CACHELINE_SIZE
346 default 128 if SYS_CACHE_SHIFT_7
347 default 64 if SYS_CACHE_SHIFT_6
348 default 32 if SYS_CACHE_SHIFT_5
351 prompt "Select the ARM data write cache policy"
352 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
354 default SYS_ARM_CACHE_WRITEBACK
356 config SYS_ARM_CACHE_WRITEBACK
357 bool "Write-back (WB)"
359 A write updates the cache only and marks the cache line as dirty.
360 External memory is updated only when the line is evicted or explicitly
363 config SYS_ARM_CACHE_WRITETHROUGH
364 bool "Write-through (WT)"
366 A write updates both the cache and the external memory system.
367 This does not mark the cache line as dirty.
369 config SYS_ARM_CACHE_WRITEALLOC
370 bool "Write allocation (WA)"
372 A cache line is allocated on a write miss. This means that executing a
373 store instruction on the processor might cause a burst read to occur.
374 There is a linefill to obtain the data for the cache line, before the
379 bool "Enable ARCH_CPU_INIT"
381 Some architectures require a call to arch_cpu_init().
382 Say Y here to enable it
384 config SYS_ARCH_TIMER
385 bool "ARM Generic Timer support"
386 depends on CPU_V7A || ARM64
389 The ARM Generic Timer (aka arch-timer) provides an architected
390 interface to a timer source on an SoC.
391 It is mandatory for ARMv8 implementation and widely available
395 bool "Support for ARM SMC Calling Convention (SMCCC)"
396 depends on CPU_V7A || ARM64
399 Say Y here if you want to enable ARM SMC Calling Convention.
400 This should be enabled if U-Boot needs to communicate with system
401 firmware (for example, PSCI) according to SMCCC.
404 bool "support boot from semihosting"
406 In emulated environments, semihosting is a way for
407 the hosted environment to call out to the emulator to
408 retrieve files from the host machine.
410 config SYS_THUMB_BUILD
411 bool "Build U-Boot using the Thumb instruction set"
414 Use this flag to build U-Boot using the Thumb instruction set for
415 ARM architectures. Thumb instruction set provides better code
416 density. For ARM architectures that support Thumb2 this flag will
417 result in Thumb2 code generated by GCC.
419 config SPL_SYS_THUMB_BUILD
420 bool "Build SPL using the Thumb instruction set"
421 default y if SYS_THUMB_BUILD
422 depends on !ARM64 && SPL
424 Use this flag to build SPL using the Thumb instruction set for
425 ARM architectures. Thumb instruction set provides better code
426 density. For ARM architectures that support Thumb2 this flag will
427 result in Thumb2 code generated by GCC.
429 config TPL_SYS_THUMB_BUILD
430 bool "Build TPL using the Thumb instruction set"
431 default y if SYS_THUMB_BUILD
432 depends on TPL && !ARM64
434 Use this flag to build TPL using the Thumb instruction set for
435 ARM architectures. Thumb instruction set provides better code
436 density. For ARM architectures that support Thumb2 this flag will
437 result in Thumb2 code generated by GCC.
440 config SYS_L2CACHE_OFF
443 If SoC does not support L2CACHE or one does not want to enable
444 L2CACHE, choose this option.
446 config ENABLE_ARM_SOC_BOOT0_HOOK
447 bool "prepare BOOT0 header"
449 If the SoC's BOOT0 requires a header area filled with (magic)
450 values, then choose this option, and create a file included as
451 <asm/arch/boot0.h> which contains the required assembler code.
453 config ARM_CORTEX_CPU_IS_UP
457 config USE_ARCH_MEMCPY
458 bool "Use an assembly optimized implementation of memcpy"
462 Enable the generation of an optimized version of memcpy.
463 Such an implementation may be faster under some conditions
464 but may increase the binary size.
466 config SPL_USE_ARCH_MEMCPY
467 bool "Use an assembly optimized implementation of memcpy for SPL"
468 default y if USE_ARCH_MEMCPY
469 depends on !ARM64 && SPL
471 Enable the generation of an optimized version of memcpy.
472 Such an implementation may be faster under some conditions
473 but may increase the binary size.
475 config TPL_USE_ARCH_MEMCPY
476 bool "Use an assembly optimized implementation of memcpy for TPL"
477 default y if USE_ARCH_MEMCPY
478 depends on !ARM64 && TPL
480 Enable the generation of an optimized version of memcpy.
481 Such an implementation may be faster under some conditions
482 but may increase the binary size.
484 config USE_ARCH_MEMSET
485 bool "Use an assembly optimized implementation of memset"
489 Enable the generation of an optimized version of memset.
490 Such an implementation may be faster under some conditions
491 but may increase the binary size.
493 config SPL_USE_ARCH_MEMSET
494 bool "Use an assembly optimized implementation of memset for SPL"
495 default y if USE_ARCH_MEMSET
496 depends on !ARM64 && SPL
498 Enable the generation of an optimized version of memset.
499 Such an implementation may be faster under some conditions
500 but may increase the binary size.
502 config TPL_USE_ARCH_MEMSET
503 bool "Use an assembly optimized implementation of memset for TPL"
504 default y if USE_ARCH_MEMSET
505 depends on !ARM64 && TPL
507 Enable the generation of an optimized version of memset.
508 Such an implementation may be faster under some conditions
509 but may increase the binary size.
511 config ARM64_SUPPORT_AARCH32
512 bool "ARM64 system support AArch32 execution state"
514 default y if !TARGET_THUNDERX_88XX
516 This ARM64 system supports AArch32 execution state.
519 prompt "Target select"
524 select GPIO_EXTRA_HEADER
525 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
526 select SPL_SEPARATE_BSS if SPL
528 config TARGET_ASPENITE
529 bool "Support aspenite"
531 select GPIO_EXTRA_HEADER
536 select GPIO_EXTRA_HEADER
537 select SPL_DM_SPI if SPL
540 Support for TI's DaVinci platform.
543 bool "Marvell Kirkwood"
544 select ARCH_MISC_INIT
545 select BOARD_EARLY_INIT_F
547 select GPIO_EXTRA_HEADER
550 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
556 select GPIO_EXTRA_HEADER
557 select SPL_DM_SPI if SPL
558 select SPL_DM_SPI_FLASH if SPL
567 select GPIO_EXTRA_HEADER
569 config TARGET_SPEAR600
570 bool "Support spear600"
571 select BOARD_EARLY_INIT_F
573 select GPIO_EXTRA_HEADER
577 config TARGET_STV0991
578 bool "Support stv0991"
584 select GPIO_EXTRA_HEADER
592 select BOARD_LATE_INIT
594 select GPIO_EXTRA_HEADER
601 select GPIO_EXTRA_HEADER
604 bool "Broadcom BCM283X family"
608 select GPIO_EXTRA_HEADER
611 select SERIAL_SEARCH_ALL
616 bool "Broadcom BCM63158 family"
622 bool "Broadcom BCM68360 family"
628 bool "Broadcom BCM6858 family"
634 bool "Broadcom BCM7XXX family"
637 select GPIO_EXTRA_HEADER
639 select OF_PRIOR_STAGE
642 This enables support for Broadcom ARM-based set-top box
643 chipsets, including the 7445 family of chips.
645 config TARGET_BCMCYGNUS
646 bool "Support bcmcygnus"
648 select GPIO_EXTRA_HEADER
650 imply BCM_SF2_ETH_GMAC
658 bool "Support Broadcom Northstar2"
660 select GPIO_EXTRA_HEADER
662 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
663 ARMv8 Cortex-A57 processors targeting a broad range of networking
667 bool "Support Broadcom NS3"
669 select BOARD_LATE_INIT
671 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
672 ARMv8 Cortex-A72 processors targeting a broad range of networking
676 bool "Samsung EXYNOS"
685 select GPIO_EXTRA_HEADER
686 imply SYS_THUMB_BUILD
691 bool "Samsung S5PC1XX"
697 select GPIO_EXTRA_HEADER
701 bool "Calxeda Highbank"
714 config ARCH_INTEGRATOR
715 bool "ARM Ltd. Integrator family"
718 select GPIO_EXTRA_HEADER
723 bool "Qualcomm IPQ40xx SoCs"
729 select GPIO_EXTRA_HEADER
741 select GPIO_EXTRA_HEADER
743 select SYS_ARCH_TIMER
744 select SYS_THUMB_BUILD
750 bool "Texas Instruments' K3 Architecture"
755 config ARCH_OMAP2PLUS
758 select GPIO_EXTRA_HEADER
759 select SPL_BOARD_INIT if SPL
760 select SPL_STACK_R if SPL
762 imply TI_SYSC if DM && OF_CONTROL
767 select GPIO_EXTRA_HEADER
768 imply DISTRO_DEFAULTS
771 Support for the Meson SoC family developed by Amlogic Inc.,
772 targeted at media players and tablet computers. We currently
773 support the S905 (GXBaby) 64-bit SoC.
778 select GPIO_EXTRA_HEADER
781 select SPL_LIBCOMMON_SUPPORT if SPL
782 select SPL_LIBGENERIC_SUPPORT if SPL
783 select SPL_OF_CONTROL if SPL
786 Support for the MediaTek SoCs family developed by MediaTek Inc.
787 Please refer to doc/README.mediatek for more information.
790 bool "NXP LPC32xx platform"
795 select GPIO_EXTRA_HEADER
801 bool "NXP i.MX8 platform"
804 select GPIO_EXTRA_HEADER
806 select ENABLE_ARM_SOC_BOOT0_HOOK
809 bool "NXP i.MX8M platform"
811 select GPIO_EXTRA_HEADER
812 select SYS_FSL_HAS_SEC if IMX_HAB
813 select SYS_FSL_SEC_COMPAT_4
814 select SYS_FSL_SEC_LE
820 bool "NXP i.MXRT platform"
824 select GPIO_EXTRA_HEADER
829 bool "NXP i.MX23 family"
831 select GPIO_EXTRA_HEADER
838 select GPIO_EXTRA_HEADER
842 bool "NXP i.MX28 family"
844 select GPIO_EXTRA_HEADER
849 bool "NXP i.MX31 family"
851 select GPIO_EXTRA_HEADER
856 select GPIO_EXTRA_HEADER
857 select SYS_FSL_HAS_SEC if IMX_HAB
858 select SYS_FSL_SEC_COMPAT_4
859 select SYS_FSL_SEC_LE
860 select ROM_UNIFIED_SECTIONS
862 imply SYS_THUMB_BUILD
866 select ARCH_MISC_INIT
868 select GPIO_EXTRA_HEADER
869 select SYS_FSL_HAS_SEC if IMX_HAB
870 select SYS_FSL_SEC_COMPAT_4
871 select SYS_FSL_SEC_LE
872 imply BOARD_EARLY_INIT_F
874 imply SYS_THUMB_BUILD
879 select GPIO_EXTRA_HEADER
880 select SYS_FSL_HAS_SEC
881 select SYS_FSL_SEC_COMPAT_4
882 select SYS_FSL_SEC_LE
884 imply SYS_THUMB_BUILD
888 default "arch/arm/mach-omap2/u-boot-spl.lds"
893 select BOARD_EARLY_INIT_F
895 select GPIO_EXTRA_HEADER
899 bool "Nexell S5P4418/S5P6818 SoC"
900 select ENABLE_ARM_SOC_BOOT0_HOOK
902 select GPIO_EXTRA_HEADER
905 bool "Actions Semi OWL SoCs"
909 select GPIO_EXTRA_HEADER
914 select SYS_RELOC_GD_ENV_ADDR
918 bool "QEMU Virtual Platform"
929 bool "Renesas ARM SoCs"
932 select GPIO_EXTRA_HEADER
933 imply BOARD_EARLY_INIT_F
936 imply SYS_THUMB_BUILD
937 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
939 config ARCH_SNAPDRAGON
940 bool "Qualcomm Snapdragon SoCs"
945 select GPIO_EXTRA_HEADER
954 bool "Altera SOCFPGA family"
955 select ARCH_EARLY_INIT_R
956 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
957 select ARM64 if TARGET_SOCFPGA_SOC64
958 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
961 select GPIO_EXTRA_HEADER
962 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
964 select SPL_DM_RESET if DM_RESET
966 select SPL_LIBCOMMON_SUPPORT
967 select SPL_LIBGENERIC_SUPPORT
968 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
969 select SPL_OF_CONTROL
970 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
971 select SPL_SERIAL_SUPPORT
973 select SPL_WATCHDOG_SUPPORT
976 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
978 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
979 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
989 imply SPL_DM_SPI_FLASH
990 imply SPL_LIBDISK_SUPPORT
991 imply SPL_MMC_SUPPORT
992 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
993 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
994 imply SPL_SPI_FLASH_SUPPORT
995 imply SPL_SPI_SUPPORT
999 bool "Support sunxi (Allwinner) SoCs"
1002 select CMD_MMC if MMC
1003 select CMD_USB if DISTRO_DEFAULTS
1009 select DM_MMC if MMC
1010 select DM_SCSI if SCSI
1012 select DM_USB if DISTRO_DEFAULTS
1013 select GPIO_EXTRA_HEADER
1014 select OF_BOARD_SETUP
1017 select SPECIFY_CONSOLE_INDEX
1018 select SPL_STACK_R if SPL
1019 select SPL_SYS_MALLOC_SIMPLE if SPL
1020 select SPL_SYS_THUMB_BUILD if !ARM64
1023 select SYS_THUMB_BUILD if !ARM64
1024 select USB if DISTRO_DEFAULTS
1025 select USB_KEYBOARD if DISTRO_DEFAULTS
1026 select USB_STORAGE if DISTRO_DEFAULTS
1027 select SPL_USE_TINY_PRINTF
1029 select SYS_RELOC_GD_ENV_ADDR
1030 imply BOARD_LATE_INIT
1033 imply CMD_UBI if MTD_RAW_NAND
1034 imply DISTRO_DEFAULTS
1037 imply OF_LIBFDT_OVERLAY
1038 imply PRE_CONSOLE_BUFFER
1039 imply SPL_GPIO_SUPPORT
1040 imply SPL_LIBCOMMON_SUPPORT
1041 imply SPL_LIBGENERIC_SUPPORT
1042 imply SPL_MMC_SUPPORT if MMC
1043 imply SPL_POWER_SUPPORT
1044 imply SPL_SERIAL_SUPPORT
1048 bool "ST-Ericsson U8500 Series"
1052 select DM_MMC if MMC
1054 select DM_USB if USB
1058 imply ARM_PL180_MMCI
1060 imply NOMADIK_MTU_TIMER
1063 imply SYSRESET_SYSCON
1066 bool "Support Xilinx Versal Platform"
1070 select DM_ETH if NET
1071 select DM_MMC if MMC
1073 select GPIO_EXTRA_HEADER
1075 imply BOARD_LATE_INIT
1076 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1079 bool "Freescale Vybrid"
1081 select GPIO_EXTRA_HEADER
1082 select SYS_FSL_ERRATUM_ESDHC111
1087 bool "Xilinx Zynq based platform"
1092 select DM_ETH if NET
1093 select DM_MMC if MMC
1097 select DM_USB if USB
1098 select GPIO_EXTRA_HEADER
1101 select SPL_BOARD_INIT if SPL
1102 select SPL_CLK if SPL
1103 select SPL_DM if SPL
1104 select SPL_DM_SPI if SPL
1105 select SPL_DM_SPI_FLASH if SPL
1106 select SPL_OF_CONTROL if SPL
1107 select SPL_SEPARATE_BSS if SPL
1109 imply ARCH_EARLY_INIT_R
1110 imply BOARD_LATE_INIT
1114 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1117 config ARCH_ZYNQMP_R5
1118 bool "Xilinx ZynqMP R5 based platform"
1122 select DM_ETH if NET
1123 select DM_MMC if MMC
1125 select GPIO_EXTRA_HEADER
1131 bool "Xilinx ZynqMP based platform"
1135 select DM_ETH if NET
1137 select DM_MMC if MMC
1139 select DM_SPI if SPI
1140 select DM_SPI_FLASH if DM_SPI
1141 select DM_USB if USB
1143 select GPIO_EXTRA_HEADER
1145 select SPL_BOARD_INIT if SPL
1146 select SPL_CLK if SPL
1147 select SPL_DM if SPL
1148 select SPL_DM_SPI if SPI && SPL_DM
1149 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1150 select SPL_DM_MAILBOX if SPL
1151 select SPL_FIRMWARE if SPL
1152 select SPL_SEPARATE_BSS if SPL
1155 imply BOARD_LATE_INIT
1157 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1164 select GPIO_EXTRA_HEADER
1165 imply DISTRO_DEFAULTS
1168 config TARGET_VEXPRESS64_AEMV8A
1169 bool "Support vexpress_aemv8a"
1171 select GPIO_EXTRA_HEADER
1174 config TARGET_VEXPRESS64_BASE_FVP
1175 bool "Support Versatile Express ARMv8a FVP BASE model"
1177 select GPIO_EXTRA_HEADER
1181 config TARGET_VEXPRESS64_JUNO
1182 bool "Support Versatile Express Juno Development Platform"
1184 select GPIO_EXTRA_HEADER
1198 config TARGET_TOTAL_COMPUTE
1199 bool "Support Total Compute Platform"
1207 config TARGET_LS2080A_EMU
1208 bool "Support ls2080a_emu"
1211 select ARMV8_MULTIENTRY
1212 select FSL_DDR_SYNC_REFRESH
1213 select GPIO_EXTRA_HEADER
1215 Support for Freescale LS2080A_EMU platform.
1216 The LS2080A Development System (EMULATOR) is a pre-silicon
1217 development platform that supports the QorIQ LS2080A
1218 Layerscape Architecture processor.
1220 config TARGET_LS1088AQDS
1221 bool "Support ls1088aqds"
1224 select ARMV8_MULTIENTRY
1225 select ARCH_SUPPORT_TFABOOT
1226 select BOARD_LATE_INIT
1227 select GPIO_EXTRA_HEADER
1229 select FSL_DDR_INTERACTIVE if !SD_BOOT
1231 Support for NXP LS1088AQDS platform.
1232 The LS1088A Development System (QDS) is a high-performance
1233 development platform that supports the QorIQ LS1088A
1234 Layerscape Architecture processor.
1236 config TARGET_LS2080AQDS
1237 bool "Support ls2080aqds"
1240 select ARMV8_MULTIENTRY
1241 select ARCH_SUPPORT_TFABOOT
1242 select BOARD_LATE_INIT
1243 select GPIO_EXTRA_HEADER
1248 select FSL_DDR_INTERACTIVE if !SPL
1250 Support for Freescale LS2080AQDS platform.
1251 The LS2080A Development System (QDS) is a high-performance
1252 development platform that supports the QorIQ LS2080A
1253 Layerscape Architecture processor.
1255 config TARGET_LS2080ARDB
1256 bool "Support ls2080ardb"
1259 select ARMV8_MULTIENTRY
1260 select ARCH_SUPPORT_TFABOOT
1261 select BOARD_LATE_INIT
1264 select FSL_DDR_INTERACTIVE if !SPL
1265 select GPIO_EXTRA_HEADER
1269 Support for Freescale LS2080ARDB platform.
1270 The LS2080A Reference design board (RDB) is a high-performance
1271 development platform that supports the QorIQ LS2080A
1272 Layerscape Architecture processor.
1274 config TARGET_LS2081ARDB
1275 bool "Support ls2081ardb"
1278 select ARMV8_MULTIENTRY
1279 select BOARD_LATE_INIT
1280 select GPIO_EXTRA_HEADER
1283 Support for Freescale LS2081ARDB platform.
1284 The LS2081A Reference design board (RDB) is a high-performance
1285 development platform that supports the QorIQ LS2081A/LS2041A
1286 Layerscape Architecture processor.
1288 config TARGET_LX2160ARDB
1289 bool "Support lx2160ardb"
1292 select ARMV8_MULTIENTRY
1293 select ARCH_SUPPORT_TFABOOT
1294 select BOARD_LATE_INIT
1295 select GPIO_EXTRA_HEADER
1297 Support for NXP LX2160ARDB platform.
1298 The lx2160ardb (LX2160A Reference design board (RDB)
1299 is a high-performance development platform that supports the
1300 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1302 config TARGET_LX2160AQDS
1303 bool "Support lx2160aqds"
1306 select ARMV8_MULTIENTRY
1307 select ARCH_SUPPORT_TFABOOT
1308 select BOARD_LATE_INIT
1309 select GPIO_EXTRA_HEADER
1311 Support for NXP LX2160AQDS platform.
1312 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1313 is a high-performance development platform that supports the
1314 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1316 config TARGET_LX2162AQDS
1317 bool "Support lx2162aqds"
1319 select ARCH_MISC_INIT
1321 select ARMV8_MULTIENTRY
1322 select ARCH_SUPPORT_TFABOOT
1323 select BOARD_LATE_INIT
1324 select GPIO_EXTRA_HEADER
1326 Support for NXP LX2162AQDS platform.
1327 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1330 bool "Support HiKey 96boards Consumer Edition Platform"
1335 select GPIO_EXTRA_HEADER
1338 select SPECIFY_CONSOLE_INDEX
1341 Support for HiKey 96boards platform. It features a HI6220
1342 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1344 config TARGET_HIKEY960
1345 bool "Support HiKey960 96boards Consumer Edition Platform"
1349 select GPIO_EXTRA_HEADER
1354 Support for HiKey960 96boards platform. It features a HI3660
1355 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1357 config TARGET_POPLAR
1358 bool "Support Poplar 96boards Enterprise Edition Platform"
1363 select GPIO_EXTRA_HEADER
1368 Support for Poplar 96boards EE platform. It features a HI3798cv200
1369 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1370 making it capable of running any commercial set-top solution based on
1373 config TARGET_LS1012AQDS
1374 bool "Support ls1012aqds"
1377 select ARCH_SUPPORT_TFABOOT
1378 select BOARD_LATE_INIT
1379 select GPIO_EXTRA_HEADER
1381 Support for Freescale LS1012AQDS platform.
1382 The LS1012A Development System (QDS) is a high-performance
1383 development platform that supports the QorIQ LS1012A
1384 Layerscape Architecture processor.
1386 config TARGET_LS1012ARDB
1387 bool "Support ls1012ardb"
1390 select ARCH_SUPPORT_TFABOOT
1391 select BOARD_LATE_INIT
1392 select GPIO_EXTRA_HEADER
1396 Support for Freescale LS1012ARDB platform.
1397 The LS1012A Reference design board (RDB) is a high-performance
1398 development platform that supports the QorIQ LS1012A
1399 Layerscape Architecture processor.
1401 config TARGET_LS1012A2G5RDB
1402 bool "Support ls1012a2g5rdb"
1405 select ARCH_SUPPORT_TFABOOT
1406 select BOARD_LATE_INIT
1407 select GPIO_EXTRA_HEADER
1410 Support for Freescale LS1012A2G5RDB platform.
1411 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1412 development platform that supports the QorIQ LS1012A
1413 Layerscape Architecture processor.
1415 config TARGET_LS1012AFRWY
1416 bool "Support ls1012afrwy"
1419 select ARCH_SUPPORT_TFABOOT
1420 select BOARD_LATE_INIT
1421 select GPIO_EXTRA_HEADER
1425 Support for Freescale LS1012AFRWY platform.
1426 The LS1012A FRWY board (FRWY) is a high-performance
1427 development platform that supports the QorIQ LS1012A
1428 Layerscape Architecture processor.
1430 config TARGET_LS1012AFRDM
1431 bool "Support ls1012afrdm"
1434 select ARCH_SUPPORT_TFABOOT
1435 select GPIO_EXTRA_HEADER
1437 Support for Freescale LS1012AFRDM platform.
1438 The LS1012A Freedom board (FRDM) is a high-performance
1439 development platform that supports the QorIQ LS1012A
1440 Layerscape Architecture processor.
1442 config TARGET_LS1028AQDS
1443 bool "Support ls1028aqds"
1446 select ARMV8_MULTIENTRY
1447 select ARCH_SUPPORT_TFABOOT
1448 select BOARD_LATE_INIT
1449 select GPIO_EXTRA_HEADER
1451 Support for Freescale LS1028AQDS platform
1452 The LS1028A Development System (QDS) is a high-performance
1453 development platform that supports the QorIQ LS1028A
1454 Layerscape Architecture processor.
1456 config TARGET_LS1028ARDB
1457 bool "Support ls1028ardb"
1460 select ARMV8_MULTIENTRY
1461 select ARCH_SUPPORT_TFABOOT
1462 select BOARD_LATE_INIT
1463 select GPIO_EXTRA_HEADER
1465 Support for Freescale LS1028ARDB platform
1466 The LS1028A Development System (RDB) is a high-performance
1467 development platform that supports the QorIQ LS1028A
1468 Layerscape Architecture processor.
1470 config TARGET_LS1088ARDB
1471 bool "Support ls1088ardb"
1474 select ARMV8_MULTIENTRY
1475 select ARCH_SUPPORT_TFABOOT
1476 select BOARD_LATE_INIT
1478 select FSL_DDR_INTERACTIVE if !SD_BOOT
1479 select GPIO_EXTRA_HEADER
1481 Support for NXP LS1088ARDB platform.
1482 The LS1088A Reference design board (RDB) is a high-performance
1483 development platform that supports the QorIQ LS1088A
1484 Layerscape Architecture processor.
1486 config TARGET_LS1021AQDS
1487 bool "Support ls1021aqds"
1489 select ARCH_SUPPORT_PSCI
1490 select BOARD_EARLY_INIT_F
1491 select BOARD_LATE_INIT
1493 select CPU_V7_HAS_NONSEC
1494 select CPU_V7_HAS_VIRT
1495 select LS1_DEEP_SLEEP
1498 select FSL_DDR_INTERACTIVE
1499 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1500 select GPIO_EXTRA_HEADER
1501 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1504 config TARGET_LS1021ATWR
1505 bool "Support ls1021atwr"
1507 select ARCH_SUPPORT_PSCI
1508 select BOARD_EARLY_INIT_F
1509 select BOARD_LATE_INIT
1511 select CPU_V7_HAS_NONSEC
1512 select CPU_V7_HAS_VIRT
1513 select LS1_DEEP_SLEEP
1515 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1516 select GPIO_EXTRA_HEADER
1519 config TARGET_PG_WCOM_SELI8
1520 bool "Support Hitachi-Powergrids SELI8 service unit card"
1522 select ARCH_SUPPORT_PSCI
1523 select BOARD_EARLY_INIT_F
1524 select BOARD_LATE_INIT
1526 select CPU_V7_HAS_NONSEC
1527 select CPU_V7_HAS_VIRT
1529 select FSL_DDR_INTERACTIVE
1530 select GPIO_EXTRA_HEADER
1534 Support for Hitachi-Powergrids SELI8 service unit card.
1535 SELI8 is a QorIQ LS1021a based service unit card used
1536 in XMC20 and FOX615 product families.
1538 config TARGET_PG_WCOM_EXPU1
1539 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1541 select ARCH_SUPPORT_PSCI
1542 select BOARD_EARLY_INIT_F
1543 select BOARD_LATE_INIT
1545 select CPU_V7_HAS_NONSEC
1546 select CPU_V7_HAS_VIRT
1548 select FSL_DDR_INTERACTIVE
1552 Support for Hitachi-Powergrids EXPU1 service unit card.
1553 EXPU1 is a QorIQ LS1021a based service unit card used
1554 in XMC20 and FOX615 product families.
1556 config TARGET_LS1021ATSN
1557 bool "Support ls1021atsn"
1559 select ARCH_SUPPORT_PSCI
1560 select BOARD_EARLY_INIT_F
1561 select BOARD_LATE_INIT
1563 select CPU_V7_HAS_NONSEC
1564 select CPU_V7_HAS_VIRT
1565 select LS1_DEEP_SLEEP
1567 select GPIO_EXTRA_HEADER
1570 config TARGET_LS1021AIOT
1571 bool "Support ls1021aiot"
1573 select ARCH_SUPPORT_PSCI
1574 select BOARD_LATE_INIT
1576 select CPU_V7_HAS_NONSEC
1577 select CPU_V7_HAS_VIRT
1579 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1580 select GPIO_EXTRA_HEADER
1583 Support for Freescale LS1021AIOT platform.
1584 The LS1021A Freescale board (IOT) is a high-performance
1585 development platform that supports the QorIQ LS1021A
1586 Layerscape Architecture processor.
1588 config TARGET_LS1043AQDS
1589 bool "Support ls1043aqds"
1592 select ARMV8_MULTIENTRY
1593 select ARCH_SUPPORT_TFABOOT
1594 select BOARD_EARLY_INIT_F
1595 select BOARD_LATE_INIT
1597 select FSL_DDR_INTERACTIVE if !SPL
1598 select FSL_DSPI if !SPL_NO_DSPI
1599 select DM_SPI_FLASH if FSL_DSPI
1600 select GPIO_EXTRA_HEADER
1604 Support for Freescale LS1043AQDS platform.
1606 config TARGET_LS1043ARDB
1607 bool "Support ls1043ardb"
1610 select ARMV8_MULTIENTRY
1611 select ARCH_SUPPORT_TFABOOT
1612 select BOARD_EARLY_INIT_F
1613 select BOARD_LATE_INIT
1615 select FSL_DSPI if !SPL_NO_DSPI
1616 select DM_SPI_FLASH if FSL_DSPI
1617 select GPIO_EXTRA_HEADER
1619 Support for Freescale LS1043ARDB platform.
1621 config TARGET_LS1046AQDS
1622 bool "Support ls1046aqds"
1625 select ARMV8_MULTIENTRY
1626 select ARCH_SUPPORT_TFABOOT
1627 select BOARD_EARLY_INIT_F
1628 select BOARD_LATE_INIT
1629 select DM_SPI_FLASH if DM_SPI
1631 select FSL_DDR_BIST if !SPL
1632 select FSL_DDR_INTERACTIVE if !SPL
1633 select FSL_DDR_INTERACTIVE if !SPL
1634 select GPIO_EXTRA_HEADER
1637 Support for Freescale LS1046AQDS platform.
1638 The LS1046A Development System (QDS) is a high-performance
1639 development platform that supports the QorIQ LS1046A
1640 Layerscape Architecture processor.
1642 config TARGET_LS1046ARDB
1643 bool "Support ls1046ardb"
1646 select ARMV8_MULTIENTRY
1647 select ARCH_SUPPORT_TFABOOT
1648 select BOARD_EARLY_INIT_F
1649 select BOARD_LATE_INIT
1650 select DM_SPI_FLASH if DM_SPI
1651 select POWER_MC34VR500
1654 select FSL_DDR_INTERACTIVE if !SPL
1655 select GPIO_EXTRA_HEADER
1658 Support for Freescale LS1046ARDB platform.
1659 The LS1046A Reference Design Board (RDB) is a high-performance
1660 development platform that supports the QorIQ LS1046A
1661 Layerscape Architecture processor.
1663 config TARGET_LS1046AFRWY
1664 bool "Support ls1046afrwy"
1667 select ARMV8_MULTIENTRY
1668 select ARCH_SUPPORT_TFABOOT
1669 select BOARD_EARLY_INIT_F
1670 select BOARD_LATE_INIT
1671 select DM_SPI_FLASH if DM_SPI
1672 select GPIO_EXTRA_HEADER
1675 Support for Freescale LS1046AFRWY platform.
1676 The LS1046A Freeway Board (FRWY) is a high-performance
1677 development platform that supports the QorIQ LS1046A
1678 Layerscape Architecture processor.
1684 select ARMV8_MULTIENTRY
1701 select GPIO_EXTRA_HEADER
1702 select SPL_DM if SPL
1703 select SPL_DM_SPI if SPL
1704 select SPL_DM_SPI_FLASH if SPL
1705 select SPL_DM_I2C if SPL
1706 select SPL_DM_MMC if SPL
1707 select SPL_DM_SERIAL if SPL
1709 Support for Kontron SMARC-sAL28 board.
1711 config TARGET_COLIBRI_PXA270
1712 bool "Support colibri_pxa270"
1714 select GPIO_EXTRA_HEADER
1716 config ARCH_UNIPHIER
1717 bool "Socionext UniPhier SoCs"
1718 select BOARD_LATE_INIT
1728 select OF_BOARD_SETUP
1732 select SPL_BOARD_INIT if SPL
1733 select SPL_DM if SPL
1734 select SPL_LIBCOMMON_SUPPORT if SPL
1735 select SPL_LIBGENERIC_SUPPORT if SPL
1736 select SPL_OF_CONTROL if SPL
1737 select SPL_PINCTRL if SPL
1740 imply DISTRO_DEFAULTS
1743 Support for UniPhier SoC family developed by Socionext Inc.
1744 (formerly, System LSI Business Division of Panasonic Corporation)
1746 config ARCH_SYNQUACER
1747 bool "Socionext SynQuacer SoCs"
1753 select SYSRESET_PSCI
1756 Support for SynQuacer SoC family developed by Socionext Inc.
1757 This SoC is used on 96boards EE DeveloperBox.
1760 bool "Support STMicroelectronics STM32 MCU with cortex M"
1764 select GPIO_EXTRA_HEADER
1768 bool "Support STMicrolectronics SoCs"
1777 Support for STMicroelectronics STiH407/10 SoC family.
1778 This SoC is used on Linaro 96Board STiH410-B2260
1781 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1782 select ARCH_MISC_INIT
1783 select ARCH_SUPPORT_TFABOOT
1784 select BOARD_LATE_INIT
1790 select GPIO_EXTRA_HEADER
1794 select OF_SYSTEM_SETUP
1800 select SYS_THUMB_BUILD
1804 imply OF_LIBFDT_OVERLAY
1805 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1808 Support for STM32MP SoC family developed by STMicroelectronics,
1809 MPUs based on ARM cortex A core
1810 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1811 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1813 SPL is the unsecure FSBL for the basic boot chain.
1815 config ARCH_ROCKCHIP
1816 bool "Support Rockchip SoCs"
1818 select BINMAN if SPL_OPTEE
1828 select DM_USB if USB
1829 select ENABLE_ARM_SOC_BOOT0_HOOK
1832 select SPL_DM if SPL
1833 select SPL_DM_SPI if SPL
1834 select SPL_DM_SPI_FLASH if SPL
1836 select SYS_THUMB_BUILD if !ARM64
1839 imply DEBUG_UART_BOARD_INIT
1840 imply DISTRO_DEFAULTS
1842 imply SARADC_ROCKCHIP
1844 imply SPL_SYS_MALLOC_SIMPLE
1847 imply USB_FUNCTION_FASTBOOT
1849 config ARCH_OCTEONTX
1850 bool "Support OcteonTX SoCs"
1853 select GPIO_EXTRA_HEADER
1857 select BOARD_LATE_INIT
1858 select SYS_CACHE_SHIFT_7
1860 config ARCH_OCTEONTX2
1861 bool "Support OcteonTX2 SoCs"
1864 select GPIO_EXTRA_HEADER
1868 select BOARD_LATE_INIT
1869 select SYS_CACHE_SHIFT_7
1871 config TARGET_THUNDERX_88XX
1872 bool "Support ThunderX 88xx"
1874 select GPIO_EXTRA_HEADER
1877 select SYS_CACHE_SHIFT_7
1880 bool "Support Aspeed SoCs"
1885 config TARGET_DURIAN
1886 bool "Support Phytium Durian Platform"
1888 select GPIO_EXTRA_HEADER
1890 Support for durian platform.
1891 It has 2GB Sdram, uart and pcie.
1893 config TARGET_PRESIDIO_ASIC
1894 bool "Support Cortina Presidio ASIC Platform"
1897 config TARGET_XENGUEST_ARM64
1898 bool "Xen guest ARM64"
1902 select LINUX_KERNEL_IMAGE_HEADER
1907 config ARCH_SUPPORT_TFABOOT
1911 bool "Support for booting from TF-A"
1912 depends on ARCH_SUPPORT_TFABOOT
1915 Some platforms support the setup of secure registers (for instance
1916 for CPU errata handling) or provide secure services like PSCI.
1917 Those services could also be provided by other firmware parts
1918 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
1919 does not need to (and cannot) execute this code.
1920 Enabling this option will make a U-Boot binary that is relying
1921 on other firmware layers to provide secure functionality.
1923 config TI_SECURE_DEVICE
1924 bool "HS Device Type Support"
1925 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1927 If a high secure (HS) device type is being used, this config
1928 must be set. This option impacts various aspects of the
1929 build system (to create signed boot images that can be
1930 authenticated) and the code. See the doc/README.ti-secure
1931 file for further details.
1933 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1934 config ISW_ENTRY_ADDR
1935 hex "Address in memory or XIP address of bootloader entry point"
1936 default 0x402F4000 if AM43XX
1937 default 0x402F0400 if AM33XX
1938 default 0x40301350 if OMAP54XX
1940 After any reset, the boot ROM searches the boot media for a valid
1941 boot image. For non-XIP devices, the ROM then copies the image into
1942 internal memory. For all boot modes, after the ROM processes the
1943 boot image it eventually computes the entry point address depending
1944 on the device type (secure/non-secure), boot media (xip/non-xip) and
1948 source "arch/arm/mach-aspeed/Kconfig"
1950 source "arch/arm/mach-at91/Kconfig"
1952 source "arch/arm/mach-bcm283x/Kconfig"
1954 source "arch/arm/mach-bcmstb/Kconfig"
1956 source "arch/arm/mach-davinci/Kconfig"
1958 source "arch/arm/mach-exynos/Kconfig"
1960 source "arch/arm/mach-highbank/Kconfig"
1962 source "arch/arm/mach-integrator/Kconfig"
1964 source "arch/arm/mach-ipq40xx/Kconfig"
1966 source "arch/arm/mach-k3/Kconfig"
1968 source "arch/arm/mach-keystone/Kconfig"
1970 source "arch/arm/mach-kirkwood/Kconfig"
1972 source "arch/arm/mach-lpc32xx/Kconfig"
1974 source "arch/arm/mach-mvebu/Kconfig"
1976 source "arch/arm/mach-octeontx/Kconfig"
1978 source "arch/arm/mach-octeontx2/Kconfig"
1980 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1982 source "arch/arm/mach-imx/mx2/Kconfig"
1984 source "arch/arm/mach-imx/mx3/Kconfig"
1986 source "arch/arm/mach-imx/mx5/Kconfig"
1988 source "arch/arm/mach-imx/mx6/Kconfig"
1990 source "arch/arm/mach-imx/mx7/Kconfig"
1992 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1994 source "arch/arm/mach-imx/imx8/Kconfig"
1996 source "arch/arm/mach-imx/imx8m/Kconfig"
1998 source "arch/arm/mach-imx/imxrt/Kconfig"
2000 source "arch/arm/mach-imx/mxs/Kconfig"
2002 source "arch/arm/mach-omap2/Kconfig"
2004 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2006 source "arch/arm/mach-orion5x/Kconfig"
2008 source "arch/arm/mach-owl/Kconfig"
2010 source "arch/arm/mach-rmobile/Kconfig"
2012 source "arch/arm/mach-meson/Kconfig"
2014 source "arch/arm/mach-mediatek/Kconfig"
2016 source "arch/arm/mach-qemu/Kconfig"
2018 source "arch/arm/mach-rockchip/Kconfig"
2020 source "arch/arm/mach-s5pc1xx/Kconfig"
2022 source "arch/arm/mach-snapdragon/Kconfig"
2024 source "arch/arm/mach-socfpga/Kconfig"
2026 source "arch/arm/mach-sti/Kconfig"
2028 source "arch/arm/mach-stm32/Kconfig"
2030 source "arch/arm/mach-stm32mp/Kconfig"
2032 source "arch/arm/mach-sunxi/Kconfig"
2034 source "arch/arm/mach-tegra/Kconfig"
2036 source "arch/arm/mach-u8500/Kconfig"
2038 source "arch/arm/mach-uniphier/Kconfig"
2040 source "arch/arm/cpu/armv7/vf610/Kconfig"
2042 source "arch/arm/mach-zynq/Kconfig"
2044 source "arch/arm/mach-zynqmp/Kconfig"
2046 source "arch/arm/mach-versal/Kconfig"
2048 source "arch/arm/mach-zynqmp-r5/Kconfig"
2050 source "arch/arm/cpu/armv7/Kconfig"
2052 source "arch/arm/cpu/armv8/Kconfig"
2054 source "arch/arm/mach-imx/Kconfig"
2056 source "arch/arm/mach-nexell/Kconfig"
2058 source "board/armltd/total_compute/Kconfig"
2060 source "board/bosch/shc/Kconfig"
2061 source "board/bosch/guardian/Kconfig"
2062 source "board/CarMediaLab/flea3/Kconfig"
2063 source "board/Marvell/aspenite/Kconfig"
2064 source "board/Marvell/octeontx/Kconfig"
2065 source "board/Marvell/octeontx2/Kconfig"
2066 source "board/armltd/vexpress64/Kconfig"
2067 source "board/cortina/presidio-asic/Kconfig"
2068 source "board/broadcom/bcm963158/Kconfig"
2069 source "board/broadcom/bcm968360bg/Kconfig"
2070 source "board/broadcom/bcm968580xref/Kconfig"
2071 source "board/broadcom/bcmns3/Kconfig"
2072 source "board/cavium/thunderx/Kconfig"
2073 source "board/eets/pdu001/Kconfig"
2074 source "board/emulation/qemu-arm/Kconfig"
2075 source "board/freescale/ls2080aqds/Kconfig"
2076 source "board/freescale/ls2080ardb/Kconfig"
2077 source "board/freescale/ls1088a/Kconfig"
2078 source "board/freescale/ls1028a/Kconfig"
2079 source "board/freescale/ls1021aqds/Kconfig"
2080 source "board/freescale/ls1043aqds/Kconfig"
2081 source "board/freescale/ls1021atwr/Kconfig"
2082 source "board/freescale/ls1021atsn/Kconfig"
2083 source "board/freescale/ls1021aiot/Kconfig"
2084 source "board/freescale/ls1046aqds/Kconfig"
2085 source "board/freescale/ls1043ardb/Kconfig"
2086 source "board/freescale/ls1046ardb/Kconfig"
2087 source "board/freescale/ls1046afrwy/Kconfig"
2088 source "board/freescale/ls1012aqds/Kconfig"
2089 source "board/freescale/ls1012ardb/Kconfig"
2090 source "board/freescale/ls1012afrdm/Kconfig"
2091 source "board/freescale/lx2160a/Kconfig"
2092 source "board/grinn/chiliboard/Kconfig"
2093 source "board/hisilicon/hikey/Kconfig"
2094 source "board/hisilicon/hikey960/Kconfig"
2095 source "board/hisilicon/poplar/Kconfig"
2096 source "board/isee/igep003x/Kconfig"
2097 source "board/kontron/sl28/Kconfig"
2098 source "board/myir/mys_6ulx/Kconfig"
2099 source "board/seeed/npi_imx6ull/Kconfig"
2100 source "board/socionext/developerbox/Kconfig"
2101 source "board/spear/spear600/Kconfig"
2102 source "board/spear/x600/Kconfig"
2103 source "board/st/stv0991/Kconfig"
2104 source "board/tcl/sl50/Kconfig"
2105 source "board/toradex/colibri_pxa270/Kconfig"
2106 source "board/variscite/dart_6ul/Kconfig"
2107 source "board/vscom/baltos/Kconfig"
2108 source "board/phytium/durian/Kconfig"
2109 source "board/xen/xenguest_arm64/Kconfig"
2110 source "board/keymile/Kconfig"
2112 source "arch/arm/Kconfig.debug"
2117 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
2118 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
2119 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64