1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
17 be loaded to and run from that address. This option lifts that
18 restriction, thus allowing the code to be loaded to and executed from
19 almost any 4K aligned address. This logic relies on the relocation
20 information that is embedded in the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
23 config INIT_SP_RELATIVE
24 bool "Specify the early stack pointer relative to the .bss section"
25 default n if ARCH_QEMU
26 default y if POSITION_INDEPENDENT
28 U-Boot typically uses a hard-coded value for the stack pointer
29 before relocation. Enable this option to instead calculate the
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that it can be loaded and executed at arbitrary
32 addresses and thus avoid using arbitrary addresses at runtime.
34 If this option is enabled, the early stack pointer is set to
35 &_bss_start with a offset value added. The offset is specified by
36 SYS_INIT_SP_BSS_OFFSET.
38 config SYS_INIT_SP_BSS_OFFSET
39 int "Early stack offset from the .bss base address"
40 depends on INIT_SP_RELATIVE
43 This option's value is the offset added to &_bss_start in order to
44 calculate the stack pointer. This offset should be large enough so
45 that the early malloc region, global data (gd), and early stack usage
46 do not overlap any appended DTB.
48 config LINUX_KERNEL_IMAGE_HEADER
51 Place a Linux kernel image header at the start of the U-Boot binary.
52 The format of the header is described in the Linux kernel source at
53 Documentation/arm64/booting.txt. This feature is useful since the
54 image header reports the amount of memory (BSS and similar) that
55 U-Boot needs to use, but which isn't part of the binary.
57 if LINUX_KERNEL_IMAGE_HEADER
58 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
61 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
62 TEXT_OFFSET value written to the Linux kernel image header.
71 ARM GICV3 Interrupt translation service (ITS).
72 Basic support for programming locality specific peripheral
73 interrupts (LPI) configuration tables and enable LPI tables.
74 LPI configuration table can be used by u-boot or Linux.
75 ARM GICV3 has limitation, once the LPI table is enabled, LPI
76 configuration table can not be re-programmed, unless GICV3 reset.
82 config DMA_ADDR_T_64BIT
92 # Used for compatibility with asm files copied from the kernel
93 config ARM_ASM_UNIFIED
97 # Used for compatibility with asm files copied from the kernel
101 config SYS_ICACHE_OFF
102 bool "Do not enable icache"
105 Do not enable instruction cache in U-Boot.
107 config SPL_SYS_ICACHE_OFF
108 bool "Do not enable icache in SPL"
110 default SYS_ICACHE_OFF
112 Do not enable instruction cache in SPL.
114 config SYS_DCACHE_OFF
115 bool "Do not enable dcache"
118 Do not enable data cache in U-Boot.
120 config SPL_SYS_DCACHE_OFF
121 bool "Do not enable dcache in SPL"
123 default SYS_DCACHE_OFF
125 Do not enable data cache in SPL.
127 config SYS_ARM_CACHE_CP15
128 bool "CP15 based cache enabling support"
130 Select this if your processor suports enabling caches by using
134 bool "MMU-based Paged Memory Management Support"
135 select SYS_ARM_CACHE_CP15
137 Select if you want MMU-based virtualised addressing space
138 support via paged memory management.
141 bool 'Use the ARM v7 PMSA Compliant MPU'
143 Some ARM systems without an MMU have instead a Memory Protection
144 Unit (MPU) that defines the type and permissions for regions of
146 If your CPU has an MPU then you should choose 'y' here unless you
147 know that you do not want to use the MPU.
149 # If set, the workarounds for these ARM errata are applied early during U-Boot
150 # startup. Note that in general these options force the workarounds to be
151 # applied; no CPU-type/version detection exists, unlike the similar options in
152 # the Linux kernel. Do not set these options unless they apply! Also note that
153 # the following can be machine-specific errata. These do have ability to
154 # provide rudimentary version and machine-specific checks, but expect no
156 # CONFIG_ARM_ERRATA_430973
157 # CONFIG_ARM_ERRATA_454179
158 # CONFIG_ARM_ERRATA_621766
159 # CONFIG_ARM_ERRATA_798870
160 # CONFIG_ARM_ERRATA_801819
161 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
162 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
164 config ARM_ERRATA_430973
167 config ARM_ERRATA_454179
170 config ARM_ERRATA_621766
173 config ARM_ERRATA_716044
176 config ARM_ERRATA_725233
179 config ARM_ERRATA_742230
182 config ARM_ERRATA_743622
185 config ARM_ERRATA_751472
188 config ARM_ERRATA_761320
191 config ARM_ERRATA_773022
194 config ARM_ERRATA_774769
197 config ARM_ERRATA_794072
200 config ARM_ERRATA_798870
203 config ARM_ERRATA_801819
206 config ARM_ERRATA_826974
209 config ARM_ERRATA_828024
212 config ARM_ERRATA_829520
215 config ARM_ERRATA_833069
218 config ARM_ERRATA_833471
221 config ARM_ERRATA_845369
224 config ARM_ERRATA_852421
227 config ARM_ERRATA_852423
230 config ARM_ERRATA_855873
233 config ARM_CORTEX_A8_CVE_2017_5715
236 config ARM_CORTEX_A15_CVE_2017_5715
241 select SYS_CACHE_SHIFT_5
246 select SYS_CACHE_SHIFT_5
251 select SYS_CACHE_SHIFT_5
256 select SYS_CACHE_SHIFT_5
261 select SYS_CACHE_SHIFT_5
267 select SYS_CACHE_SHIFT_5
274 select SYS_CACHE_SHIFT_6
281 select SYS_CACHE_SHIFT_5
282 select SYS_THUMB_BUILD
288 select SYS_ARM_CACHE_CP15
290 select SYS_CACHE_SHIFT_6
294 select SYS_CACHE_SHIFT_5
299 select SYS_CACHE_SHIFT_5
303 default "arm720t" if CPU_ARM720T
304 default "arm920t" if CPU_ARM920T
305 default "arm926ejs" if CPU_ARM926EJS
306 default "arm946es" if CPU_ARM946ES
307 default "arm1136" if CPU_ARM1136
308 default "arm1176" if CPU_ARM1176
309 default "armv7" if CPU_V7A
310 default "armv7" if CPU_V7R
311 default "armv7m" if CPU_V7M
312 default "pxa" if CPU_PXA
313 default "sa1100" if CPU_SA1100
314 default "armv8" if ARM64
318 default 4 if CPU_ARM720T
319 default 4 if CPU_ARM920T
320 default 5 if CPU_ARM926EJS
321 default 5 if CPU_ARM946ES
322 default 6 if CPU_ARM1136
323 default 6 if CPU_ARM1176
328 default 4 if CPU_SA1100
331 config SYS_CACHE_SHIFT_5
334 config SYS_CACHE_SHIFT_6
337 config SYS_CACHE_SHIFT_7
340 config SYS_CACHELINE_SIZE
342 default 128 if SYS_CACHE_SHIFT_7
343 default 64 if SYS_CACHE_SHIFT_6
344 default 32 if SYS_CACHE_SHIFT_5
347 prompt "Select the ARM data write cache policy"
348 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
349 TARGET_BCMNSP || CPU_PXA || RZA1
350 default SYS_ARM_CACHE_WRITEBACK
352 config SYS_ARM_CACHE_WRITEBACK
353 bool "Write-back (WB)"
355 A write updates the cache only and marks the cache line as dirty.
356 External memory is updated only when the line is evicted or explicitly
359 config SYS_ARM_CACHE_WRITETHROUGH
360 bool "Write-through (WT)"
362 A write updates both the cache and the external memory system.
363 This does not mark the cache line as dirty.
365 config SYS_ARM_CACHE_WRITEALLOC
366 bool "Write allocation (WA)"
368 A cache line is allocated on a write miss. This means that executing a
369 store instruction on the processor might cause a burst read to occur.
370 There is a linefill to obtain the data for the cache line, before the
375 bool "Enable ARCH_CPU_INIT"
377 Some architectures require a call to arch_cpu_init().
378 Say Y here to enable it
380 config SYS_ARCH_TIMER
381 bool "ARM Generic Timer support"
382 depends on CPU_V7A || ARM64
385 The ARM Generic Timer (aka arch-timer) provides an architected
386 interface to a timer source on an SoC.
387 It is mandatory for ARMv8 implementation and widely available
391 bool "Support for ARM SMC Calling Convention (SMCCC)"
392 depends on CPU_V7A || ARM64
395 Say Y here if you want to enable ARM SMC Calling Convention.
396 This should be enabled if U-Boot needs to communicate with system
397 firmware (for example, PSCI) according to SMCCC.
400 bool "support boot from semihosting"
402 In emulated environments, semihosting is a way for
403 the hosted environment to call out to the emulator to
404 retrieve files from the host machine.
406 config SYS_THUMB_BUILD
407 bool "Build U-Boot using the Thumb instruction set"
410 Use this flag to build U-Boot using the Thumb instruction set for
411 ARM architectures. Thumb instruction set provides better code
412 density. For ARM architectures that support Thumb2 this flag will
413 result in Thumb2 code generated by GCC.
415 config SPL_SYS_THUMB_BUILD
416 bool "Build SPL using the Thumb instruction set"
417 default y if SYS_THUMB_BUILD
418 depends on !ARM64 && SPL
420 Use this flag to build SPL using the Thumb instruction set for
421 ARM architectures. Thumb instruction set provides better code
422 density. For ARM architectures that support Thumb2 this flag will
423 result in Thumb2 code generated by GCC.
425 config TPL_SYS_THUMB_BUILD
426 bool "Build TPL using the Thumb instruction set"
427 default y if SYS_THUMB_BUILD
428 depends on TPL && !ARM64
430 Use this flag to build TPL using the Thumb instruction set for
431 ARM architectures. Thumb instruction set provides better code
432 density. For ARM architectures that support Thumb2 this flag will
433 result in Thumb2 code generated by GCC.
436 config SYS_L2CACHE_OFF
439 If SoC does not support L2CACHE or one does not want to enable
440 L2CACHE, choose this option.
442 config ENABLE_ARM_SOC_BOOT0_HOOK
443 bool "prepare BOOT0 header"
445 If the SoC's BOOT0 requires a header area filled with (magic)
446 values, then choose this option, and create a file included as
447 <asm/arch/boot0.h> which contains the required assembler code.
449 config ARM_CORTEX_CPU_IS_UP
453 config USE_ARCH_MEMCPY
454 bool "Use an assembly optimized implementation of memcpy"
458 Enable the generation of an optimized version of memcpy.
459 Such an implementation may be faster under some conditions
460 but may increase the binary size.
462 config SPL_USE_ARCH_MEMCPY
463 bool "Use an assembly optimized implementation of memcpy for SPL"
464 default y if USE_ARCH_MEMCPY
465 depends on !ARM64 && SPL
467 Enable the generation of an optimized version of memcpy.
468 Such an implementation may be faster under some conditions
469 but may increase the binary size.
471 config TPL_USE_ARCH_MEMCPY
472 bool "Use an assembly optimized implementation of memcpy for TPL"
473 default y if USE_ARCH_MEMCPY
474 depends on !ARM64 && TPL
476 Enable the generation of an optimized version of memcpy.
477 Such an implementation may be faster under some conditions
478 but may increase the binary size.
480 config USE_ARCH_MEMSET
481 bool "Use an assembly optimized implementation of memset"
485 Enable the generation of an optimized version of memset.
486 Such an implementation may be faster under some conditions
487 but may increase the binary size.
489 config SPL_USE_ARCH_MEMSET
490 bool "Use an assembly optimized implementation of memset for SPL"
491 default y if USE_ARCH_MEMSET
492 depends on !ARM64 && SPL
494 Enable the generation of an optimized version of memset.
495 Such an implementation may be faster under some conditions
496 but may increase the binary size.
498 config TPL_USE_ARCH_MEMSET
499 bool "Use an assembly optimized implementation of memset for TPL"
500 default y if USE_ARCH_MEMSET
501 depends on !ARM64 && TPL
503 Enable the generation of an optimized version of memset.
504 Such an implementation may be faster under some conditions
505 but may increase the binary size.
507 config ARM64_SUPPORT_AARCH32
508 bool "ARM64 system support AArch32 execution state"
510 default y if !TARGET_THUNDERX_88XX
512 This ARM64 system supports AArch32 execution state.
515 prompt "Target select"
520 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
521 select SPL_SEPARATE_BSS if SPL
523 config TARGET_EDB93XX
524 bool "Support edb93xx"
528 config TARGET_ASPENITE
529 bool "Support aspenite"
533 bool "Support gplugd"
539 select SPL_DM_SPI if SPL
542 Support for TI's DaVinci platform.
545 bool "Marvell Kirkwood"
546 select ARCH_MISC_INIT
547 select BOARD_EARLY_INIT_F
551 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
557 select SPL_DM_SPI if SPL
558 select SPL_DM_SPI_FLASH if SPL
568 config TARGET_SPEAR300
569 bool "Support spear300"
570 select BOARD_EARLY_INIT_F
575 config TARGET_SPEAR310
576 bool "Support spear310"
577 select BOARD_EARLY_INIT_F
582 config TARGET_SPEAR320
583 bool "Support spear320"
584 select BOARD_EARLY_INIT_F
589 config TARGET_SPEAR600
590 bool "Support spear600"
591 select BOARD_EARLY_INIT_F
596 config TARGET_STV0991
597 bool "Support stv0991"
610 select BOARD_LATE_INIT
620 bool "Broadcom BCM283X family"
626 select SERIAL_SEARCH_ALL
631 bool "Broadcom BCM63158 family"
637 bool "Broadcom BCM68360 family"
643 bool "Broadcom BCM6858 family"
649 bool "Broadcom BCM7XXX family"
653 select OF_PRIOR_STAGE
656 This enables support for Broadcom ARM-based set-top box
657 chipsets, including the 7445 family of chips.
659 config TARGET_BCMCYGNUS
660 bool "Support bcmcygnus"
663 imply BCM_SF2_ETH_GMAC
671 bool "Support bcmnsp"
675 bool "Support Broadcom Northstar2"
678 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
679 ARMv8 Cortex-A57 processors targeting a broad range of networking
683 bool "Support Broadcom NS3"
685 select BOARD_LATE_INIT
687 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
688 ARMv8 Cortex-A72 processors targeting a broad range of networking
692 bool "Samsung EXYNOS"
701 imply SYS_THUMB_BUILD
706 bool "Samsung S5PC1XX"
715 bool "Calxeda Highbank"
719 config ARCH_INTEGRATOR
720 bool "ARM Ltd. Integrator family"
727 bool "Qualcomm IPQ40xx SoCs"
745 select SYS_ARCH_TIMER
746 select SYS_THUMB_BUILD
752 bool "Texas Instruments' K3 Architecture"
757 config ARCH_OMAP2PLUS
760 select SPL_BOARD_INIT if SPL
761 select SPL_STACK_R if SPL
763 imply TI_SYSC if DM && OF_CONTROL
768 imply DISTRO_DEFAULTS
771 Support for the Meson SoC family developed by Amlogic Inc.,
772 targeted at media players and tablet computers. We currently
773 support the S905 (GXBaby) 64-bit SoC.
780 select SPL_LIBCOMMON_SUPPORT if SPL
781 select SPL_LIBGENERIC_SUPPORT if SPL
782 select SPL_OF_CONTROL if SPL
785 Support for the MediaTek SoCs family developed by MediaTek Inc.
786 Please refer to doc/README.mediatek for more information.
789 bool "NXP LPC32xx platform"
799 bool "NXP i.MX8 platform"
803 select ENABLE_ARM_SOC_BOOT0_HOOK
806 bool "NXP i.MX8M platform"
808 select SYS_FSL_HAS_SEC if IMX_HAB
809 select SYS_FSL_SEC_COMPAT_4
810 select SYS_FSL_SEC_LE
816 bool "NXP i.MXRT platform"
824 bool "NXP i.MX23 family"
835 bool "NXP i.MX28 family"
841 bool "NXP i.MX31 family"
847 select SYS_FSL_HAS_SEC if IMX_HAB
848 select SYS_FSL_SEC_COMPAT_4
849 select SYS_FSL_SEC_LE
850 select ROM_UNIFIED_SECTIONS
852 imply SYS_THUMB_BUILD
856 select ARCH_MISC_INIT
858 select SYS_FSL_HAS_SEC if IMX_HAB
859 select SYS_FSL_SEC_COMPAT_4
860 select SYS_FSL_SEC_LE
861 imply BOARD_EARLY_INIT_F
863 imply SYS_THUMB_BUILD
868 select SYS_FSL_HAS_SEC
869 select SYS_FSL_SEC_COMPAT_4
870 select SYS_FSL_SEC_LE
872 imply SYS_THUMB_BUILD
876 default "arch/arm/mach-omap2/u-boot-spl.lds"
881 select BOARD_EARLY_INIT_F
886 bool "Nexell S5P4418/S5P6818 SoC"
887 select ENABLE_ARM_SOC_BOOT0_HOOK
891 bool "Actions Semi OWL SoCs"
899 select SYS_RELOC_GD_ENV_ADDR
903 bool "QEMU Virtual Platform"
914 bool "Renesas ARM SoCs"
917 imply BOARD_EARLY_INIT_F
920 imply SYS_THUMB_BUILD
921 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
923 config ARCH_SNAPDRAGON
924 bool "Qualcomm Snapdragon SoCs"
937 bool "Altera SOCFPGA family"
938 select ARCH_EARLY_INIT_R
939 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
940 select ARM64 if TARGET_SOCFPGA_SOC64
941 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
944 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
946 select SPL_DM_RESET if DM_RESET
948 select SPL_LIBCOMMON_SUPPORT
949 select SPL_LIBGENERIC_SUPPORT
950 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
951 select SPL_OF_CONTROL
952 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
953 select SPL_SERIAL_SUPPORT
955 select SPL_WATCHDOG_SUPPORT
958 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
960 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
961 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
971 imply SPL_DM_SPI_FLASH
972 imply SPL_LIBDISK_SUPPORT
973 imply SPL_MMC_SUPPORT
974 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
975 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
976 imply SPL_SPI_FLASH_SUPPORT
977 imply SPL_SPI_SUPPORT
981 bool "Support sunxi (Allwinner) SoCs"
984 select CMD_MMC if MMC
985 select CMD_USB if DISTRO_DEFAULTS
992 select DM_SCSI if SCSI
994 select DM_USB if DISTRO_DEFAULTS
995 select OF_BOARD_SETUP
998 select SPECIFY_CONSOLE_INDEX
999 select SPL_STACK_R if SPL
1000 select SPL_SYS_MALLOC_SIMPLE if SPL
1001 select SPL_SYS_THUMB_BUILD if !ARM64
1004 select SYS_THUMB_BUILD if !ARM64
1005 select USB if DISTRO_DEFAULTS
1006 select USB_KEYBOARD if DISTRO_DEFAULTS
1007 select USB_STORAGE if DISTRO_DEFAULTS
1008 select SPL_USE_TINY_PRINTF
1010 select SYS_RELOC_GD_ENV_ADDR
1011 imply BOARD_LATE_INIT
1014 imply CMD_UBI if MTD_RAW_NAND
1015 imply DISTRO_DEFAULTS
1018 imply OF_LIBFDT_OVERLAY
1019 imply PRE_CONSOLE_BUFFER
1020 imply SPL_GPIO_SUPPORT
1021 imply SPL_LIBCOMMON_SUPPORT
1022 imply SPL_LIBGENERIC_SUPPORT
1023 imply SPL_MMC_SUPPORT if MMC
1024 imply SPL_POWER_SUPPORT
1025 imply SPL_SERIAL_SUPPORT
1029 bool "ST-Ericsson U8500 Series"
1033 select DM_MMC if MMC
1035 select DM_USB if USB
1039 imply ARM_PL180_MMCI
1041 imply NOMADIK_MTU_TIMER
1044 imply SYSRESET_SYSCON
1047 bool "Support Xilinx Versal Platform"
1051 select DM_ETH if NET
1052 select DM_MMC if MMC
1055 imply BOARD_LATE_INIT
1056 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1059 bool "Freescale Vybrid"
1061 select SYS_FSL_ERRATUM_ESDHC111
1066 bool "Xilinx Zynq based platform"
1071 select DM_ETH if NET
1072 select DM_MMC if MMC
1076 select DM_USB if USB
1079 select SPL_BOARD_INIT if SPL
1080 select SPL_CLK if SPL
1081 select SPL_DM if SPL
1082 select SPL_DM_SPI if SPL
1083 select SPL_DM_SPI_FLASH if SPL
1084 select SPL_OF_CONTROL if SPL
1085 select SPL_SEPARATE_BSS if SPL
1087 imply ARCH_EARLY_INIT_R
1088 imply BOARD_LATE_INIT
1092 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1095 config ARCH_ZYNQMP_R5
1096 bool "Xilinx ZynqMP R5 based platform"
1100 select DM_ETH if NET
1101 select DM_MMC if MMC
1108 bool "Xilinx ZynqMP based platform"
1112 select DM_ETH if NET
1114 select DM_MMC if MMC
1116 select DM_SPI if SPI
1117 select DM_SPI_FLASH if DM_SPI
1118 select DM_USB if USB
1121 select SPL_BOARD_INIT if SPL
1122 select SPL_CLK if SPL
1123 select SPL_DM if SPL
1124 select SPL_DM_SPI if SPI && SPL_DM
1125 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1126 select SPL_DM_MAILBOX if SPL
1127 select SPL_FIRMWARE if SPL
1128 select SPL_SEPARATE_BSS if SPL
1131 imply BOARD_LATE_INIT
1133 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1140 imply DISTRO_DEFAULTS
1143 config TARGET_VEXPRESS64_AEMV8A
1144 bool "Support vexpress_aemv8a"
1148 config TARGET_VEXPRESS64_BASE_FVP
1149 bool "Support Versatile Express ARMv8a FVP BASE model"
1154 config TARGET_VEXPRESS64_JUNO
1155 bool "Support Versatile Express Juno Development Platform"
1170 config TARGET_TOTAL_COMPUTE
1171 bool "Support Total Compute Platform"
1179 config TARGET_LS2080A_EMU
1180 bool "Support ls2080a_emu"
1183 select ARMV8_MULTIENTRY
1184 select FSL_DDR_SYNC_REFRESH
1186 Support for Freescale LS2080A_EMU platform.
1187 The LS2080A Development System (EMULATOR) is a pre-silicon
1188 development platform that supports the QorIQ LS2080A
1189 Layerscape Architecture processor.
1191 config TARGET_LS1088AQDS
1192 bool "Support ls1088aqds"
1195 select ARMV8_MULTIENTRY
1196 select ARCH_SUPPORT_TFABOOT
1197 select BOARD_LATE_INIT
1199 select FSL_DDR_INTERACTIVE if !SD_BOOT
1201 Support for NXP LS1088AQDS platform.
1202 The LS1088A Development System (QDS) is a high-performance
1203 development platform that supports the QorIQ LS1088A
1204 Layerscape Architecture processor.
1206 config TARGET_LS2080AQDS
1207 bool "Support ls2080aqds"
1210 select ARMV8_MULTIENTRY
1211 select ARCH_SUPPORT_TFABOOT
1212 select BOARD_LATE_INIT
1217 select FSL_DDR_INTERACTIVE if !SPL
1219 Support for Freescale LS2080AQDS platform.
1220 The LS2080A Development System (QDS) is a high-performance
1221 development platform that supports the QorIQ LS2080A
1222 Layerscape Architecture processor.
1224 config TARGET_LS2080ARDB
1225 bool "Support ls2080ardb"
1228 select ARMV8_MULTIENTRY
1229 select ARCH_SUPPORT_TFABOOT
1230 select BOARD_LATE_INIT
1233 select FSL_DDR_INTERACTIVE if !SPL
1237 Support for Freescale LS2080ARDB platform.
1238 The LS2080A Reference design board (RDB) is a high-performance
1239 development platform that supports the QorIQ LS2080A
1240 Layerscape Architecture processor.
1242 config TARGET_LS2081ARDB
1243 bool "Support ls2081ardb"
1246 select ARMV8_MULTIENTRY
1247 select BOARD_LATE_INIT
1250 Support for Freescale LS2081ARDB platform.
1251 The LS2081A Reference design board (RDB) is a high-performance
1252 development platform that supports the QorIQ LS2081A/LS2041A
1253 Layerscape Architecture processor.
1255 config TARGET_LX2160ARDB
1256 bool "Support lx2160ardb"
1259 select ARMV8_MULTIENTRY
1260 select ARCH_SUPPORT_TFABOOT
1261 select BOARD_LATE_INIT
1263 Support for NXP LX2160ARDB platform.
1264 The lx2160ardb (LX2160A Reference design board (RDB)
1265 is a high-performance development platform that supports the
1266 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1268 config TARGET_LX2160AQDS
1269 bool "Support lx2160aqds"
1272 select ARMV8_MULTIENTRY
1273 select ARCH_SUPPORT_TFABOOT
1274 select BOARD_LATE_INIT
1276 Support for NXP LX2160AQDS platform.
1277 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1278 is a high-performance development platform that supports the
1279 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1281 config TARGET_LX2162AQDS
1282 bool "Support lx2162aqds"
1284 select ARCH_MISC_INIT
1286 select ARMV8_MULTIENTRY
1287 select ARCH_SUPPORT_TFABOOT
1288 select BOARD_LATE_INIT
1290 Support for NXP LX2162AQDS platform.
1291 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1294 bool "Support HiKey 96boards Consumer Edition Platform"
1301 select SPECIFY_CONSOLE_INDEX
1304 Support for HiKey 96boards platform. It features a HI6220
1305 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1307 config TARGET_HIKEY960
1308 bool "Support HiKey960 96boards Consumer Edition Platform"
1316 Support for HiKey960 96boards platform. It features a HI3660
1317 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1319 config TARGET_POPLAR
1320 bool "Support Poplar 96boards Enterprise Edition Platform"
1329 Support for Poplar 96boards EE platform. It features a HI3798cv200
1330 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1331 making it capable of running any commercial set-top solution based on
1334 config TARGET_LS1012AQDS
1335 bool "Support ls1012aqds"
1338 select ARCH_SUPPORT_TFABOOT
1339 select BOARD_LATE_INIT
1341 Support for Freescale LS1012AQDS platform.
1342 The LS1012A Development System (QDS) is a high-performance
1343 development platform that supports the QorIQ LS1012A
1344 Layerscape Architecture processor.
1346 config TARGET_LS1012ARDB
1347 bool "Support ls1012ardb"
1350 select ARCH_SUPPORT_TFABOOT
1351 select BOARD_LATE_INIT
1355 Support for Freescale LS1012ARDB platform.
1356 The LS1012A Reference design board (RDB) is a high-performance
1357 development platform that supports the QorIQ LS1012A
1358 Layerscape Architecture processor.
1360 config TARGET_LS1012A2G5RDB
1361 bool "Support ls1012a2g5rdb"
1364 select ARCH_SUPPORT_TFABOOT
1365 select BOARD_LATE_INIT
1368 Support for Freescale LS1012A2G5RDB platform.
1369 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1370 development platform that supports the QorIQ LS1012A
1371 Layerscape Architecture processor.
1373 config TARGET_LS1012AFRWY
1374 bool "Support ls1012afrwy"
1377 select ARCH_SUPPORT_TFABOOT
1378 select BOARD_LATE_INIT
1382 Support for Freescale LS1012AFRWY platform.
1383 The LS1012A FRWY board (FRWY) is a high-performance
1384 development platform that supports the QorIQ LS1012A
1385 Layerscape Architecture processor.
1387 config TARGET_LS1012AFRDM
1388 bool "Support ls1012afrdm"
1391 select ARCH_SUPPORT_TFABOOT
1393 Support for Freescale LS1012AFRDM platform.
1394 The LS1012A Freedom board (FRDM) is a high-performance
1395 development platform that supports the QorIQ LS1012A
1396 Layerscape Architecture processor.
1398 config TARGET_LS1028AQDS
1399 bool "Support ls1028aqds"
1402 select ARMV8_MULTIENTRY
1403 select ARCH_SUPPORT_TFABOOT
1404 select BOARD_LATE_INIT
1406 Support for Freescale LS1028AQDS platform
1407 The LS1028A Development System (QDS) is a high-performance
1408 development platform that supports the QorIQ LS1028A
1409 Layerscape Architecture processor.
1411 config TARGET_LS1028ARDB
1412 bool "Support ls1028ardb"
1415 select ARMV8_MULTIENTRY
1416 select ARCH_SUPPORT_TFABOOT
1417 select BOARD_LATE_INIT
1419 Support for Freescale LS1028ARDB platform
1420 The LS1028A Development System (RDB) is a high-performance
1421 development platform that supports the QorIQ LS1028A
1422 Layerscape Architecture processor.
1424 config TARGET_LS1088ARDB
1425 bool "Support ls1088ardb"
1428 select ARMV8_MULTIENTRY
1429 select ARCH_SUPPORT_TFABOOT
1430 select BOARD_LATE_INIT
1432 select FSL_DDR_INTERACTIVE if !SD_BOOT
1434 Support for NXP LS1088ARDB platform.
1435 The LS1088A Reference design board (RDB) is a high-performance
1436 development platform that supports the QorIQ LS1088A
1437 Layerscape Architecture processor.
1439 config TARGET_LS1021AQDS
1440 bool "Support ls1021aqds"
1442 select ARCH_SUPPORT_PSCI
1443 select BOARD_EARLY_INIT_F
1444 select BOARD_LATE_INIT
1446 select CPU_V7_HAS_NONSEC
1447 select CPU_V7_HAS_VIRT
1448 select LS1_DEEP_SLEEP
1451 select FSL_DDR_INTERACTIVE
1452 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1453 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1456 config TARGET_LS1021ATWR
1457 bool "Support ls1021atwr"
1459 select ARCH_SUPPORT_PSCI
1460 select BOARD_EARLY_INIT_F
1461 select BOARD_LATE_INIT
1463 select CPU_V7_HAS_NONSEC
1464 select CPU_V7_HAS_VIRT
1465 select LS1_DEEP_SLEEP
1467 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1470 config TARGET_LS1021ATSN
1471 bool "Support ls1021atsn"
1473 select ARCH_SUPPORT_PSCI
1474 select BOARD_EARLY_INIT_F
1475 select BOARD_LATE_INIT
1477 select CPU_V7_HAS_NONSEC
1478 select CPU_V7_HAS_VIRT
1479 select LS1_DEEP_SLEEP
1483 config TARGET_LS1021AIOT
1484 bool "Support ls1021aiot"
1486 select ARCH_SUPPORT_PSCI
1487 select BOARD_LATE_INIT
1489 select CPU_V7_HAS_NONSEC
1490 select CPU_V7_HAS_VIRT
1492 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1495 Support for Freescale LS1021AIOT platform.
1496 The LS1021A Freescale board (IOT) is a high-performance
1497 development platform that supports the QorIQ LS1021A
1498 Layerscape Architecture processor.
1500 config TARGET_LS1043AQDS
1501 bool "Support ls1043aqds"
1504 select ARMV8_MULTIENTRY
1505 select ARCH_SUPPORT_TFABOOT
1506 select BOARD_EARLY_INIT_F
1507 select BOARD_LATE_INIT
1509 select FSL_DDR_INTERACTIVE if !SPL
1510 select FSL_DSPI if !SPL_NO_DSPI
1511 select DM_SPI_FLASH if FSL_DSPI
1515 Support for Freescale LS1043AQDS platform.
1517 config TARGET_LS1043ARDB
1518 bool "Support ls1043ardb"
1521 select ARMV8_MULTIENTRY
1522 select ARCH_SUPPORT_TFABOOT
1523 select BOARD_EARLY_INIT_F
1524 select BOARD_LATE_INIT
1526 select FSL_DSPI if !SPL_NO_DSPI
1527 select DM_SPI_FLASH if FSL_DSPI
1529 Support for Freescale LS1043ARDB platform.
1531 config TARGET_LS1046AQDS
1532 bool "Support ls1046aqds"
1535 select ARMV8_MULTIENTRY
1536 select ARCH_SUPPORT_TFABOOT
1537 select BOARD_EARLY_INIT_F
1538 select BOARD_LATE_INIT
1539 select DM_SPI_FLASH if DM_SPI
1541 select FSL_DDR_BIST if !SPL
1542 select FSL_DDR_INTERACTIVE if !SPL
1543 select FSL_DDR_INTERACTIVE if !SPL
1546 Support for Freescale LS1046AQDS platform.
1547 The LS1046A Development System (QDS) is a high-performance
1548 development platform that supports the QorIQ LS1046A
1549 Layerscape Architecture processor.
1551 config TARGET_LS1046ARDB
1552 bool "Support ls1046ardb"
1555 select ARMV8_MULTIENTRY
1556 select ARCH_SUPPORT_TFABOOT
1557 select BOARD_EARLY_INIT_F
1558 select BOARD_LATE_INIT
1559 select DM_SPI_FLASH if DM_SPI
1560 select POWER_MC34VR500
1563 select FSL_DDR_INTERACTIVE if !SPL
1566 Support for Freescale LS1046ARDB platform.
1567 The LS1046A Reference Design Board (RDB) is a high-performance
1568 development platform that supports the QorIQ LS1046A
1569 Layerscape Architecture processor.
1571 config TARGET_LS1046AFRWY
1572 bool "Support ls1046afrwy"
1575 select ARMV8_MULTIENTRY
1576 select ARCH_SUPPORT_TFABOOT
1577 select BOARD_EARLY_INIT_F
1578 select BOARD_LATE_INIT
1579 select DM_SPI_FLASH if DM_SPI
1582 Support for Freescale LS1046AFRWY platform.
1583 The LS1046A Freeway Board (FRWY) is a high-performance
1584 development platform that supports the QorIQ LS1046A
1585 Layerscape Architecture processor.
1591 select ARMV8_MULTIENTRY
1595 Support for Kontron SMARC-sAL28 board.
1597 config TARGET_COLIBRI_PXA270
1598 bool "Support colibri_pxa270"
1601 config ARCH_UNIPHIER
1602 bool "Socionext UniPhier SoCs"
1603 select BOARD_LATE_INIT
1613 select OF_BOARD_SETUP
1617 select SPL_BOARD_INIT if SPL
1618 select SPL_DM if SPL
1619 select SPL_LIBCOMMON_SUPPORT if SPL
1620 select SPL_LIBGENERIC_SUPPORT if SPL
1621 select SPL_OF_CONTROL if SPL
1622 select SPL_PINCTRL if SPL
1625 imply DISTRO_DEFAULTS
1628 Support for UniPhier SoC family developed by Socionext Inc.
1629 (formerly, System LSI Business Division of Panasonic Corporation)
1632 bool "Support STMicroelectronics STM32 MCU with cortex M"
1639 bool "Support STMicrolectronics SoCs"
1648 Support for STMicroelectronics STiH407/10 SoC family.
1649 This SoC is used on Linaro 96Board STiH410-B2260
1652 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1653 select ARCH_MISC_INIT
1654 select ARCH_SUPPORT_TFABOOT
1655 select BOARD_LATE_INIT
1664 select OF_SYSTEM_SETUP
1670 select SYS_THUMB_BUILD
1674 imply OF_LIBFDT_OVERLAY
1675 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1678 Support for STM32MP SoC family developed by STMicroelectronics,
1679 MPUs based on ARM cortex A core
1680 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1681 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1683 SPL is the unsecure FSBL for the basic boot chain.
1685 config ARCH_ROCKCHIP
1686 bool "Support Rockchip SoCs"
1688 select BINMAN if SPL_OPTEE
1698 select DM_USB if USB
1699 select ENABLE_ARM_SOC_BOOT0_HOOK
1702 select SPL_DM if SPL
1703 select SPL_DM_SPI if SPL
1704 select SPL_DM_SPI_FLASH if SPL
1706 select SYS_THUMB_BUILD if !ARM64
1709 imply DEBUG_UART_BOARD_INIT
1710 imply DISTRO_DEFAULTS
1712 imply SARADC_ROCKCHIP
1714 imply SPL_SYS_MALLOC_SIMPLE
1717 imply USB_FUNCTION_FASTBOOT
1719 config ARCH_OCTEONTX
1720 bool "Support OcteonTX SoCs"
1726 select BOARD_LATE_INIT
1727 select SYS_CACHE_SHIFT_7
1729 config ARCH_OCTEONTX2
1730 bool "Support OcteonTX2 SoCs"
1736 select BOARD_LATE_INIT
1737 select SYS_CACHE_SHIFT_7
1739 config TARGET_THUNDERX_88XX
1740 bool "Support ThunderX 88xx"
1744 select SYS_CACHE_SHIFT_7
1747 bool "Support Aspeed SoCs"
1752 config TARGET_DURIAN
1753 bool "Support Phytium Durian Platform"
1756 Support for durian platform.
1757 It has 2GB Sdram, uart and pcie.
1759 config TARGET_PRESIDIO_ASIC
1760 bool "Support Cortina Presidio ASIC Platform"
1763 config TARGET_XENGUEST_ARM64
1764 bool "Xen guest ARM64"
1768 select LINUX_KERNEL_IMAGE_HEADER
1773 config ARCH_SUPPORT_TFABOOT
1777 bool "Support for booting from TF-A"
1778 depends on ARCH_SUPPORT_TFABOOT
1781 Some platforms support the setup of secure registers (for instance
1782 for CPU errata handling) or provide secure services like PSCI.
1783 Those services could also be provided by other firmware parts
1784 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
1785 does not need to (and cannot) execute this code.
1786 Enabling this option will make a U-Boot binary that is relying
1787 on other firmware layers to provide secure functionality.
1789 config TI_SECURE_DEVICE
1790 bool "HS Device Type Support"
1791 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1793 If a high secure (HS) device type is being used, this config
1794 must be set. This option impacts various aspects of the
1795 build system (to create signed boot images that can be
1796 authenticated) and the code. See the doc/README.ti-secure
1797 file for further details.
1799 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1800 config ISW_ENTRY_ADDR
1801 hex "Address in memory or XIP address of bootloader entry point"
1802 default 0x402F4000 if AM43XX
1803 default 0x402F0400 if AM33XX
1804 default 0x40301350 if OMAP54XX
1806 After any reset, the boot ROM searches the boot media for a valid
1807 boot image. For non-XIP devices, the ROM then copies the image into
1808 internal memory. For all boot modes, after the ROM processes the
1809 boot image it eventually computes the entry point address depending
1810 on the device type (secure/non-secure), boot media (xip/non-xip) and
1814 source "arch/arm/mach-aspeed/Kconfig"
1816 source "arch/arm/mach-at91/Kconfig"
1818 source "arch/arm/mach-bcm283x/Kconfig"
1820 source "arch/arm/mach-bcmstb/Kconfig"
1822 source "arch/arm/mach-davinci/Kconfig"
1824 source "arch/arm/mach-exynos/Kconfig"
1826 source "arch/arm/mach-highbank/Kconfig"
1828 source "arch/arm/mach-integrator/Kconfig"
1830 source "arch/arm/mach-ipq40xx/Kconfig"
1832 source "arch/arm/mach-k3/Kconfig"
1834 source "arch/arm/mach-keystone/Kconfig"
1836 source "arch/arm/mach-kirkwood/Kconfig"
1838 source "arch/arm/mach-lpc32xx/Kconfig"
1840 source "arch/arm/mach-mvebu/Kconfig"
1842 source "arch/arm/mach-octeontx/Kconfig"
1844 source "arch/arm/mach-octeontx2/Kconfig"
1846 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1848 source "arch/arm/mach-imx/mx2/Kconfig"
1850 source "arch/arm/mach-imx/mx3/Kconfig"
1852 source "arch/arm/mach-imx/mx5/Kconfig"
1854 source "arch/arm/mach-imx/mx6/Kconfig"
1856 source "arch/arm/mach-imx/mx7/Kconfig"
1858 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1860 source "arch/arm/mach-imx/imx8/Kconfig"
1862 source "arch/arm/mach-imx/imx8m/Kconfig"
1864 source "arch/arm/mach-imx/imxrt/Kconfig"
1866 source "arch/arm/mach-imx/mxs/Kconfig"
1868 source "arch/arm/mach-omap2/Kconfig"
1870 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1872 source "arch/arm/mach-orion5x/Kconfig"
1874 source "arch/arm/mach-owl/Kconfig"
1876 source "arch/arm/mach-rmobile/Kconfig"
1878 source "arch/arm/mach-meson/Kconfig"
1880 source "arch/arm/mach-mediatek/Kconfig"
1882 source "arch/arm/mach-qemu/Kconfig"
1884 source "arch/arm/mach-rockchip/Kconfig"
1886 source "arch/arm/mach-s5pc1xx/Kconfig"
1888 source "arch/arm/mach-snapdragon/Kconfig"
1890 source "arch/arm/mach-socfpga/Kconfig"
1892 source "arch/arm/mach-sti/Kconfig"
1894 source "arch/arm/mach-stm32/Kconfig"
1896 source "arch/arm/mach-stm32mp/Kconfig"
1898 source "arch/arm/mach-sunxi/Kconfig"
1900 source "arch/arm/mach-tegra/Kconfig"
1902 source "arch/arm/mach-u8500/Kconfig"
1904 source "arch/arm/mach-uniphier/Kconfig"
1906 source "arch/arm/cpu/armv7/vf610/Kconfig"
1908 source "arch/arm/mach-zynq/Kconfig"
1910 source "arch/arm/mach-zynqmp/Kconfig"
1912 source "arch/arm/mach-versal/Kconfig"
1914 source "arch/arm/mach-zynqmp-r5/Kconfig"
1916 source "arch/arm/cpu/armv7/Kconfig"
1918 source "arch/arm/cpu/armv8/Kconfig"
1920 source "arch/arm/mach-imx/Kconfig"
1922 source "arch/arm/mach-nexell/Kconfig"
1924 source "board/armltd/total_compute/Kconfig"
1926 source "board/bosch/shc/Kconfig"
1927 source "board/bosch/guardian/Kconfig"
1928 source "board/CarMediaLab/flea3/Kconfig"
1929 source "board/Marvell/aspenite/Kconfig"
1930 source "board/Marvell/gplugd/Kconfig"
1931 source "board/Marvell/octeontx/Kconfig"
1932 source "board/Marvell/octeontx2/Kconfig"
1933 source "board/armltd/vexpress64/Kconfig"
1934 source "board/cortina/presidio-asic/Kconfig"
1935 source "board/broadcom/bcm963158/Kconfig"
1936 source "board/broadcom/bcm968360bg/Kconfig"
1937 source "board/broadcom/bcm968580xref/Kconfig"
1938 source "board/broadcom/bcmcygnus/Kconfig"
1939 source "board/broadcom/bcmnsp/Kconfig"
1940 source "board/broadcom/bcmns3/Kconfig"
1941 source "board/cavium/thunderx/Kconfig"
1942 source "board/cirrus/edb93xx/Kconfig"
1943 source "board/eets/pdu001/Kconfig"
1944 source "board/emulation/qemu-arm/Kconfig"
1945 source "board/freescale/ls2080aqds/Kconfig"
1946 source "board/freescale/ls2080ardb/Kconfig"
1947 source "board/freescale/ls1088a/Kconfig"
1948 source "board/freescale/ls1028a/Kconfig"
1949 source "board/freescale/ls1021aqds/Kconfig"
1950 source "board/freescale/ls1043aqds/Kconfig"
1951 source "board/freescale/ls1021atwr/Kconfig"
1952 source "board/freescale/ls1021atsn/Kconfig"
1953 source "board/freescale/ls1021aiot/Kconfig"
1954 source "board/freescale/ls1046aqds/Kconfig"
1955 source "board/freescale/ls1043ardb/Kconfig"
1956 source "board/freescale/ls1046ardb/Kconfig"
1957 source "board/freescale/ls1046afrwy/Kconfig"
1958 source "board/freescale/ls1012aqds/Kconfig"
1959 source "board/freescale/ls1012ardb/Kconfig"
1960 source "board/freescale/ls1012afrdm/Kconfig"
1961 source "board/freescale/lx2160a/Kconfig"
1962 source "board/grinn/chiliboard/Kconfig"
1963 source "board/hisilicon/hikey/Kconfig"
1964 source "board/hisilicon/hikey960/Kconfig"
1965 source "board/hisilicon/poplar/Kconfig"
1966 source "board/isee/igep003x/Kconfig"
1967 source "board/kontron/sl28/Kconfig"
1968 source "board/myir/mys_6ulx/Kconfig"
1969 source "board/spear/spear300/Kconfig"
1970 source "board/spear/spear310/Kconfig"
1971 source "board/spear/spear320/Kconfig"
1972 source "board/spear/spear600/Kconfig"
1973 source "board/spear/x600/Kconfig"
1974 source "board/st/stv0991/Kconfig"
1975 source "board/tcl/sl50/Kconfig"
1976 source "board/toradex/colibri_pxa270/Kconfig"
1977 source "board/variscite/dart_6ul/Kconfig"
1978 source "board/vscom/baltos/Kconfig"
1979 source "board/phytium/durian/Kconfig"
1980 source "board/xen/xenguest_arm64/Kconfig"
1982 source "arch/arm/Kconfig.debug"
1987 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
1988 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
1989 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64