4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_TRACEHOOK
32 select HAVE_CONTEXT_TRACKING
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_CC_STACKPROTECTOR
35 select HAVE_DEBUG_KMEMLEAK
36 select HAVE_DMA_API_DEBUG
38 select HAVE_DMA_CONTIGUOUS if MMU
39 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
40 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
41 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
42 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
43 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
44 select HAVE_GENERIC_DMA_COHERENT
45 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
46 select HAVE_IDE if PCI || ISA || PCMCIA
47 select HAVE_IRQ_TIME_ACCOUNTING
48 select HAVE_KERNEL_GZIP
49 select HAVE_KERNEL_LZ4
50 select HAVE_KERNEL_LZMA
51 select HAVE_KERNEL_LZO
53 select HAVE_KPROBES if !XIP_KERNEL
54 select HAVE_KRETPROBES if (HAVE_KPROBES)
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
58 select HAVE_PERF_EVENTS
60 select HAVE_PERF_USER_STACK_DUMP
61 select HAVE_REGS_AND_STACK_ACCESS_API
62 select HAVE_SYSCALL_TRACEPOINTS
64 select HAVE_VIRT_CPU_ACCOUNTING_GEN
65 select IRQ_FORCED_THREADING
67 select MODULES_USE_ELF_REL
70 select OLD_SIGSUSPEND3
71 select PERF_USE_VMALLOC
73 select SYS_SUPPORTS_APM_EMULATION
74 # Above selects are sorted alphabetically; please add new ones
75 # according to that. Thanks.
77 The ARM series is a line of low-power-consumption RISC chip designs
78 licensed by ARM Ltd and targeted at embedded applications and
79 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
80 manufactured, but legacy ARM-based PC hardware remains popular in
81 Europe. There is an ARM Linux project with a web page at
82 <http://www.arm.linux.org.uk/>.
84 config ARM_HAS_SG_CHAIN
87 config NEED_SG_DMA_LENGTH
90 config ARM_DMA_USE_IOMMU
92 select ARM_HAS_SG_CHAIN
93 select NEED_SG_DMA_LENGTH
97 config ARM_DMA_IOMMU_ALIGNMENT
98 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
102 DMA mapping framework by default aligns all buffers to the smallest
103 PAGE_SIZE order which is greater than or equal to the requested buffer
104 size. This works well for buffers up to a few hundreds kilobytes, but
105 for larger buffers it just a waste of address space. Drivers which has
106 relatively small addressing window (like 64Mib) might run out of
107 virtual space with just a few allocations.
109 With this parameter you can specify the maximum PAGE_SIZE order for
110 DMA IOMMU buffers. Larger buffers will be aligned only to this
111 specified order. The order is expressed as a power of two multiplied
119 config MIGHT_HAVE_PCI
122 config SYS_SUPPORTS_APM_EMULATION
127 select GENERIC_ALLOCATOR
138 The Extended Industry Standard Architecture (EISA) bus was
139 developed as an open alternative to the IBM MicroChannel bus.
141 The EISA bus provided some of the features of the IBM MicroChannel
142 bus while maintaining backward compatibility with cards made for
143 the older ISA bus. The EISA bus saw limited use between 1988 and
144 1995 when it was made obsolete by the PCI bus.
146 Say Y here if you are building a kernel for an EISA-based machine.
153 config STACKTRACE_SUPPORT
157 config HAVE_LATENCYTOP_SUPPORT
162 config LOCKDEP_SUPPORT
166 config TRACE_IRQFLAGS_SUPPORT
170 config RWSEM_GENERIC_SPINLOCK
174 config RWSEM_XCHGADD_ALGORITHM
177 config ARCH_HAS_ILOG2_U32
180 config ARCH_HAS_ILOG2_U64
183 config ARCH_HAS_CPUFREQ
186 Internal node to signify that the ARCH has CPUFREQ support
187 and that the relevant menu configurations are displayed for
190 config ARCH_HAS_BANDGAP
193 config GENERIC_HWEIGHT
197 config GENERIC_CALIBRATE_DELAY
201 config ARCH_MAY_HAVE_PC_FDC
207 config NEED_DMA_MAP_STATE
210 config ARCH_HAS_DMA_SET_COHERENT_MASK
213 config GENERIC_ISA_DMA
219 config NEED_RET_TO_USER
227 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
228 default DRAM_BASE if REMAP_VECTORS_TO_RAM
231 The base address of exception vectors. This must be two pages
234 config ARM_PATCH_PHYS_VIRT
235 bool "Patch physical to virtual translations at runtime" if EMBEDDED
237 depends on !XIP_KERNEL && MMU
238 depends on !ARCH_REALVIEW || !SPARSEMEM
240 Patch phys-to-virt and virt-to-phys translation functions at
241 boot and module load time according to the position of the
242 kernel in system memory.
244 This can only be used with non-XIP MMU kernels where the base
245 of physical memory is at a 16MB boundary.
247 Only disable this option if you know that you do not require
248 this feature (eg, building a kernel for a single machine) and
249 you need to shrink the kernel to the minimal size.
251 config NEED_MACH_GPIO_H
254 Select this when mach/gpio.h is required to provide special
255 definitions for this platform. The need for mach/gpio.h should
256 be avoided when possible.
258 config NEED_MACH_IO_H
261 Select this when mach/io.h is required to provide special
262 definitions for this platform. The need for mach/io.h should
263 be avoided when possible.
265 config NEED_MACH_MEMORY_H
268 Select this when mach/memory.h is required to provide special
269 definitions for this platform. The need for mach/memory.h should
270 be avoided when possible.
273 hex "Physical address of main memory" if MMU
274 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
275 default DRAM_BASE if !MMU
277 Please provide the physical address corresponding to the
278 location of main memory in your system.
284 source "init/Kconfig"
286 source "kernel/Kconfig.freezer"
291 bool "MMU-based Paged Memory Management Support"
294 Select if you want MMU-based virtualised addressing space
295 support by paged memory management. If unsure, say 'Y'.
298 # The "ARM system type" choice list is ordered alphabetically by option
299 # text. Please add new entries in the option alphabetic order.
302 prompt "ARM system type"
303 default ARCH_VERSATILE if !MMU
304 default ARCH_MULTIPLATFORM if MMU
306 config ARCH_MULTIPLATFORM
307 bool "Allow multiple platforms to be selected"
309 select ARM_PATCH_PHYS_VIRT
312 select MULTI_IRQ_HANDLER
316 config ARCH_INTEGRATOR
317 bool "ARM Ltd. Integrator family"
318 select ARCH_HAS_CPUFREQ
321 select COMMON_CLK_VERSATILE
322 select GENERIC_CLOCKEVENTS
325 select MULTI_IRQ_HANDLER
326 select NEED_MACH_MEMORY_H
327 select PLAT_VERSATILE
330 select VERSATILE_FPGA_IRQ
332 Support for ARM's Integrator platform.
335 bool "ARM Ltd. RealView family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
340 select COMMON_CLK_VERSATILE
341 select GENERIC_CLOCKEVENTS
342 select GPIO_PL061 if GPIOLIB
344 select NEED_MACH_MEMORY_H
345 select PLAT_VERSATILE
346 select PLAT_VERSATILE_CLCD
348 This enables support for ARM Ltd RealView boards.
350 config ARCH_VERSATILE
351 bool "ARM Ltd. Versatile family"
352 select ARCH_WANT_OPTIONAL_GPIOLIB
354 select ARM_TIMER_SP804
357 select GENERIC_CLOCKEVENTS
358 select HAVE_MACH_CLKDEV
360 select PLAT_VERSATILE
361 select PLAT_VERSATILE_CLCD
362 select PLAT_VERSATILE_CLOCK
363 select VERSATILE_FPGA_IRQ
365 This enables support for ARM Ltd Versatile board.
369 select ARCH_REQUIRE_GPIOLIB
372 select NEED_MACH_GPIO_H
373 select NEED_MACH_IO_H if PCCARD
375 select PINCTRL_AT91 if USE_OF
377 This enables support for systems based on Atmel
378 AT91RM9200 and AT91SAM9* processors.
381 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
382 select ARCH_REQUIRE_GPIOLIB
387 select GENERIC_CLOCKEVENTS
389 select MULTI_IRQ_HANDLER
392 Support for Cirrus Logic 711x/721x/731x based boards.
395 bool "Cortina Systems Gemini"
396 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
401 Support for the Cortina Systems Gemini family SoCs
405 select ARCH_USES_GETTIMEOFFSET
408 select NEED_MACH_IO_H
409 select NEED_MACH_MEMORY_H
412 This is an evaluation board for the StrongARM processor available
413 from Digital. It has limited hardware on-board, including an
414 Ethernet interface, two PCMCIA sockets, two serial ports and a
418 bool "Energy Micro efm32"
420 select ARCH_REQUIRE_GPIOLIB
422 # CLKSRC_MMIO is wrong here, but needed until a proper fix is merged,
423 # i.e. CLKSRC_EFM32 selecting CLKSRC_MMIO
428 select GENERIC_CLOCKEVENTS
434 Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
439 select ARCH_HAS_HOLES_MEMORYMODEL
440 select ARCH_REQUIRE_GPIOLIB
441 select ARCH_USES_GETTIMEOFFSET
446 select NEED_MACH_MEMORY_H
448 This enables support for the Cirrus EP93xx series of CPUs.
450 config ARCH_FOOTBRIDGE
454 select GENERIC_CLOCKEVENTS
456 select NEED_MACH_IO_H if !MMU
457 select NEED_MACH_MEMORY_H
459 Support for systems based on the DC21285 companion chip
460 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
463 bool "Hilscher NetX based"
467 select GENERIC_CLOCKEVENTS
469 This enables support for systems based on the Hilscher NetX Soc
475 select NEED_MACH_MEMORY_H
476 select NEED_RET_TO_USER
481 Support for Intel's IOP13XX (XScale) family of processors.
486 select ARCH_REQUIRE_GPIOLIB
489 select NEED_RET_TO_USER
493 Support for Intel's 80219 and IOP32X (XScale) family of
499 select ARCH_REQUIRE_GPIOLIB
502 select NEED_RET_TO_USER
506 Support for Intel's IOP33X (XScale) family of processors.
511 select ARCH_HAS_DMA_SET_COHERENT_MASK
512 select ARCH_SUPPORTS_BIG_ENDIAN
513 select ARCH_REQUIRE_GPIOLIB
516 select DMABOUNCE if PCI
517 select GENERIC_CLOCKEVENTS
518 select MIGHT_HAVE_PCI
519 select NEED_MACH_IO_H
520 select USB_EHCI_BIG_ENDIAN_DESC
521 select USB_EHCI_BIG_ENDIAN_MMIO
523 Support for Intel's IXP4XX (XScale) family of processors.
527 select ARCH_REQUIRE_GPIOLIB
529 select GENERIC_CLOCKEVENTS
530 select MIGHT_HAVE_PCI
534 select PLAT_ORION_LEGACY
535 select USB_ARCH_HAS_EHCI
537 Support for the Marvell Dove SoC 88AP510
540 bool "Marvell Kirkwood"
541 select ARCH_HAS_CPUFREQ
542 select ARCH_REQUIRE_GPIOLIB
544 select GENERIC_CLOCKEVENTS
549 select PINCTRL_KIRKWOOD
550 select PLAT_ORION_LEGACY
552 Support for the following Marvell Kirkwood series SoCs:
553 88F6180, 88F6192 and 88F6281.
556 bool "Marvell MV78xx0"
557 select ARCH_REQUIRE_GPIOLIB
559 select GENERIC_CLOCKEVENTS
562 select PLAT_ORION_LEGACY
564 Support for the following Marvell MV78xx0 series SoCs:
570 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
575 select PLAT_ORION_LEGACY
577 Support for the following Marvell Orion 5x series SoCs:
578 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
579 Orion-2 (5281), Orion-1-90 (6183).
582 bool "Marvell PXA168/910/MMP2"
584 select ARCH_REQUIRE_GPIOLIB
586 select GENERIC_ALLOCATOR
587 select GENERIC_CLOCKEVENTS
590 select MULTI_IRQ_HANDLER
595 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
598 bool "Micrel/Kendin KS8695"
599 select ARCH_REQUIRE_GPIOLIB
602 select GENERIC_CLOCKEVENTS
603 select NEED_MACH_MEMORY_H
605 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
606 System-on-Chip devices.
609 bool "Nuvoton W90X900 CPU"
610 select ARCH_REQUIRE_GPIOLIB
614 select GENERIC_CLOCKEVENTS
616 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
617 At present, the w90x900 has been renamed nuc900, regarding
618 the ARM series product line, you can login the following
619 link address to know more.
621 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
622 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
626 select ARCH_REQUIRE_GPIOLIB
631 select GENERIC_CLOCKEVENTS
634 select USB_ARCH_HAS_OHCI
637 Support for the NXP LPC32XX family of processors
640 bool "PXA2xx/PXA3xx-based"
642 select ARCH_HAS_CPUFREQ
644 select ARCH_REQUIRE_GPIOLIB
645 select ARM_CPU_SUSPEND if PM
649 select GENERIC_CLOCKEVENTS
652 select MULTI_IRQ_HANDLER
656 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
661 select ARCH_REQUIRE_GPIOLIB
663 select GENERIC_CLOCKEVENTS
665 Support for Qualcomm MSM/QSD based systems. This runs on the
666 apps processor of the MSM/QSD and depends on a shared memory
667 interface to the modem processor which runs the baseband
668 stack and controls some vital subsystems
669 (clock and power control, etc).
671 config ARCH_SHMOBILE_LEGACY
672 bool "Renesas ARM SoCs (non-multiplatform)"
674 select ARM_PATCH_PHYS_VIRT
676 select GENERIC_CLOCKEVENTS
677 select HAVE_ARM_SCU if SMP
678 select HAVE_ARM_TWD if SMP
679 select HAVE_MACH_CLKDEV
681 select MIGHT_HAVE_CACHE_L2X0
682 select MULTI_IRQ_HANDLER
685 select PM_GENERIC_DOMAINS if PM
688 Support for Renesas ARM SoC platforms using a non-multiplatform
689 kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
695 select ARCH_MAY_HAVE_PC_FDC
696 select ARCH_SPARSEMEM_ENABLE
697 select ARCH_USES_GETTIMEOFFSET
700 select HAVE_PATA_PLATFORM
702 select NEED_MACH_IO_H
703 select NEED_MACH_MEMORY_H
707 On the Acorn Risc-PC, Linux can support the internal IDE disk and
708 CD-ROM interface, serial and parallel port, and the floppy drive.
712 select ARCH_HAS_CPUFREQ
714 select ARCH_REQUIRE_GPIOLIB
715 select ARCH_SPARSEMEM_ENABLE
720 select GENERIC_CLOCKEVENTS
723 select NEED_MACH_MEMORY_H
726 Support for StrongARM 11x0 based boards.
729 bool "Samsung S3C24XX SoCs"
730 select ARCH_HAS_CPUFREQ
731 select ARCH_REQUIRE_GPIOLIB
733 select CLKSRC_SAMSUNG_PWM
734 select GENERIC_CLOCKEVENTS
736 select HAVE_S3C2410_I2C if I2C
737 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select HAVE_S3C_RTC if RTC_CLASS
739 select MULTI_IRQ_HANDLER
740 select NEED_MACH_IO_H
743 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
744 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
745 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
746 Samsung SMDK2410 development board (and derivatives).
749 bool "Samsung S3C64XX"
750 select ARCH_HAS_CPUFREQ
751 select ARCH_REQUIRE_GPIOLIB
755 select CLKSRC_SAMSUNG_PWM
758 select GENERIC_CLOCKEVENTS
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
765 select PM_GENERIC_DOMAINS
767 select S3C_GPIO_TRACK
769 select SAMSUNG_WAKEMASK
770 select SAMSUNG_WDT_RESET
771 select USB_ARCH_HAS_OHCI
773 Samsung S3C64XX series based systems
776 bool "Samsung S5P6440 S5P6450"
778 select CLKSRC_SAMSUNG_PWM
780 select GENERIC_CLOCKEVENTS
782 select HAVE_S3C2410_I2C if I2C
783 select HAVE_S3C2410_WATCHDOG if WATCHDOG
784 select HAVE_S3C_RTC if RTC_CLASS
785 select NEED_MACH_GPIO_H
787 select SAMSUNG_WDT_RESET
789 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
793 bool "Samsung S5PC100"
794 select ARCH_REQUIRE_GPIOLIB
796 select CLKSRC_SAMSUNG_PWM
798 select GENERIC_CLOCKEVENTS
800 select HAVE_S3C2410_I2C if I2C
801 select HAVE_S3C2410_WATCHDOG if WATCHDOG
802 select HAVE_S3C_RTC if RTC_CLASS
803 select NEED_MACH_GPIO_H
805 select SAMSUNG_WDT_RESET
807 Samsung S5PC100 series based systems
810 bool "Samsung S5PV210/S5PC110"
811 select ARCH_HAS_CPUFREQ
812 select ARCH_HAS_HOLES_MEMORYMODEL
813 select ARCH_SPARSEMEM_ENABLE
815 select CLKSRC_SAMSUNG_PWM
817 select GENERIC_CLOCKEVENTS
819 select HAVE_S3C2410_I2C if I2C
820 select HAVE_S3C2410_WATCHDOG if WATCHDOG
821 select HAVE_S3C_RTC if RTC_CLASS
822 select NEED_MACH_GPIO_H
823 select NEED_MACH_MEMORY_H
826 Samsung S5PV210/S5PC110 series based systems
829 bool "Samsung EXYNOS"
830 select ARCH_HAS_CPUFREQ
831 select ARCH_HAS_HOLES_MEMORYMODEL
832 select ARCH_REQUIRE_GPIOLIB
833 select ARCH_SPARSEMEM_ENABLE
837 select GENERIC_CLOCKEVENTS
838 select HAVE_S3C2410_I2C if I2C
839 select HAVE_S3C2410_WATCHDOG if WATCHDOG
840 select HAVE_S3C_RTC if RTC_CLASS
841 select NEED_MACH_MEMORY_H
845 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
849 select ARCH_HAS_HOLES_MEMORYMODEL
850 select ARCH_REQUIRE_GPIOLIB
852 select GENERIC_ALLOCATOR
853 select GENERIC_CLOCKEVENTS
854 select GENERIC_IRQ_CHIP
860 Support for TI's DaVinci platform.
865 select ARCH_HAS_CPUFREQ
866 select ARCH_HAS_HOLES_MEMORYMODEL
868 select ARCH_REQUIRE_GPIOLIB
871 select GENERIC_CLOCKEVENTS
872 select GENERIC_IRQ_CHIP
875 select NEED_MACH_IO_H if PCCARD
876 select NEED_MACH_MEMORY_H
878 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
882 menu "Multiple platform selection"
883 depends on ARCH_MULTIPLATFORM
885 comment "CPU Core family selection"
887 config ARCH_MULTI_V4T
888 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
889 depends on !ARCH_MULTI_V6_V7
890 select ARCH_MULTI_V4_V5
891 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
892 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
893 CPU_ARM925T || CPU_ARM940T)
896 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
897 depends on !ARCH_MULTI_V6_V7
898 select ARCH_MULTI_V4_V5
899 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
900 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
901 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
903 config ARCH_MULTI_V4_V5
907 bool "ARMv6 based platforms (ARM11)"
908 select ARCH_MULTI_V6_V7
912 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
914 select ARCH_MULTI_V6_V7
917 config ARCH_MULTI_V6_V7
920 config ARCH_MULTI_CPU_AUTO
921 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
927 # This is sorted alphabetically by mach-* pathname. However, plat-*
928 # Kconfigs may be included either alphabetically (according to the
929 # plat- suffix) or along side the corresponding mach-* source.
931 source "arch/arm/mach-mvebu/Kconfig"
933 source "arch/arm/mach-at91/Kconfig"
935 source "arch/arm/mach-bcm/Kconfig"
937 source "arch/arm/mach-bcm2835/Kconfig"
939 source "arch/arm/mach-berlin/Kconfig"
941 source "arch/arm/mach-clps711x/Kconfig"
943 source "arch/arm/mach-cns3xxx/Kconfig"
945 source "arch/arm/mach-davinci/Kconfig"
947 source "arch/arm/mach-dove/Kconfig"
949 source "arch/arm/mach-ep93xx/Kconfig"
951 source "arch/arm/mach-footbridge/Kconfig"
953 source "arch/arm/mach-gemini/Kconfig"
955 source "arch/arm/mach-highbank/Kconfig"
957 source "arch/arm/mach-hisi/Kconfig"
959 source "arch/arm/mach-integrator/Kconfig"
961 source "arch/arm/mach-iop32x/Kconfig"
963 source "arch/arm/mach-iop33x/Kconfig"
965 source "arch/arm/mach-iop13xx/Kconfig"
967 source "arch/arm/mach-ixp4xx/Kconfig"
969 source "arch/arm/mach-keystone/Kconfig"
971 source "arch/arm/mach-kirkwood/Kconfig"
973 source "arch/arm/mach-ks8695/Kconfig"
975 source "arch/arm/mach-msm/Kconfig"
977 source "arch/arm/mach-moxart/Kconfig"
979 source "arch/arm/mach-mv78xx0/Kconfig"
981 source "arch/arm/mach-imx/Kconfig"
983 source "arch/arm/mach-mxs/Kconfig"
985 source "arch/arm/mach-netx/Kconfig"
987 source "arch/arm/mach-nomadik/Kconfig"
989 source "arch/arm/mach-nspire/Kconfig"
991 source "arch/arm/plat-omap/Kconfig"
993 source "arch/arm/mach-omap1/Kconfig"
995 source "arch/arm/mach-omap2/Kconfig"
997 source "arch/arm/mach-orion5x/Kconfig"
999 source "arch/arm/mach-picoxcell/Kconfig"
1001 source "arch/arm/mach-pxa/Kconfig"
1002 source "arch/arm/plat-pxa/Kconfig"
1004 source "arch/arm/mach-mmp/Kconfig"
1006 source "arch/arm/mach-realview/Kconfig"
1008 source "arch/arm/mach-rockchip/Kconfig"
1010 source "arch/arm/mach-sa1100/Kconfig"
1012 source "arch/arm/plat-samsung/Kconfig"
1014 source "arch/arm/mach-socfpga/Kconfig"
1016 source "arch/arm/mach-spear/Kconfig"
1018 source "arch/arm/mach-sti/Kconfig"
1020 source "arch/arm/mach-s3c24xx/Kconfig"
1022 source "arch/arm/mach-s3c64xx/Kconfig"
1024 source "arch/arm/mach-s5p64x0/Kconfig"
1026 source "arch/arm/mach-s5pc100/Kconfig"
1028 source "arch/arm/mach-s5pv210/Kconfig"
1030 source "arch/arm/mach-exynos/Kconfig"
1032 source "arch/arm/mach-shmobile/Kconfig"
1034 source "arch/arm/mach-sunxi/Kconfig"
1036 source "arch/arm/mach-prima2/Kconfig"
1038 source "arch/arm/mach-tegra/Kconfig"
1040 source "arch/arm/mach-u300/Kconfig"
1042 source "arch/arm/mach-ux500/Kconfig"
1044 source "arch/arm/mach-versatile/Kconfig"
1046 source "arch/arm/mach-vexpress/Kconfig"
1047 source "arch/arm/plat-versatile/Kconfig"
1049 source "arch/arm/mach-virt/Kconfig"
1051 source "arch/arm/mach-vt8500/Kconfig"
1053 source "arch/arm/mach-w90x900/Kconfig"
1055 source "arch/arm/mach-zynq/Kconfig"
1057 # Definitions to make life easier
1063 select GENERIC_CLOCKEVENTS
1069 select GENERIC_IRQ_CHIP
1072 config PLAT_ORION_LEGACY
1079 config PLAT_VERSATILE
1082 config ARM_TIMER_SP804
1085 select CLKSRC_OF if OF
1087 source arch/arm/mm/Kconfig
1091 default 16 if ARCH_EP93XX
1095 bool "Enable iWMMXt support" if !CPU_PJ4
1096 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1097 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1099 Enable support for iWMMXt context switching at run time if
1100 running on a CPU that supports it.
1102 config MULTI_IRQ_HANDLER
1105 Allow each machine to specify it's own IRQ handler at run time.
1108 source "arch/arm/Kconfig-nommu"
1111 config PJ4B_ERRATA_4742
1112 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1113 depends on CPU_PJ4B && MACH_ARMADA_370
1116 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1117 Event (WFE) IDLE states, a specific timing sensitivity exists between
1118 the retiring WFI/WFE instructions and the newly issued subsequent
1119 instructions. This sensitivity can result in a CPU hang scenario.
1121 The software must insert either a Data Synchronization Barrier (DSB)
1122 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1125 config ARM_ERRATA_326103
1126 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1129 Executing a SWP instruction to read-only memory does not set bit 11
1130 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1131 treat the access as a read, preventing a COW from occurring and
1132 causing the faulting task to livelock.
1134 config ARM_ERRATA_411920
1135 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1136 depends on CPU_V6 || CPU_V6K
1138 Invalidation of the Instruction Cache operation can
1139 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1140 It does not affect the MPCore. This option enables the ARM Ltd.
1141 recommended workaround.
1143 config ARM_ERRATA_430973
1144 bool "ARM errata: Stale prediction on replaced interworking branch"
1147 This option enables the workaround for the 430973 Cortex-A8
1148 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1149 interworking branch is replaced with another code sequence at the
1150 same virtual address, whether due to self-modifying code or virtual
1151 to physical address re-mapping, Cortex-A8 does not recover from the
1152 stale interworking branch prediction. This results in Cortex-A8
1153 executing the new code sequence in the incorrect ARM or Thumb state.
1154 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1155 and also flushes the branch target cache at every context switch.
1156 Note that setting specific bits in the ACTLR register may not be
1157 available in non-secure mode.
1159 config ARM_ERRATA_458693
1160 bool "ARM errata: Processor deadlock when a false hazard is created"
1162 depends on !ARCH_MULTIPLATFORM
1164 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1165 erratum. For very specific sequences of memory operations, it is
1166 possible for a hazard condition intended for a cache line to instead
1167 be incorrectly associated with a different cache line. This false
1168 hazard might then cause a processor deadlock. The workaround enables
1169 the L1 caching of the NEON accesses and disables the PLD instruction
1170 in the ACTLR register. Note that setting specific bits in the ACTLR
1171 register may not be available in non-secure mode.
1173 config ARM_ERRATA_460075
1174 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1176 depends on !ARCH_MULTIPLATFORM
1178 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1179 erratum. Any asynchronous access to the L2 cache may encounter a
1180 situation in which recent store transactions to the L2 cache are lost
1181 and overwritten with stale memory contents from external memory. The
1182 workaround disables the write-allocate mode for the L2 cache via the
1183 ACTLR register. Note that setting specific bits in the ACTLR register
1184 may not be available in non-secure mode.
1186 config ARM_ERRATA_742230
1187 bool "ARM errata: DMB operation may be faulty"
1188 depends on CPU_V7 && SMP
1189 depends on !ARCH_MULTIPLATFORM
1191 This option enables the workaround for the 742230 Cortex-A9
1192 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1193 between two write operations may not ensure the correct visibility
1194 ordering of the two writes. This workaround sets a specific bit in
1195 the diagnostic register of the Cortex-A9 which causes the DMB
1196 instruction to behave as a DSB, ensuring the correct behaviour of
1199 config ARM_ERRATA_742231
1200 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1201 depends on CPU_V7 && SMP
1202 depends on !ARCH_MULTIPLATFORM
1204 This option enables the workaround for the 742231 Cortex-A9
1205 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1206 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1207 accessing some data located in the same cache line, may get corrupted
1208 data due to bad handling of the address hazard when the line gets
1209 replaced from one of the CPUs at the same time as another CPU is
1210 accessing it. This workaround sets specific bits in the diagnostic
1211 register of the Cortex-A9 which reduces the linefill issuing
1212 capabilities of the processor.
1214 config PL310_ERRATA_588369
1215 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1216 depends on CACHE_L2X0
1218 The PL310 L2 cache controller implements three types of Clean &
1219 Invalidate maintenance operations: by Physical Address
1220 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1221 They are architecturally defined to behave as the execution of a
1222 clean operation followed immediately by an invalidate operation,
1223 both performing to the same memory location. This functionality
1224 is not correctly implemented in PL310 as clean lines are not
1225 invalidated as a result of these operations.
1227 config ARM_ERRATA_643719
1228 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1229 depends on CPU_V7 && SMP
1231 This option enables the workaround for the 643719 Cortex-A9 (prior to
1232 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1233 register returns zero when it should return one. The workaround
1234 corrects this value, ensuring cache maintenance operations which use
1235 it behave as intended and avoiding data corruption.
1237 config ARM_ERRATA_720789
1238 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1241 This option enables the workaround for the 720789 Cortex-A9 (prior to
1242 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1243 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1244 As a consequence of this erratum, some TLB entries which should be
1245 invalidated are not, resulting in an incoherency in the system page
1246 tables. The workaround changes the TLB flushing routines to invalidate
1247 entries regardless of the ASID.
1249 config PL310_ERRATA_727915
1250 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1251 depends on CACHE_L2X0
1253 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1254 operation (offset 0x7FC). This operation runs in background so that
1255 PL310 can handle normal accesses while it is in progress. Under very
1256 rare circumstances, due to this erratum, write data can be lost when
1257 PL310 treats a cacheable write transaction during a Clean &
1258 Invalidate by Way operation.
1260 config ARM_ERRATA_743622
1261 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1263 depends on !ARCH_MULTIPLATFORM
1265 This option enables the workaround for the 743622 Cortex-A9
1266 (r2p*) erratum. Under very rare conditions, a faulty
1267 optimisation in the Cortex-A9 Store Buffer may lead to data
1268 corruption. This workaround sets a specific bit in the diagnostic
1269 register of the Cortex-A9 which disables the Store Buffer
1270 optimisation, preventing the defect from occurring. This has no
1271 visible impact on the overall performance or power consumption of the
1274 config ARM_ERRATA_751472
1275 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1277 depends on !ARCH_MULTIPLATFORM
1279 This option enables the workaround for the 751472 Cortex-A9 (prior
1280 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1281 completion of a following broadcasted operation if the second
1282 operation is received by a CPU before the ICIALLUIS has completed,
1283 potentially leading to corrupted entries in the cache or TLB.
1285 config PL310_ERRATA_753970
1286 bool "PL310 errata: cache sync operation may be faulty"
1287 depends on CACHE_PL310
1289 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1291 Under some condition the effect of cache sync operation on
1292 the store buffer still remains when the operation completes.
1293 This means that the store buffer is always asked to drain and
1294 this prevents it from merging any further writes. The workaround
1295 is to replace the normal offset of cache sync operation (0x730)
1296 by another offset targeting an unmapped PL310 register 0x740.
1297 This has the same effect as the cache sync operation: store buffer
1298 drain and waiting for all buffers empty.
1300 config ARM_ERRATA_754322
1301 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1304 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1305 r3p*) erratum. A speculative memory access may cause a page table walk
1306 which starts prior to an ASID switch but completes afterwards. This
1307 can populate the micro-TLB with a stale entry which may be hit with
1308 the new ASID. This workaround places two dsb instructions in the mm
1309 switching code so that no page table walks can cross the ASID switch.
1311 config ARM_ERRATA_754327
1312 bool "ARM errata: no automatic Store Buffer drain"
1313 depends on CPU_V7 && SMP
1315 This option enables the workaround for the 754327 Cortex-A9 (prior to
1316 r2p0) erratum. The Store Buffer does not have any automatic draining
1317 mechanism and therefore a livelock may occur if an external agent
1318 continuously polls a memory location waiting to observe an update.
1319 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1320 written polling loops from denying visibility of updates to memory.
1322 config ARM_ERRATA_364296
1323 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1326 This options enables the workaround for the 364296 ARM1136
1327 r0p2 erratum (possible cache data corruption with
1328 hit-under-miss enabled). It sets the undocumented bit 31 in
1329 the auxiliary control register and the FI bit in the control
1330 register, thus disabling hit-under-miss without putting the
1331 processor into full low interrupt latency mode. ARM11MPCore
1334 config ARM_ERRATA_764369
1335 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1336 depends on CPU_V7 && SMP
1338 This option enables the workaround for erratum 764369
1339 affecting Cortex-A9 MPCore with two or more processors (all
1340 current revisions). Under certain timing circumstances, a data
1341 cache line maintenance operation by MVA targeting an Inner
1342 Shareable memory region may fail to proceed up to either the
1343 Point of Coherency or to the Point of Unification of the
1344 system. This workaround adds a DSB instruction before the
1345 relevant cache maintenance functions and sets a specific bit
1346 in the diagnostic control register of the SCU.
1348 config PL310_ERRATA_769419
1349 bool "PL310 errata: no automatic Store Buffer drain"
1350 depends on CACHE_L2X0
1352 On revisions of the PL310 prior to r3p2, the Store Buffer does
1353 not automatically drain. This can cause normal, non-cacheable
1354 writes to be retained when the memory system is idle, leading
1355 to suboptimal I/O performance for drivers using coherent DMA.
1356 This option adds a write barrier to the cpu_idle loop so that,
1357 on systems with an outer cache, the store buffer is drained
1360 config ARM_ERRATA_775420
1361 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1364 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1365 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1366 operation aborts with MMU exception, it might cause the processor
1367 to deadlock. This workaround puts DSB before executing ISB if
1368 an abort may occur on cache maintenance.
1370 config ARM_ERRATA_798181
1371 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1372 depends on CPU_V7 && SMP
1374 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1375 adequately shooting down all use of the old entries. This
1376 option enables the Linux kernel workaround for this erratum
1377 which sends an IPI to the CPUs that are running the same ASID
1378 as the one being invalidated.
1380 config ARM_ERRATA_773022
1381 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1384 This option enables the workaround for the 773022 Cortex-A15
1385 (up to r0p4) erratum. In certain rare sequences of code, the
1386 loop buffer may deliver incorrect instructions. This
1387 workaround disables the loop buffer to avoid the erratum.
1391 source "arch/arm/common/Kconfig"
1401 Find out whether you have ISA slots on your motherboard. ISA is the
1402 name of a bus system, i.e. the way the CPU talks to the other stuff
1403 inside your box. Other bus systems are PCI, EISA, MicroChannel
1404 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1405 newer boards don't support it. If you have ISA, say Y, otherwise N.
1407 # Select ISA DMA controller support
1412 # Select ISA DMA interface
1417 bool "PCI support" if MIGHT_HAVE_PCI
1419 Find out whether you have a PCI motherboard. PCI is the name of a
1420 bus system, i.e. the way the CPU talks to the other stuff inside
1421 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1422 VESA. If you have PCI, say Y, otherwise N.
1428 config PCI_NANOENGINE
1429 bool "BSE nanoEngine PCI support"
1430 depends on SA1100_NANOENGINE
1432 Enable PCI on the BSE nanoEngine board.
1437 config PCI_HOST_ITE8152
1439 depends on PCI && MACH_ARMCORE
1443 source "drivers/pci/Kconfig"
1444 source "drivers/pci/pcie/Kconfig"
1446 source "drivers/pcmcia/Kconfig"
1450 menu "Kernel Features"
1455 This option should be selected by machines which have an SMP-
1458 The only effect of this option is to make the SMP-related
1459 options available to the user for configuration.
1462 bool "Symmetric Multi-Processing"
1463 depends on CPU_V6K || CPU_V7
1464 depends on GENERIC_CLOCKEVENTS
1466 depends on MMU || ARM_MPU
1468 This enables support for systems with more than one CPU. If you have
1469 a system with only one CPU, like most personal computers, say N. If
1470 you have a system with more than one CPU, say Y.
1472 If you say N here, the kernel will run on single and multiprocessor
1473 machines, but will use only one CPU of a multiprocessor machine. If
1474 you say Y here, the kernel will run on many, but not all, single
1475 processor machines. On a single processor machine, the kernel will
1476 run faster if you say N here.
1478 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1479 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1480 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1482 If you don't know what to do here, say N.
1485 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1486 depends on SMP && !XIP_KERNEL && MMU
1489 SMP kernels contain instructions which fail on non-SMP processors.
1490 Enabling this option allows the kernel to modify itself to make
1491 these instructions safe. Disabling it allows about 1K of space
1494 If you don't know what to do here, say Y.
1496 config ARM_CPU_TOPOLOGY
1497 bool "Support cpu topology definition"
1498 depends on SMP && CPU_V7
1501 Support ARM cpu topology definition. The MPIDR register defines
1502 affinity between processors which is then used to describe the cpu
1503 topology of an ARM System.
1506 bool "Multi-core scheduler support"
1507 depends on ARM_CPU_TOPOLOGY
1509 Multi-core scheduler support improves the CPU scheduler's decision
1510 making when dealing with multi-core CPU chips at a cost of slightly
1511 increased overhead in some places. If unsure say N here.
1514 bool "SMT scheduler support"
1515 depends on ARM_CPU_TOPOLOGY
1517 Improves the CPU scheduler's decision making when dealing with
1518 MultiThreading at a cost of slightly increased overhead in some
1519 places. If unsure say N here.
1524 This option enables support for the ARM system coherency unit
1526 config HAVE_ARM_ARCH_TIMER
1527 bool "Architected timer support"
1529 select ARM_ARCH_TIMER
1530 select GENERIC_CLOCKEVENTS
1532 This option enables support for the ARM architected timer
1537 select CLKSRC_OF if OF
1539 This options enables support for the ARM timer and watchdog unit
1542 bool "Multi-Cluster Power Management"
1543 depends on CPU_V7 && SMP
1545 This option provides the common power management infrastructure
1546 for (multi-)cluster based systems, such as big.LITTLE based
1550 bool "big.LITTLE support (Experimental)"
1551 depends on CPU_V7 && SMP
1554 This option enables support selections for the big.LITTLE
1555 system architecture.
1558 bool "big.LITTLE switcher support"
1559 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1561 select ARM_CPU_SUSPEND
1563 The big.LITTLE "switcher" provides the core functionality to
1564 transparently handle transition between a cluster of A15's
1565 and a cluster of A7's in a big.LITTLE system.
1567 config BL_SWITCHER_DUMMY_IF
1568 tristate "Simple big.LITTLE switcher user interface"
1569 depends on BL_SWITCHER && DEBUG_KERNEL
1571 This is a simple and dummy char dev interface to control
1572 the big.LITTLE switcher core code. It is meant for
1573 debugging purposes only.
1576 prompt "Memory split"
1579 Select the desired split between kernel and user memory.
1581 If you are not absolutely sure what you are doing, leave this
1585 bool "3G/1G user/kernel split"
1587 bool "2G/2G user/kernel split"
1589 bool "1G/3G user/kernel split"
1594 default 0x40000000 if VMSPLIT_1G
1595 default 0x80000000 if VMSPLIT_2G
1599 int "Maximum number of CPUs (2-32)"
1605 bool "Support for hot-pluggable CPUs"
1608 Say Y here to experiment with turning CPUs off and on. CPUs
1609 can be controlled through /sys/devices/system/cpu.
1612 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1615 Say Y here if you want Linux to communicate with system firmware
1616 implementing the PSCI specification for CPU-centric power
1617 management operations described in ARM document number ARM DEN
1618 0022A ("Power State Coordination Interface System Software on
1621 # The GPIO number here must be sorted by descending number. In case of
1622 # a multiplatform kernel, we just want the highest value required by the
1623 # selected platforms.
1626 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1627 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX
1628 default 392 if ARCH_U8500
1629 default 352 if ARCH_VT8500
1630 default 288 if ARCH_SUNXI
1631 default 264 if MACH_H4700
1634 Maximum number of GPIOs in the system.
1636 If unsure, leave the default value.
1638 source kernel/Kconfig.preempt
1642 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1643 ARCH_S5PV210 || ARCH_EXYNOS4
1644 default AT91_TIMER_HZ if ARCH_AT91
1645 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1649 depends on HZ_FIXED = 0
1650 prompt "Timer frequency"
1674 default HZ_FIXED if HZ_FIXED != 0
1675 default 100 if HZ_100
1676 default 200 if HZ_200
1677 default 250 if HZ_250
1678 default 300 if HZ_300
1679 default 500 if HZ_500
1683 def_bool HIGH_RES_TIMERS
1685 config THUMB2_KERNEL
1686 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1687 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1688 default y if CPU_THUMBONLY
1690 select ARM_ASM_UNIFIED
1693 By enabling this option, the kernel will be compiled in
1694 Thumb-2 mode. A compiler/assembler that understand the unified
1695 ARM-Thumb syntax is needed.
1699 config THUMB2_AVOID_R_ARM_THM_JUMP11
1700 bool "Work around buggy Thumb-2 short branch relocations in gas"
1701 depends on THUMB2_KERNEL && MODULES
1704 Various binutils versions can resolve Thumb-2 branches to
1705 locally-defined, preemptible global symbols as short-range "b.n"
1706 branch instructions.
1708 This is a problem, because there's no guarantee the final
1709 destination of the symbol, or any candidate locations for a
1710 trampoline, are within range of the branch. For this reason, the
1711 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1712 relocation in modules at all, and it makes little sense to add
1715 The symptom is that the kernel fails with an "unsupported
1716 relocation" error when loading some modules.
1718 Until fixed tools are available, passing
1719 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1720 code which hits this problem, at the cost of a bit of extra runtime
1721 stack usage in some cases.
1723 The problem is described in more detail at:
1724 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1726 Only Thumb-2 kernels are affected.
1728 Unless you are sure your tools don't have this problem, say Y.
1730 config ARM_ASM_UNIFIED
1734 bool "Use the ARM EABI to compile the kernel"
1736 This option allows for the kernel to be compiled using the latest
1737 ARM ABI (aka EABI). This is only useful if you are using a user
1738 space environment that is also compiled with EABI.
1740 Since there are major incompatibilities between the legacy ABI and
1741 EABI, especially with regard to structure member alignment, this
1742 option also changes the kernel syscall calling convention to
1743 disambiguate both ABIs and allow for backward compatibility support
1744 (selected with CONFIG_OABI_COMPAT).
1746 To use this you need GCC version 4.0.0 or later.
1749 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1750 depends on AEABI && !THUMB2_KERNEL
1752 This option preserves the old syscall interface along with the
1753 new (ARM EABI) one. It also provides a compatibility layer to
1754 intercept syscalls that have structure arguments which layout
1755 in memory differs between the legacy ABI and the new ARM EABI
1756 (only for non "thumb" binaries). This option adds a tiny
1757 overhead to all syscalls and produces a slightly larger kernel.
1759 The seccomp filter system will not be available when this is
1760 selected, since there is no way yet to sensibly distinguish
1761 between calling conventions during filtering.
1763 If you know you'll be using only pure EABI user space then you
1764 can say N here. If this option is not selected and you attempt
1765 to execute a legacy ABI binary then the result will be
1766 UNPREDICTABLE (in fact it can be predicted that it won't work
1767 at all). If in doubt say N.
1769 config ARCH_HAS_HOLES_MEMORYMODEL
1772 config ARCH_SPARSEMEM_ENABLE
1775 config ARCH_SPARSEMEM_DEFAULT
1776 def_bool ARCH_SPARSEMEM_ENABLE
1778 config ARCH_SELECT_MEMORY_MODEL
1779 def_bool ARCH_SPARSEMEM_ENABLE
1781 config HAVE_ARCH_PFN_VALID
1782 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1785 bool "High Memory Support"
1788 The address space of ARM processors is only 4 Gigabytes large
1789 and it has to accommodate user address space, kernel address
1790 space as well as some memory mapped IO. That means that, if you
1791 have a large amount of physical memory and/or IO, not all of the
1792 memory can be "permanently mapped" by the kernel. The physical
1793 memory that is not permanently mapped is called "high memory".
1795 Depending on the selected kernel/user memory split, minimum
1796 vmalloc space and actual amount of RAM, you may not need this
1797 option which should result in a slightly faster kernel.
1802 bool "Allocate 2nd-level pagetables from highmem"
1805 config HW_PERF_EVENTS
1806 bool "Enable hardware performance counter support for perf events"
1807 depends on PERF_EVENTS
1810 Enable hardware performance counter support for perf events. If
1811 disabled, perf events will use software events only.
1813 config SYS_SUPPORTS_HUGETLBFS
1817 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1821 config ARCH_WANT_GENERAL_HUGETLB
1826 config FORCE_MAX_ZONEORDER
1827 int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1828 range 11 64 if ARCH_SHMOBILE_LEGACY
1829 default "12" if SOC_AM33XX
1830 default "9" if SA1111 || ARCH_EFM32
1833 The kernel memory allocator divides physically contiguous memory
1834 blocks into "zones", where each zone is a power of two number of
1835 pages. This option selects the largest power of two that the kernel
1836 keeps in the memory allocator. If you need to allocate very large
1837 blocks of physically contiguous memory, then you may need to
1838 increase this value.
1840 This config option is actually maximum order plus one. For example,
1841 a value of 11 means that the largest free memory block is 2^10 pages.
1843 config ALIGNMENT_TRAP
1845 depends on CPU_CP15_MMU
1846 default y if !ARCH_EBSA110
1847 select HAVE_PROC_CPU if PROC_FS
1849 ARM processors cannot fetch/store information which is not
1850 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1851 address divisible by 4. On 32-bit ARM processors, these non-aligned
1852 fetch/store instructions will be emulated in software if you say
1853 here, which has a severe performance impact. This is necessary for
1854 correct operation of some network protocols. With an IP-only
1855 configuration it is safe to say N, otherwise say Y.
1857 config UACCESS_WITH_MEMCPY
1858 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1860 default y if CPU_FEROCEON
1862 Implement faster copy_to_user and clear_user methods for CPU
1863 cores where a 8-word STM instruction give significantly higher
1864 memory write throughput than a sequence of individual 32bit stores.
1866 A possible side effect is a slight increase in scheduling latency
1867 between threads sharing the same address space if they invoke
1868 such copy operations with large buffers.
1870 However, if the CPU data cache is using a write-allocate mode,
1871 this option is unlikely to provide any performance gain.
1875 prompt "Enable seccomp to safely compute untrusted bytecode"
1877 This kernel feature is useful for number crunching applications
1878 that may need to compute untrusted bytecode during their
1879 execution. By using pipes or other transports made available to
1880 the process as file descriptors supporting the read/write
1881 syscalls, it's possible to isolate those applications in
1882 their own address space using seccomp. Once seccomp is
1883 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1884 and the task is only allowed to execute a few safe syscalls
1885 defined by each seccomp mode.
1898 bool "Xen guest support on ARM (EXPERIMENTAL)"
1899 depends on ARM && AEABI && OF
1900 depends on CPU_V7 && !CPU_V6
1901 depends on !GENERIC_ATOMIC64
1905 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1912 bool "Flattened Device Tree support"
1915 select OF_EARLY_FLATTREE
1917 Include support for flattened device tree machine descriptions.
1920 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1923 This is the traditional way of passing data to the kernel at boot
1924 time. If you are solely relying on the flattened device tree (or
1925 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1926 to remove ATAGS support from your kernel binary. If unsure,
1929 config DEPRECATED_PARAM_STRUCT
1930 bool "Provide old way to pass kernel parameters"
1933 This was deprecated in 2001 and announced to live on for 5 years.
1934 Some old boot loaders still use this way.
1936 # Compressed boot loader in ROM. Yes, we really want to ask about
1937 # TEXT and BSS so we preserve their values in the config files.
1938 config ZBOOT_ROM_TEXT
1939 hex "Compressed ROM boot loader base address"
1942 The physical address at which the ROM-able zImage is to be
1943 placed in the target. Platforms which normally make use of
1944 ROM-able zImage formats normally set this to a suitable
1945 value in their defconfig file.
1947 If ZBOOT_ROM is not enabled, this has no effect.
1949 config ZBOOT_ROM_BSS
1950 hex "Compressed ROM boot loader BSS address"
1953 The base address of an area of read/write memory in the target
1954 for the ROM-able zImage which must be available while the
1955 decompressor is running. It must be large enough to hold the
1956 entire decompressed kernel plus an additional 128 KiB.
1957 Platforms which normally make use of ROM-able zImage formats
1958 normally set this to a suitable value in their defconfig file.
1960 If ZBOOT_ROM is not enabled, this has no effect.
1963 bool "Compressed boot loader in ROM/flash"
1964 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1965 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1967 Say Y here if you intend to execute your compressed kernel image
1968 (zImage) directly from ROM or flash. If unsure, say N.
1971 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1972 depends on ZBOOT_ROM && ARCH_SH7372
1973 default ZBOOT_ROM_NONE
1975 Include experimental SD/MMC loading code in the ROM-able zImage.
1976 With this enabled it is possible to write the ROM-able zImage
1977 kernel image to an MMC or SD card and boot the kernel straight
1978 from the reset vector. At reset the processor Mask ROM will load
1979 the first part of the ROM-able zImage which in turn loads the
1980 rest the kernel image to RAM.
1982 config ZBOOT_ROM_NONE
1983 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1985 Do not load image from SD or MMC
1987 config ZBOOT_ROM_MMCIF
1988 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1990 Load image from MMCIF hardware block.
1992 config ZBOOT_ROM_SH_MOBILE_SDHI
1993 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1995 Load image from SDHI hardware block
1999 config ARM_APPENDED_DTB
2000 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2003 With this option, the boot code will look for a device tree binary
2004 (DTB) appended to zImage
2005 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2007 This is meant as a backward compatibility convenience for those
2008 systems with a bootloader that can't be upgraded to accommodate
2009 the documented boot protocol using a device tree.
2011 Beware that there is very little in terms of protection against
2012 this option being confused by leftover garbage in memory that might
2013 look like a DTB header after a reboot if no actual DTB is appended
2014 to zImage. Do not leave this option active in a production kernel
2015 if you don't intend to always append a DTB. Proper passing of the
2016 location into r2 of a bootloader provided DTB is always preferable
2019 config ARM_ATAG_DTB_COMPAT
2020 bool "Supplement the appended DTB with traditional ATAG information"
2021 depends on ARM_APPENDED_DTB
2023 Some old bootloaders can't be updated to a DTB capable one, yet
2024 they provide ATAGs with memory configuration, the ramdisk address,
2025 the kernel cmdline string, etc. Such information is dynamically
2026 provided by the bootloader and can't always be stored in a static
2027 DTB. To allow a device tree enabled kernel to be used with such
2028 bootloaders, this option allows zImage to extract the information
2029 from the ATAG list and store it at run time into the appended DTB.
2032 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2033 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2035 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2036 bool "Use bootloader kernel arguments if available"
2038 Uses the command-line options passed by the boot loader instead of
2039 the device tree bootargs property. If the boot loader doesn't provide
2040 any, the device tree bootargs property will be used.
2042 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2043 bool "Extend with bootloader kernel arguments"
2045 The command-line arguments provided by the boot loader will be
2046 appended to the the device tree bootargs property.
2051 string "Default kernel command string"
2054 On some architectures (EBSA110 and CATS), there is currently no way
2055 for the boot loader to pass arguments to the kernel. For these
2056 architectures, you should supply some command-line options at build
2057 time by entering them here. As a minimum, you should specify the
2058 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2061 prompt "Kernel command line type" if CMDLINE != ""
2062 default CMDLINE_FROM_BOOTLOADER
2065 config CMDLINE_FROM_BOOTLOADER
2066 bool "Use bootloader kernel arguments if available"
2068 Uses the command-line options passed by the boot loader. If
2069 the boot loader doesn't provide any, the default kernel command
2070 string provided in CMDLINE will be used.
2072 config CMDLINE_EXTEND
2073 bool "Extend bootloader kernel arguments"
2075 The command-line arguments provided by the boot loader will be
2076 appended to the default kernel command string.
2078 config CMDLINE_FORCE
2079 bool "Always use the default kernel command string"
2081 Always use the default kernel command string, even if the boot
2082 loader passes other arguments to the kernel.
2083 This is useful if you cannot or don't want to change the
2084 command-line options your boot loader passes to the kernel.
2088 bool "Kernel Execute-In-Place from ROM"
2089 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2091 Execute-In-Place allows the kernel to run from non-volatile storage
2092 directly addressable by the CPU, such as NOR flash. This saves RAM
2093 space since the text section of the kernel is not loaded from flash
2094 to RAM. Read-write sections, such as the data section and stack,
2095 are still copied to RAM. The XIP kernel is not compressed since
2096 it has to run directly from flash, so it will take more space to
2097 store it. The flash address used to link the kernel object files,
2098 and for storing it, is configuration dependent. Therefore, if you
2099 say Y here, you must know the proper physical address where to
2100 store the kernel image depending on your own flash memory usage.
2102 Also note that the make target becomes "make xipImage" rather than
2103 "make zImage" or "make Image". The final kernel binary to put in
2104 ROM memory will be arch/arm/boot/xipImage.
2108 config XIP_PHYS_ADDR
2109 hex "XIP Kernel Physical Location"
2110 depends on XIP_KERNEL
2111 default "0x00080000"
2113 This is the physical address in your flash memory the kernel will
2114 be linked for and stored to. This address is dependent on your
2118 bool "Kexec system call (EXPERIMENTAL)"
2119 depends on (!SMP || PM_SLEEP_SMP)
2121 kexec is a system call that implements the ability to shutdown your
2122 current kernel, and to start another kernel. It is like a reboot
2123 but it is independent of the system firmware. And like a reboot
2124 you can start any kernel with it, not just Linux.
2126 It is an ongoing process to be certain the hardware in a machine
2127 is properly shutdown, so do not be surprised if this code does not
2128 initially work for you.
2131 bool "Export atags in procfs"
2132 depends on ATAGS && KEXEC
2135 Should the atags used to boot the kernel be exported in an "atags"
2136 file in procfs. Useful with kexec.
2139 bool "Build kdump crash kernel (EXPERIMENTAL)"
2141 Generate crash dump after being started by kexec. This should
2142 be normally only set in special crash dump kernels which are
2143 loaded in the main kernel with kexec-tools into a specially
2144 reserved region and then later executed after a crash by
2145 kdump/kexec. The crash dump kernel must be compiled to a
2146 memory address not used by the main kernel
2148 For more details see Documentation/kdump/kdump.txt
2150 config AUTO_ZRELADDR
2151 bool "Auto calculation of the decompressed kernel image address"
2153 ZRELADDR is the physical address where the decompressed kernel
2154 image will be placed. If AUTO_ZRELADDR is selected, the address
2155 will be determined at run-time by masking the current IP with
2156 0xf8000000. This assumes the zImage being placed in the first 128MB
2157 from start of memory.
2161 menu "CPU Power Management"
2164 source "drivers/cpufreq/Kconfig"
2167 source "drivers/cpuidle/Kconfig"
2171 menu "Floating point emulation"
2173 comment "At least one emulation must be selected"
2176 bool "NWFPE math emulation"
2177 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2179 Say Y to include the NWFPE floating point emulator in the kernel.
2180 This is necessary to run most binaries. Linux does not currently
2181 support floating point hardware so you need to say Y here even if
2182 your machine has an FPA or floating point co-processor podule.
2184 You may say N here if you are going to load the Acorn FPEmulator
2185 early in the bootup.
2188 bool "Support extended precision"
2189 depends on FPE_NWFPE
2191 Say Y to include 80-bit support in the kernel floating-point
2192 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2193 Note that gcc does not generate 80-bit operations by default,
2194 so in most cases this option only enlarges the size of the
2195 floating point emulator without any good reason.
2197 You almost surely want to say N here.
2200 bool "FastFPE math emulation (EXPERIMENTAL)"
2201 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2203 Say Y here to include the FAST floating point emulator in the kernel.
2204 This is an experimental much faster emulator which now also has full
2205 precision for the mantissa. It does not support any exceptions.
2206 It is very simple, and approximately 3-6 times faster than NWFPE.
2208 It should be sufficient for most programs. It may be not suitable
2209 for scientific calculations, but you have to check this for yourself.
2210 If you do not feel you need a faster FP emulation you should better
2214 bool "VFP-format floating point maths"
2215 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2217 Say Y to include VFP support code in the kernel. This is needed
2218 if your hardware includes a VFP unit.
2220 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2221 release notes and additional status information.
2223 Say N if your target does not have VFP hardware.
2231 bool "Advanced SIMD (NEON) Extension support"
2232 depends on VFPv3 && CPU_V7
2234 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2237 config KERNEL_MODE_NEON
2238 bool "Support for NEON in kernel mode"
2239 depends on NEON && AEABI
2241 Say Y to include support for NEON in kernel mode.
2245 menu "Userspace binary formats"
2247 source "fs/Kconfig.binfmt"
2250 tristate "RISC OS personality"
2253 Say Y here to include the kernel code necessary if you want to run
2254 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2255 experimental; if this sounds frightening, say N and sleep in peace.
2256 You can also say M here to compile this support as a module (which
2257 will be called arthur).
2261 menu "Power management options"
2263 source "kernel/power/Kconfig"
2265 config ARCH_SUSPEND_POSSIBLE
2266 depends on !ARCH_S5PC100
2267 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2268 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2271 config ARM_CPU_SUSPEND
2276 source "net/Kconfig"
2278 source "drivers/Kconfig"
2282 source "arch/arm/Kconfig.debug"
2284 source "security/Kconfig"
2286 source "crypto/Kconfig"
2288 source "lib/Kconfig"
2290 source "arch/arm/kvm/Kconfig"