4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_TRACEHOOK
32 select HAVE_CONTEXT_TRACKING
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_DEBUG_KMEMLEAK
35 select HAVE_DMA_API_DEBUG
37 select HAVE_DMA_CONTIGUOUS if MMU
38 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
39 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
40 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
41 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
42 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
43 select HAVE_GENERIC_DMA_COHERENT
44 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
45 select HAVE_IDE if PCI || ISA || PCMCIA
46 select HAVE_IRQ_TIME_ACCOUNTING
47 select HAVE_KERNEL_GZIP
48 select HAVE_KERNEL_LZ4
49 select HAVE_KERNEL_LZMA
50 select HAVE_KERNEL_LZO
52 select HAVE_KPROBES if !XIP_KERNEL
53 select HAVE_KRETPROBES if (HAVE_KPROBES)
55 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
56 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
57 select HAVE_PERF_EVENTS
59 select HAVE_PERF_USER_STACK_DUMP
60 select HAVE_REGS_AND_STACK_ACCESS_API
61 select HAVE_SYSCALL_TRACEPOINTS
63 select HAVE_VIRT_CPU_ACCOUNTING_GEN
64 select IRQ_FORCED_THREADING
66 select MODULES_USE_ELF_REL
69 select OLD_SIGSUSPEND3
70 select PERF_USE_VMALLOC
72 select SYS_SUPPORTS_APM_EMULATION
73 # Above selects are sorted alphabetically; please add new ones
74 # according to that. Thanks.
76 The ARM series is a line of low-power-consumption RISC chip designs
77 licensed by ARM Ltd and targeted at embedded applications and
78 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
79 manufactured, but legacy ARM-based PC hardware remains popular in
80 Europe. There is an ARM Linux project with a web page at
81 <http://www.arm.linux.org.uk/>.
83 config ARM_HAS_SG_CHAIN
86 config NEED_SG_DMA_LENGTH
89 config ARM_DMA_USE_IOMMU
91 select ARM_HAS_SG_CHAIN
92 select NEED_SG_DMA_LENGTH
96 config ARM_DMA_IOMMU_ALIGNMENT
97 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
101 DMA mapping framework by default aligns all buffers to the smallest
102 PAGE_SIZE order which is greater than or equal to the requested buffer
103 size. This works well for buffers up to a few hundreds kilobytes, but
104 for larger buffers it just a waste of address space. Drivers which has
105 relatively small addressing window (like 64Mib) might run out of
106 virtual space with just a few allocations.
108 With this parameter you can specify the maximum PAGE_SIZE order for
109 DMA IOMMU buffers. Larger buffers will be aligned only to this
110 specified order. The order is expressed as a power of two multiplied
118 config MIGHT_HAVE_PCI
121 config SYS_SUPPORTS_APM_EMULATION
126 select GENERIC_ALLOCATOR
137 The Extended Industry Standard Architecture (EISA) bus was
138 developed as an open alternative to the IBM MicroChannel bus.
140 The EISA bus provided some of the features of the IBM MicroChannel
141 bus while maintaining backward compatibility with cards made for
142 the older ISA bus. The EISA bus saw limited use between 1988 and
143 1995 when it was made obsolete by the PCI bus.
145 Say Y here if you are building a kernel for an EISA-based machine.
152 config STACKTRACE_SUPPORT
156 config HAVE_LATENCYTOP_SUPPORT
161 config LOCKDEP_SUPPORT
165 config TRACE_IRQFLAGS_SUPPORT
169 config RWSEM_GENERIC_SPINLOCK
173 config RWSEM_XCHGADD_ALGORITHM
176 config ARCH_HAS_ILOG2_U32
179 config ARCH_HAS_ILOG2_U64
182 config ARCH_HAS_CPUFREQ
185 Internal node to signify that the ARCH has CPUFREQ support
186 and that the relevant menu configurations are displayed for
189 config ARCH_HAS_BANDGAP
192 config GENERIC_HWEIGHT
196 config GENERIC_CALIBRATE_DELAY
200 config ARCH_MAY_HAVE_PC_FDC
206 config NEED_DMA_MAP_STATE
209 config ARCH_HAS_DMA_SET_COHERENT_MASK
212 config GENERIC_ISA_DMA
218 config NEED_RET_TO_USER
226 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
227 default DRAM_BASE if REMAP_VECTORS_TO_RAM
230 The base address of exception vectors. This must be two pages
233 config ARM_PATCH_PHYS_VIRT
234 bool "Patch physical to virtual translations at runtime" if EMBEDDED
236 depends on !XIP_KERNEL && MMU
237 depends on !ARCH_REALVIEW || !SPARSEMEM
239 Patch phys-to-virt and virt-to-phys translation functions at
240 boot and module load time according to the position of the
241 kernel in system memory.
243 This can only be used with non-XIP MMU kernels where the base
244 of physical memory is at a 16MB boundary.
246 Only disable this option if you know that you do not require
247 this feature (eg, building a kernel for a single machine) and
248 you need to shrink the kernel to the minimal size.
250 config NEED_MACH_GPIO_H
253 Select this when mach/gpio.h is required to provide special
254 definitions for this platform. The need for mach/gpio.h should
255 be avoided when possible.
257 config NEED_MACH_IO_H
260 Select this when mach/io.h is required to provide special
261 definitions for this platform. The need for mach/io.h should
262 be avoided when possible.
264 config NEED_MACH_MEMORY_H
267 Select this when mach/memory.h is required to provide special
268 definitions for this platform. The need for mach/memory.h should
269 be avoided when possible.
272 hex "Physical address of main memory" if MMU
273 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
274 default DRAM_BASE if !MMU
276 Please provide the physical address corresponding to the
277 location of main memory in your system.
283 source "init/Kconfig"
285 source "kernel/Kconfig.freezer"
290 bool "MMU-based Paged Memory Management Support"
293 Select if you want MMU-based virtualised addressing space
294 support by paged memory management. If unsure, say 'Y'.
297 # The "ARM system type" choice list is ordered alphabetically by option
298 # text. Please add new entries in the option alphabetic order.
301 prompt "ARM system type"
302 default ARCH_VERSATILE if !MMU
303 default ARCH_MULTIPLATFORM if MMU
305 config ARCH_MULTIPLATFORM
306 bool "Allow multiple platforms to be selected"
308 select ARM_PATCH_PHYS_VIRT
311 select MULTI_IRQ_HANDLER
315 config ARCH_INTEGRATOR
316 bool "ARM Ltd. Integrator family"
317 select ARCH_HAS_CPUFREQ
320 select COMMON_CLK_VERSATILE
321 select GENERIC_CLOCKEVENTS
324 select MULTI_IRQ_HANDLER
325 select NEED_MACH_MEMORY_H
326 select PLAT_VERSATILE
329 select VERSATILE_FPGA_IRQ
331 Support for ARM's Integrator platform.
334 bool "ARM Ltd. RealView family"
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 select ARM_TIMER_SP804
339 select COMMON_CLK_VERSATILE
340 select GENERIC_CLOCKEVENTS
341 select GPIO_PL061 if GPIOLIB
343 select NEED_MACH_MEMORY_H
344 select PLAT_VERSATILE
345 select PLAT_VERSATILE_CLCD
347 This enables support for ARM Ltd RealView boards.
349 config ARCH_VERSATILE
350 bool "ARM Ltd. Versatile family"
351 select ARCH_WANT_OPTIONAL_GPIOLIB
353 select ARM_TIMER_SP804
356 select GENERIC_CLOCKEVENTS
357 select HAVE_MACH_CLKDEV
359 select PLAT_VERSATILE
360 select PLAT_VERSATILE_CLCD
361 select PLAT_VERSATILE_CLOCK
362 select VERSATILE_FPGA_IRQ
364 This enables support for ARM Ltd Versatile board.
368 select ARCH_REQUIRE_GPIOLIB
371 select NEED_MACH_GPIO_H
372 select NEED_MACH_IO_H if PCCARD
374 select PINCTRL_AT91 if USE_OF
376 This enables support for systems based on Atmel
377 AT91RM9200 and AT91SAM9* processors.
380 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
381 select ARCH_REQUIRE_GPIOLIB
386 select GENERIC_CLOCKEVENTS
388 select MULTI_IRQ_HANDLER
391 Support for Cirrus Logic 711x/721x/731x based boards.
394 bool "Cortina Systems Gemini"
395 select ARCH_REQUIRE_GPIOLIB
398 select GENERIC_CLOCKEVENTS
400 Support for the Cortina Systems Gemini family SoCs
404 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
411 This is an evaluation board for the StrongARM processor available
412 from Digital. It has limited hardware on-board, including an
413 Ethernet interface, two PCMCIA sockets, two serial ports and a
418 select ARCH_HAS_HOLES_MEMORYMODEL
419 select ARCH_REQUIRE_GPIOLIB
420 select ARCH_USES_GETTIMEOFFSET
425 select NEED_MACH_MEMORY_H
427 This enables support for the Cirrus EP93xx series of CPUs.
429 config ARCH_FOOTBRIDGE
433 select GENERIC_CLOCKEVENTS
435 select NEED_MACH_IO_H if !MMU
436 select NEED_MACH_MEMORY_H
438 Support for systems based on the DC21285 companion chip
439 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
442 bool "Hilscher NetX based"
446 select GENERIC_CLOCKEVENTS
448 This enables support for systems based on the Hilscher NetX Soc
454 select NEED_MACH_MEMORY_H
455 select NEED_RET_TO_USER
460 Support for Intel's IOP13XX (XScale) family of processors.
465 select ARCH_REQUIRE_GPIOLIB
468 select NEED_RET_TO_USER
472 Support for Intel's 80219 and IOP32X (XScale) family of
478 select ARCH_REQUIRE_GPIOLIB
481 select NEED_RET_TO_USER
485 Support for Intel's IOP33X (XScale) family of processors.
490 select ARCH_HAS_DMA_SET_COHERENT_MASK
491 select ARCH_SUPPORTS_BIG_ENDIAN
492 select ARCH_REQUIRE_GPIOLIB
495 select DMABOUNCE if PCI
496 select GENERIC_CLOCKEVENTS
497 select MIGHT_HAVE_PCI
498 select NEED_MACH_IO_H
499 select USB_EHCI_BIG_ENDIAN_DESC
500 select USB_EHCI_BIG_ENDIAN_MMIO
502 Support for Intel's IXP4XX (XScale) family of processors.
506 select ARCH_REQUIRE_GPIOLIB
508 select GENERIC_CLOCKEVENTS
509 select MIGHT_HAVE_PCI
513 select PLAT_ORION_LEGACY
514 select USB_ARCH_HAS_EHCI
516 Support for the Marvell Dove SoC 88AP510
519 bool "Marvell Kirkwood"
520 select ARCH_HAS_CPUFREQ
521 select ARCH_REQUIRE_GPIOLIB
523 select GENERIC_CLOCKEVENTS
528 select PINCTRL_KIRKWOOD
529 select PLAT_ORION_LEGACY
531 Support for the following Marvell Kirkwood series SoCs:
532 88F6180, 88F6192 and 88F6281.
535 bool "Marvell MV78xx0"
536 select ARCH_REQUIRE_GPIOLIB
538 select GENERIC_CLOCKEVENTS
541 select PLAT_ORION_LEGACY
543 Support for the following Marvell MV78xx0 series SoCs:
549 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
554 select PLAT_ORION_LEGACY
556 Support for the following Marvell Orion 5x series SoCs:
557 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
558 Orion-2 (5281), Orion-1-90 (6183).
561 bool "Marvell PXA168/910/MMP2"
563 select ARCH_REQUIRE_GPIOLIB
565 select GENERIC_ALLOCATOR
566 select GENERIC_CLOCKEVENTS
569 select MULTI_IRQ_HANDLER
574 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
577 bool "Micrel/Kendin KS8695"
578 select ARCH_REQUIRE_GPIOLIB
581 select GENERIC_CLOCKEVENTS
582 select NEED_MACH_MEMORY_H
584 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
585 System-on-Chip devices.
588 bool "Nuvoton W90X900 CPU"
589 select ARCH_REQUIRE_GPIOLIB
593 select GENERIC_CLOCKEVENTS
595 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
596 At present, the w90x900 has been renamed nuc900, regarding
597 the ARM series product line, you can login the following
598 link address to know more.
600 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
601 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
605 select ARCH_REQUIRE_GPIOLIB
610 select GENERIC_CLOCKEVENTS
613 select USB_ARCH_HAS_OHCI
616 Support for the NXP LPC32XX family of processors
619 bool "PXA2xx/PXA3xx-based"
621 select ARCH_HAS_CPUFREQ
623 select ARCH_REQUIRE_GPIOLIB
624 select ARM_CPU_SUSPEND if PM
628 select GENERIC_CLOCKEVENTS
631 select MULTI_IRQ_HANDLER
635 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
639 select ARCH_REQUIRE_GPIOLIB
640 select CLKSRC_OF if OF
642 select GENERIC_CLOCKEVENTS
644 Support for Qualcomm MSM/QSD based systems. This runs on the
645 apps processor of the MSM/QSD and depends on a shared memory
646 interface to the modem processor which runs the baseband
647 stack and controls some vital subsystems
648 (clock and power control, etc).
651 bool "Renesas SH-Mobile / R-Mobile"
652 select ARM_PATCH_PHYS_VIRT
654 select GENERIC_CLOCKEVENTS
655 select HAVE_ARM_SCU if SMP
656 select HAVE_ARM_TWD if SMP
657 select HAVE_MACH_CLKDEV
659 select MIGHT_HAVE_CACHE_L2X0
660 select MULTI_IRQ_HANDLER
663 select PM_GENERIC_DOMAINS if PM
666 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
671 select ARCH_MAY_HAVE_PC_FDC
672 select ARCH_SPARSEMEM_ENABLE
673 select ARCH_USES_GETTIMEOFFSET
676 select HAVE_PATA_PLATFORM
678 select NEED_MACH_IO_H
679 select NEED_MACH_MEMORY_H
683 On the Acorn Risc-PC, Linux can support the internal IDE disk and
684 CD-ROM interface, serial and parallel port, and the floppy drive.
688 select ARCH_HAS_CPUFREQ
690 select ARCH_REQUIRE_GPIOLIB
691 select ARCH_SPARSEMEM_ENABLE
696 select GENERIC_CLOCKEVENTS
699 select NEED_MACH_MEMORY_H
702 Support for StrongARM 11x0 based boards.
705 bool "Samsung S3C24XX SoCs"
706 select ARCH_HAS_CPUFREQ
707 select ARCH_REQUIRE_GPIOLIB
709 select CLKSRC_SAMSUNG_PWM
710 select GENERIC_CLOCKEVENTS
712 select HAVE_S3C2410_I2C if I2C
713 select HAVE_S3C2410_WATCHDOG if WATCHDOG
714 select HAVE_S3C_RTC if RTC_CLASS
715 select MULTI_IRQ_HANDLER
716 select NEED_MACH_GPIO_H
717 select NEED_MACH_IO_H
720 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
721 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
722 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
723 Samsung SMDK2410 development board (and derivatives).
726 bool "Samsung S3C64XX"
727 select ARCH_HAS_CPUFREQ
728 select ARCH_REQUIRE_GPIOLIB
731 select CLKSRC_SAMSUNG_PWM
734 select GENERIC_CLOCKEVENTS
736 select HAVE_S3C2410_I2C if I2C
737 select HAVE_S3C2410_WATCHDOG if WATCHDOG
739 select NEED_MACH_GPIO_H
742 select PM_GENERIC_DOMAINS
744 select S3C_GPIO_TRACK
746 select SAMSUNG_GPIOLIB_4BIT
747 select SAMSUNG_WAKEMASK
748 select SAMSUNG_WDT_RESET
749 select USB_ARCH_HAS_OHCI
751 Samsung S3C64XX series based systems
754 bool "Samsung S5P6440 S5P6450"
756 select CLKSRC_SAMSUNG_PWM
758 select GENERIC_CLOCKEVENTS
760 select HAVE_S3C2410_I2C if I2C
761 select HAVE_S3C2410_WATCHDOG if WATCHDOG
762 select HAVE_S3C_RTC if RTC_CLASS
763 select NEED_MACH_GPIO_H
765 select SAMSUNG_WDT_RESET
767 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
771 bool "Samsung S5PC100"
772 select ARCH_REQUIRE_GPIOLIB
774 select CLKSRC_SAMSUNG_PWM
776 select GENERIC_CLOCKEVENTS
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H
783 select SAMSUNG_WDT_RESET
785 Samsung S5PC100 series based systems
788 bool "Samsung S5PV210/S5PC110"
789 select ARCH_HAS_CPUFREQ
790 select ARCH_HAS_HOLES_MEMORYMODEL
791 select ARCH_SPARSEMEM_ENABLE
793 select CLKSRC_SAMSUNG_PWM
795 select GENERIC_CLOCKEVENTS
797 select HAVE_S3C2410_I2C if I2C
798 select HAVE_S3C2410_WATCHDOG if WATCHDOG
799 select HAVE_S3C_RTC if RTC_CLASS
800 select NEED_MACH_GPIO_H
801 select NEED_MACH_MEMORY_H
804 Samsung S5PV210/S5PC110 series based systems
807 bool "Samsung EXYNOS"
808 select ARCH_HAS_CPUFREQ
809 select ARCH_HAS_HOLES_MEMORYMODEL
810 select ARCH_REQUIRE_GPIOLIB
811 select ARCH_SPARSEMEM_ENABLE
815 select GENERIC_CLOCKEVENTS
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C2410_WATCHDOG if WATCHDOG
818 select HAVE_S3C_RTC if RTC_CLASS
819 select NEED_MACH_MEMORY_H
823 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
827 select ARCH_HAS_HOLES_MEMORYMODEL
828 select ARCH_REQUIRE_GPIOLIB
830 select GENERIC_ALLOCATOR
831 select GENERIC_CLOCKEVENTS
832 select GENERIC_IRQ_CHIP
838 Support for TI's DaVinci platform.
843 select ARCH_HAS_CPUFREQ
844 select ARCH_HAS_HOLES_MEMORYMODEL
846 select ARCH_REQUIRE_GPIOLIB
849 select GENERIC_CLOCKEVENTS
850 select GENERIC_IRQ_CHIP
853 select NEED_MACH_IO_H if PCCARD
854 select NEED_MACH_MEMORY_H
856 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
860 menu "Multiple platform selection"
861 depends on ARCH_MULTIPLATFORM
863 comment "CPU Core family selection"
865 config ARCH_MULTI_V4T
866 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
867 depends on !ARCH_MULTI_V6_V7
868 select ARCH_MULTI_V4_V5
869 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
870 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
871 CPU_ARM925T || CPU_ARM940T)
874 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
875 depends on !ARCH_MULTI_V6_V7
876 select ARCH_MULTI_V4_V5
877 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
878 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
879 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
881 config ARCH_MULTI_V4_V5
885 bool "ARMv6 based platforms (ARM11)"
886 select ARCH_MULTI_V6_V7
890 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
892 select ARCH_MULTI_V6_V7
895 config ARCH_MULTI_V6_V7
898 config ARCH_MULTI_CPU_AUTO
899 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
905 # This is sorted alphabetically by mach-* pathname. However, plat-*
906 # Kconfigs may be included either alphabetically (according to the
907 # plat- suffix) or along side the corresponding mach-* source.
909 source "arch/arm/mach-mvebu/Kconfig"
911 source "arch/arm/mach-at91/Kconfig"
913 source "arch/arm/mach-bcm/Kconfig"
915 source "arch/arm/mach-bcm2835/Kconfig"
917 source "arch/arm/mach-clps711x/Kconfig"
919 source "arch/arm/mach-cns3xxx/Kconfig"
921 source "arch/arm/mach-davinci/Kconfig"
923 source "arch/arm/mach-dove/Kconfig"
925 source "arch/arm/mach-ep93xx/Kconfig"
927 source "arch/arm/mach-footbridge/Kconfig"
929 source "arch/arm/mach-gemini/Kconfig"
931 source "arch/arm/mach-highbank/Kconfig"
933 source "arch/arm/mach-integrator/Kconfig"
935 source "arch/arm/mach-iop32x/Kconfig"
937 source "arch/arm/mach-iop33x/Kconfig"
939 source "arch/arm/mach-iop13xx/Kconfig"
941 source "arch/arm/mach-ixp4xx/Kconfig"
943 source "arch/arm/mach-keystone/Kconfig"
945 source "arch/arm/mach-kirkwood/Kconfig"
947 source "arch/arm/mach-ks8695/Kconfig"
949 source "arch/arm/mach-msm/Kconfig"
951 source "arch/arm/mach-mv78xx0/Kconfig"
953 source "arch/arm/mach-imx/Kconfig"
955 source "arch/arm/mach-mxs/Kconfig"
957 source "arch/arm/mach-netx/Kconfig"
959 source "arch/arm/mach-nomadik/Kconfig"
961 source "arch/arm/mach-nspire/Kconfig"
963 source "arch/arm/plat-omap/Kconfig"
965 source "arch/arm/mach-omap1/Kconfig"
967 source "arch/arm/mach-omap2/Kconfig"
969 source "arch/arm/mach-orion5x/Kconfig"
971 source "arch/arm/mach-picoxcell/Kconfig"
973 source "arch/arm/mach-pxa/Kconfig"
974 source "arch/arm/plat-pxa/Kconfig"
976 source "arch/arm/mach-mmp/Kconfig"
978 source "arch/arm/mach-realview/Kconfig"
980 source "arch/arm/mach-rockchip/Kconfig"
982 source "arch/arm/mach-sa1100/Kconfig"
984 source "arch/arm/plat-samsung/Kconfig"
986 source "arch/arm/mach-socfpga/Kconfig"
988 source "arch/arm/mach-spear/Kconfig"
990 source "arch/arm/mach-sti/Kconfig"
992 source "arch/arm/mach-s3c24xx/Kconfig"
994 source "arch/arm/mach-s3c64xx/Kconfig"
996 source "arch/arm/mach-s5p64x0/Kconfig"
998 source "arch/arm/mach-s5pc100/Kconfig"
1000 source "arch/arm/mach-s5pv210/Kconfig"
1002 source "arch/arm/mach-exynos/Kconfig"
1004 source "arch/arm/mach-shmobile/Kconfig"
1006 source "arch/arm/mach-sunxi/Kconfig"
1008 source "arch/arm/mach-prima2/Kconfig"
1010 source "arch/arm/mach-tegra/Kconfig"
1012 source "arch/arm/mach-u300/Kconfig"
1014 source "arch/arm/mach-ux500/Kconfig"
1016 source "arch/arm/mach-versatile/Kconfig"
1018 source "arch/arm/mach-vexpress/Kconfig"
1019 source "arch/arm/plat-versatile/Kconfig"
1021 source "arch/arm/mach-virt/Kconfig"
1023 source "arch/arm/mach-vt8500/Kconfig"
1025 source "arch/arm/mach-w90x900/Kconfig"
1027 source "arch/arm/mach-zynq/Kconfig"
1029 # Definitions to make life easier
1035 select GENERIC_CLOCKEVENTS
1041 select GENERIC_IRQ_CHIP
1044 config PLAT_ORION_LEGACY
1051 config PLAT_VERSATILE
1054 config ARM_TIMER_SP804
1057 select CLKSRC_OF if OF
1059 source arch/arm/mm/Kconfig
1063 default 16 if ARCH_EP93XX
1067 bool "Enable iWMMXt support" if !CPU_PJ4
1068 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1069 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1071 Enable support for iWMMXt context switching at run time if
1072 running on a CPU that supports it.
1074 config MULTI_IRQ_HANDLER
1077 Allow each machine to specify it's own IRQ handler at run time.
1080 source "arch/arm/Kconfig-nommu"
1083 config PJ4B_ERRATA_4742
1084 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1085 depends on CPU_PJ4B && MACH_ARMADA_370
1088 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1089 Event (WFE) IDLE states, a specific timing sensitivity exists between
1090 the retiring WFI/WFE instructions and the newly issued subsequent
1091 instructions. This sensitivity can result in a CPU hang scenario.
1093 The software must insert either a Data Synchronization Barrier (DSB)
1094 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1097 config ARM_ERRATA_326103
1098 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1101 Executing a SWP instruction to read-only memory does not set bit 11
1102 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1103 treat the access as a read, preventing a COW from occurring and
1104 causing the faulting task to livelock.
1106 config ARM_ERRATA_411920
1107 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1108 depends on CPU_V6 || CPU_V6K
1110 Invalidation of the Instruction Cache operation can
1111 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1112 It does not affect the MPCore. This option enables the ARM Ltd.
1113 recommended workaround.
1115 config ARM_ERRATA_430973
1116 bool "ARM errata: Stale prediction on replaced interworking branch"
1119 This option enables the workaround for the 430973 Cortex-A8
1120 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1121 interworking branch is replaced with another code sequence at the
1122 same virtual address, whether due to self-modifying code or virtual
1123 to physical address re-mapping, Cortex-A8 does not recover from the
1124 stale interworking branch prediction. This results in Cortex-A8
1125 executing the new code sequence in the incorrect ARM or Thumb state.
1126 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1127 and also flushes the branch target cache at every context switch.
1128 Note that setting specific bits in the ACTLR register may not be
1129 available in non-secure mode.
1131 config ARM_ERRATA_458693
1132 bool "ARM errata: Processor deadlock when a false hazard is created"
1134 depends on !ARCH_MULTIPLATFORM
1136 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1137 erratum. For very specific sequences of memory operations, it is
1138 possible for a hazard condition intended for a cache line to instead
1139 be incorrectly associated with a different cache line. This false
1140 hazard might then cause a processor deadlock. The workaround enables
1141 the L1 caching of the NEON accesses and disables the PLD instruction
1142 in the ACTLR register. Note that setting specific bits in the ACTLR
1143 register may not be available in non-secure mode.
1145 config ARM_ERRATA_460075
1146 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1148 depends on !ARCH_MULTIPLATFORM
1150 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1151 erratum. Any asynchronous access to the L2 cache may encounter a
1152 situation in which recent store transactions to the L2 cache are lost
1153 and overwritten with stale memory contents from external memory. The
1154 workaround disables the write-allocate mode for the L2 cache via the
1155 ACTLR register. Note that setting specific bits in the ACTLR register
1156 may not be available in non-secure mode.
1158 config ARM_ERRATA_742230
1159 bool "ARM errata: DMB operation may be faulty"
1160 depends on CPU_V7 && SMP
1161 depends on !ARCH_MULTIPLATFORM
1163 This option enables the workaround for the 742230 Cortex-A9
1164 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1165 between two write operations may not ensure the correct visibility
1166 ordering of the two writes. This workaround sets a specific bit in
1167 the diagnostic register of the Cortex-A9 which causes the DMB
1168 instruction to behave as a DSB, ensuring the correct behaviour of
1171 config ARM_ERRATA_742231
1172 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1173 depends on CPU_V7 && SMP
1174 depends on !ARCH_MULTIPLATFORM
1176 This option enables the workaround for the 742231 Cortex-A9
1177 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1178 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1179 accessing some data located in the same cache line, may get corrupted
1180 data due to bad handling of the address hazard when the line gets
1181 replaced from one of the CPUs at the same time as another CPU is
1182 accessing it. This workaround sets specific bits in the diagnostic
1183 register of the Cortex-A9 which reduces the linefill issuing
1184 capabilities of the processor.
1186 config PL310_ERRATA_588369
1187 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1188 depends on CACHE_L2X0
1190 The PL310 L2 cache controller implements three types of Clean &
1191 Invalidate maintenance operations: by Physical Address
1192 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1193 They are architecturally defined to behave as the execution of a
1194 clean operation followed immediately by an invalidate operation,
1195 both performing to the same memory location. This functionality
1196 is not correctly implemented in PL310 as clean lines are not
1197 invalidated as a result of these operations.
1199 config ARM_ERRATA_643719
1200 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1201 depends on CPU_V7 && SMP
1203 This option enables the workaround for the 643719 Cortex-A9 (prior to
1204 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1205 register returns zero when it should return one. The workaround
1206 corrects this value, ensuring cache maintenance operations which use
1207 it behave as intended and avoiding data corruption.
1209 config ARM_ERRATA_720789
1210 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1213 This option enables the workaround for the 720789 Cortex-A9 (prior to
1214 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1215 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1216 As a consequence of this erratum, some TLB entries which should be
1217 invalidated are not, resulting in an incoherency in the system page
1218 tables. The workaround changes the TLB flushing routines to invalidate
1219 entries regardless of the ASID.
1221 config PL310_ERRATA_727915
1222 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1223 depends on CACHE_L2X0
1225 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1226 operation (offset 0x7FC). This operation runs in background so that
1227 PL310 can handle normal accesses while it is in progress. Under very
1228 rare circumstances, due to this erratum, write data can be lost when
1229 PL310 treats a cacheable write transaction during a Clean &
1230 Invalidate by Way operation.
1232 config ARM_ERRATA_743622
1233 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1235 depends on !ARCH_MULTIPLATFORM
1237 This option enables the workaround for the 743622 Cortex-A9
1238 (r2p*) erratum. Under very rare conditions, a faulty
1239 optimisation in the Cortex-A9 Store Buffer may lead to data
1240 corruption. This workaround sets a specific bit in the diagnostic
1241 register of the Cortex-A9 which disables the Store Buffer
1242 optimisation, preventing the defect from occurring. This has no
1243 visible impact on the overall performance or power consumption of the
1246 config ARM_ERRATA_751472
1247 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1249 depends on !ARCH_MULTIPLATFORM
1251 This option enables the workaround for the 751472 Cortex-A9 (prior
1252 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1253 completion of a following broadcasted operation if the second
1254 operation is received by a CPU before the ICIALLUIS has completed,
1255 potentially leading to corrupted entries in the cache or TLB.
1257 config PL310_ERRATA_753970
1258 bool "PL310 errata: cache sync operation may be faulty"
1259 depends on CACHE_PL310
1261 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1263 Under some condition the effect of cache sync operation on
1264 the store buffer still remains when the operation completes.
1265 This means that the store buffer is always asked to drain and
1266 this prevents it from merging any further writes. The workaround
1267 is to replace the normal offset of cache sync operation (0x730)
1268 by another offset targeting an unmapped PL310 register 0x740.
1269 This has the same effect as the cache sync operation: store buffer
1270 drain and waiting for all buffers empty.
1272 config ARM_ERRATA_754322
1273 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1276 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1277 r3p*) erratum. A speculative memory access may cause a page table walk
1278 which starts prior to an ASID switch but completes afterwards. This
1279 can populate the micro-TLB with a stale entry which may be hit with
1280 the new ASID. This workaround places two dsb instructions in the mm
1281 switching code so that no page table walks can cross the ASID switch.
1283 config ARM_ERRATA_754327
1284 bool "ARM errata: no automatic Store Buffer drain"
1285 depends on CPU_V7 && SMP
1287 This option enables the workaround for the 754327 Cortex-A9 (prior to
1288 r2p0) erratum. The Store Buffer does not have any automatic draining
1289 mechanism and therefore a livelock may occur if an external agent
1290 continuously polls a memory location waiting to observe an update.
1291 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1292 written polling loops from denying visibility of updates to memory.
1294 config ARM_ERRATA_364296
1295 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1298 This options enables the workaround for the 364296 ARM1136
1299 r0p2 erratum (possible cache data corruption with
1300 hit-under-miss enabled). It sets the undocumented bit 31 in
1301 the auxiliary control register and the FI bit in the control
1302 register, thus disabling hit-under-miss without putting the
1303 processor into full low interrupt latency mode. ARM11MPCore
1306 config ARM_ERRATA_764369
1307 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1308 depends on CPU_V7 && SMP
1310 This option enables the workaround for erratum 764369
1311 affecting Cortex-A9 MPCore with two or more processors (all
1312 current revisions). Under certain timing circumstances, a data
1313 cache line maintenance operation by MVA targeting an Inner
1314 Shareable memory region may fail to proceed up to either the
1315 Point of Coherency or to the Point of Unification of the
1316 system. This workaround adds a DSB instruction before the
1317 relevant cache maintenance functions and sets a specific bit
1318 in the diagnostic control register of the SCU.
1320 config PL310_ERRATA_769419
1321 bool "PL310 errata: no automatic Store Buffer drain"
1322 depends on CACHE_L2X0
1324 On revisions of the PL310 prior to r3p2, the Store Buffer does
1325 not automatically drain. This can cause normal, non-cacheable
1326 writes to be retained when the memory system is idle, leading
1327 to suboptimal I/O performance for drivers using coherent DMA.
1328 This option adds a write barrier to the cpu_idle loop so that,
1329 on systems with an outer cache, the store buffer is drained
1332 config ARM_ERRATA_775420
1333 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1336 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1337 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1338 operation aborts with MMU exception, it might cause the processor
1339 to deadlock. This workaround puts DSB before executing ISB if
1340 an abort may occur on cache maintenance.
1342 config ARM_ERRATA_798181
1343 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1344 depends on CPU_V7 && SMP
1346 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1347 adequately shooting down all use of the old entries. This
1348 option enables the Linux kernel workaround for this erratum
1349 which sends an IPI to the CPUs that are running the same ASID
1350 as the one being invalidated.
1352 config ARM_ERRATA_773022
1353 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1356 This option enables the workaround for the 773022 Cortex-A15
1357 (up to r0p4) erratum. In certain rare sequences of code, the
1358 loop buffer may deliver incorrect instructions. This
1359 workaround disables the loop buffer to avoid the erratum.
1363 source "arch/arm/common/Kconfig"
1373 Find out whether you have ISA slots on your motherboard. ISA is the
1374 name of a bus system, i.e. the way the CPU talks to the other stuff
1375 inside your box. Other bus systems are PCI, EISA, MicroChannel
1376 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1377 newer boards don't support it. If you have ISA, say Y, otherwise N.
1379 # Select ISA DMA controller support
1384 # Select ISA DMA interface
1389 bool "PCI support" if MIGHT_HAVE_PCI
1391 Find out whether you have a PCI motherboard. PCI is the name of a
1392 bus system, i.e. the way the CPU talks to the other stuff inside
1393 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1394 VESA. If you have PCI, say Y, otherwise N.
1400 config PCI_NANOENGINE
1401 bool "BSE nanoEngine PCI support"
1402 depends on SA1100_NANOENGINE
1404 Enable PCI on the BSE nanoEngine board.
1409 config PCI_HOST_ITE8152
1411 depends on PCI && MACH_ARMCORE
1415 source "drivers/pci/Kconfig"
1416 source "drivers/pci/pcie/Kconfig"
1418 source "drivers/pcmcia/Kconfig"
1422 menu "Kernel Features"
1427 This option should be selected by machines which have an SMP-
1430 The only effect of this option is to make the SMP-related
1431 options available to the user for configuration.
1434 bool "Symmetric Multi-Processing"
1435 depends on CPU_V6K || CPU_V7
1436 depends on GENERIC_CLOCKEVENTS
1438 depends on MMU || ARM_MPU
1440 This enables support for systems with more than one CPU. If you have
1441 a system with only one CPU, like most personal computers, say N. If
1442 you have a system with more than one CPU, say Y.
1444 If you say N here, the kernel will run on single and multiprocessor
1445 machines, but will use only one CPU of a multiprocessor machine. If
1446 you say Y here, the kernel will run on many, but not all, single
1447 processor machines. On a single processor machine, the kernel will
1448 run faster if you say N here.
1450 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1451 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1452 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1454 If you don't know what to do here, say N.
1457 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1458 depends on SMP && !XIP_KERNEL && MMU
1461 SMP kernels contain instructions which fail on non-SMP processors.
1462 Enabling this option allows the kernel to modify itself to make
1463 these instructions safe. Disabling it allows about 1K of space
1466 If you don't know what to do here, say Y.
1468 config ARM_CPU_TOPOLOGY
1469 bool "Support cpu topology definition"
1470 depends on SMP && CPU_V7
1473 Support ARM cpu topology definition. The MPIDR register defines
1474 affinity between processors which is then used to describe the cpu
1475 topology of an ARM System.
1478 bool "Multi-core scheduler support"
1479 depends on ARM_CPU_TOPOLOGY
1481 Multi-core scheduler support improves the CPU scheduler's decision
1482 making when dealing with multi-core CPU chips at a cost of slightly
1483 increased overhead in some places. If unsure say N here.
1486 bool "SMT scheduler support"
1487 depends on ARM_CPU_TOPOLOGY
1489 Improves the CPU scheduler's decision making when dealing with
1490 MultiThreading at a cost of slightly increased overhead in some
1491 places. If unsure say N here.
1496 This option enables support for the ARM system coherency unit
1498 config HAVE_ARM_ARCH_TIMER
1499 bool "Architected timer support"
1501 select ARM_ARCH_TIMER
1502 select GENERIC_CLOCKEVENTS
1504 This option enables support for the ARM architected timer
1509 select CLKSRC_OF if OF
1511 This options enables support for the ARM timer and watchdog unit
1514 bool "Multi-Cluster Power Management"
1515 depends on CPU_V7 && SMP
1517 This option provides the common power management infrastructure
1518 for (multi-)cluster based systems, such as big.LITTLE based
1522 bool "big.LITTLE support (Experimental)"
1523 depends on CPU_V7 && SMP
1526 This option enables support selections for the big.LITTLE
1527 system architecture.
1530 bool "big.LITTLE switcher support"
1531 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1533 select ARM_CPU_SUSPEND
1535 The big.LITTLE "switcher" provides the core functionality to
1536 transparently handle transition between a cluster of A15's
1537 and a cluster of A7's in a big.LITTLE system.
1539 config BL_SWITCHER_DUMMY_IF
1540 tristate "Simple big.LITTLE switcher user interface"
1541 depends on BL_SWITCHER && DEBUG_KERNEL
1543 This is a simple and dummy char dev interface to control
1544 the big.LITTLE switcher core code. It is meant for
1545 debugging purposes only.
1548 prompt "Memory split"
1551 Select the desired split between kernel and user memory.
1553 If you are not absolutely sure what you are doing, leave this
1557 bool "3G/1G user/kernel split"
1559 bool "2G/2G user/kernel split"
1561 bool "1G/3G user/kernel split"
1566 default 0x40000000 if VMSPLIT_1G
1567 default 0x80000000 if VMSPLIT_2G
1571 int "Maximum number of CPUs (2-32)"
1577 bool "Support for hot-pluggable CPUs"
1580 Say Y here to experiment with turning CPUs off and on. CPUs
1581 can be controlled through /sys/devices/system/cpu.
1584 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1587 Say Y here if you want Linux to communicate with system firmware
1588 implementing the PSCI specification for CPU-centric power
1589 management operations described in ARM document number ARM DEN
1590 0022A ("Power State Coordination Interface System Software on
1593 # The GPIO number here must be sorted by descending number. In case of
1594 # a multiplatform kernel, we just want the highest value required by the
1595 # selected platforms.
1598 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1599 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1600 default 392 if ARCH_U8500
1601 default 352 if ARCH_VT8500
1602 default 288 if ARCH_SUNXI
1603 default 264 if MACH_H4700
1606 Maximum number of GPIOs in the system.
1608 If unsure, leave the default value.
1610 source kernel/Kconfig.preempt
1614 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1615 ARCH_S5PV210 || ARCH_EXYNOS4
1616 default AT91_TIMER_HZ if ARCH_AT91
1617 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1621 depends on HZ_FIXED = 0
1622 prompt "Timer frequency"
1646 default HZ_FIXED if HZ_FIXED != 0
1647 default 100 if HZ_100
1648 default 200 if HZ_200
1649 default 250 if HZ_250
1650 default 300 if HZ_300
1651 default 500 if HZ_500
1655 def_bool HIGH_RES_TIMERS
1657 config THUMB2_KERNEL
1658 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1659 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1660 default y if CPU_THUMBONLY
1662 select ARM_ASM_UNIFIED
1665 By enabling this option, the kernel will be compiled in
1666 Thumb-2 mode. A compiler/assembler that understand the unified
1667 ARM-Thumb syntax is needed.
1671 config THUMB2_AVOID_R_ARM_THM_JUMP11
1672 bool "Work around buggy Thumb-2 short branch relocations in gas"
1673 depends on THUMB2_KERNEL && MODULES
1676 Various binutils versions can resolve Thumb-2 branches to
1677 locally-defined, preemptible global symbols as short-range "b.n"
1678 branch instructions.
1680 This is a problem, because there's no guarantee the final
1681 destination of the symbol, or any candidate locations for a
1682 trampoline, are within range of the branch. For this reason, the
1683 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1684 relocation in modules at all, and it makes little sense to add
1687 The symptom is that the kernel fails with an "unsupported
1688 relocation" error when loading some modules.
1690 Until fixed tools are available, passing
1691 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1692 code which hits this problem, at the cost of a bit of extra runtime
1693 stack usage in some cases.
1695 The problem is described in more detail at:
1696 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1698 Only Thumb-2 kernels are affected.
1700 Unless you are sure your tools don't have this problem, say Y.
1702 config ARM_ASM_UNIFIED
1706 bool "Use the ARM EABI to compile the kernel"
1708 This option allows for the kernel to be compiled using the latest
1709 ARM ABI (aka EABI). This is only useful if you are using a user
1710 space environment that is also compiled with EABI.
1712 Since there are major incompatibilities between the legacy ABI and
1713 EABI, especially with regard to structure member alignment, this
1714 option also changes the kernel syscall calling convention to
1715 disambiguate both ABIs and allow for backward compatibility support
1716 (selected with CONFIG_OABI_COMPAT).
1718 To use this you need GCC version 4.0.0 or later.
1721 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1722 depends on AEABI && !THUMB2_KERNEL
1724 This option preserves the old syscall interface along with the
1725 new (ARM EABI) one. It also provides a compatibility layer to
1726 intercept syscalls that have structure arguments which layout
1727 in memory differs between the legacy ABI and the new ARM EABI
1728 (only for non "thumb" binaries). This option adds a tiny
1729 overhead to all syscalls and produces a slightly larger kernel.
1731 The seccomp filter system will not be available when this is
1732 selected, since there is no way yet to sensibly distinguish
1733 between calling conventions during filtering.
1735 If you know you'll be using only pure EABI user space then you
1736 can say N here. If this option is not selected and you attempt
1737 to execute a legacy ABI binary then the result will be
1738 UNPREDICTABLE (in fact it can be predicted that it won't work
1739 at all). If in doubt say N.
1741 config ARCH_HAS_HOLES_MEMORYMODEL
1744 config ARCH_SPARSEMEM_ENABLE
1747 config ARCH_SPARSEMEM_DEFAULT
1748 def_bool ARCH_SPARSEMEM_ENABLE
1750 config ARCH_SELECT_MEMORY_MODEL
1751 def_bool ARCH_SPARSEMEM_ENABLE
1753 config HAVE_ARCH_PFN_VALID
1754 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1757 bool "High Memory Support"
1760 The address space of ARM processors is only 4 Gigabytes large
1761 and it has to accommodate user address space, kernel address
1762 space as well as some memory mapped IO. That means that, if you
1763 have a large amount of physical memory and/or IO, not all of the
1764 memory can be "permanently mapped" by the kernel. The physical
1765 memory that is not permanently mapped is called "high memory".
1767 Depending on the selected kernel/user memory split, minimum
1768 vmalloc space and actual amount of RAM, you may not need this
1769 option which should result in a slightly faster kernel.
1774 bool "Allocate 2nd-level pagetables from highmem"
1777 config HW_PERF_EVENTS
1778 bool "Enable hardware performance counter support for perf events"
1779 depends on PERF_EVENTS
1782 Enable hardware performance counter support for perf events. If
1783 disabled, perf events will use software events only.
1785 config SYS_SUPPORTS_HUGETLBFS
1789 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1793 config ARCH_WANT_GENERAL_HUGETLB
1798 config FORCE_MAX_ZONEORDER
1799 int "Maximum zone order" if ARCH_SHMOBILE
1800 range 11 64 if ARCH_SHMOBILE
1801 default "12" if SOC_AM33XX
1802 default "9" if SA1111
1805 The kernel memory allocator divides physically contiguous memory
1806 blocks into "zones", where each zone is a power of two number of
1807 pages. This option selects the largest power of two that the kernel
1808 keeps in the memory allocator. If you need to allocate very large
1809 blocks of physically contiguous memory, then you may need to
1810 increase this value.
1812 This config option is actually maximum order plus one. For example,
1813 a value of 11 means that the largest free memory block is 2^10 pages.
1815 config ALIGNMENT_TRAP
1817 depends on CPU_CP15_MMU
1818 default y if !ARCH_EBSA110
1819 select HAVE_PROC_CPU if PROC_FS
1821 ARM processors cannot fetch/store information which is not
1822 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1823 address divisible by 4. On 32-bit ARM processors, these non-aligned
1824 fetch/store instructions will be emulated in software if you say
1825 here, which has a severe performance impact. This is necessary for
1826 correct operation of some network protocols. With an IP-only
1827 configuration it is safe to say N, otherwise say Y.
1829 config UACCESS_WITH_MEMCPY
1830 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1832 default y if CPU_FEROCEON
1834 Implement faster copy_to_user and clear_user methods for CPU
1835 cores where a 8-word STM instruction give significantly higher
1836 memory write throughput than a sequence of individual 32bit stores.
1838 A possible side effect is a slight increase in scheduling latency
1839 between threads sharing the same address space if they invoke
1840 such copy operations with large buffers.
1842 However, if the CPU data cache is using a write-allocate mode,
1843 this option is unlikely to provide any performance gain.
1847 prompt "Enable seccomp to safely compute untrusted bytecode"
1849 This kernel feature is useful for number crunching applications
1850 that may need to compute untrusted bytecode during their
1851 execution. By using pipes or other transports made available to
1852 the process as file descriptors supporting the read/write
1853 syscalls, it's possible to isolate those applications in
1854 their own address space using seccomp. Once seccomp is
1855 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1856 and the task is only allowed to execute a few safe syscalls
1857 defined by each seccomp mode.
1859 config CC_STACKPROTECTOR
1860 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1862 This option turns on the -fstack-protector GCC feature. This
1863 feature puts, at the beginning of functions, a canary value on
1864 the stack just before the return address, and validates
1865 the value just before actually returning. Stack based buffer
1866 overflows (that need to overwrite this return address) now also
1867 overwrite the canary, which gets detected and the attack is then
1868 neutralized via a kernel panic.
1869 This feature requires gcc version 4.2 or above.
1882 bool "Xen guest support on ARM (EXPERIMENTAL)"
1883 depends on ARM && AEABI && OF
1884 depends on CPU_V7 && !CPU_V6
1885 depends on !GENERIC_ATOMIC64
1889 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1896 bool "Flattened Device Tree support"
1899 select OF_EARLY_FLATTREE
1901 Include support for flattened device tree machine descriptions.
1904 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1907 This is the traditional way of passing data to the kernel at boot
1908 time. If you are solely relying on the flattened device tree (or
1909 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1910 to remove ATAGS support from your kernel binary. If unsure,
1913 config DEPRECATED_PARAM_STRUCT
1914 bool "Provide old way to pass kernel parameters"
1917 This was deprecated in 2001 and announced to live on for 5 years.
1918 Some old boot loaders still use this way.
1920 # Compressed boot loader in ROM. Yes, we really want to ask about
1921 # TEXT and BSS so we preserve their values in the config files.
1922 config ZBOOT_ROM_TEXT
1923 hex "Compressed ROM boot loader base address"
1926 The physical address at which the ROM-able zImage is to be
1927 placed in the target. Platforms which normally make use of
1928 ROM-able zImage formats normally set this to a suitable
1929 value in their defconfig file.
1931 If ZBOOT_ROM is not enabled, this has no effect.
1933 config ZBOOT_ROM_BSS
1934 hex "Compressed ROM boot loader BSS address"
1937 The base address of an area of read/write memory in the target
1938 for the ROM-able zImage which must be available while the
1939 decompressor is running. It must be large enough to hold the
1940 entire decompressed kernel plus an additional 128 KiB.
1941 Platforms which normally make use of ROM-able zImage formats
1942 normally set this to a suitable value in their defconfig file.
1944 If ZBOOT_ROM is not enabled, this has no effect.
1947 bool "Compressed boot loader in ROM/flash"
1948 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1949 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1951 Say Y here if you intend to execute your compressed kernel image
1952 (zImage) directly from ROM or flash. If unsure, say N.
1955 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1956 depends on ZBOOT_ROM && ARCH_SH7372
1957 default ZBOOT_ROM_NONE
1959 Include experimental SD/MMC loading code in the ROM-able zImage.
1960 With this enabled it is possible to write the ROM-able zImage
1961 kernel image to an MMC or SD card and boot the kernel straight
1962 from the reset vector. At reset the processor Mask ROM will load
1963 the first part of the ROM-able zImage which in turn loads the
1964 rest the kernel image to RAM.
1966 config ZBOOT_ROM_NONE
1967 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1969 Do not load image from SD or MMC
1971 config ZBOOT_ROM_MMCIF
1972 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1974 Load image from MMCIF hardware block.
1976 config ZBOOT_ROM_SH_MOBILE_SDHI
1977 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1979 Load image from SDHI hardware block
1983 config ARM_APPENDED_DTB
1984 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1987 With this option, the boot code will look for a device tree binary
1988 (DTB) appended to zImage
1989 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1991 This is meant as a backward compatibility convenience for those
1992 systems with a bootloader that can't be upgraded to accommodate
1993 the documented boot protocol using a device tree.
1995 Beware that there is very little in terms of protection against
1996 this option being confused by leftover garbage in memory that might
1997 look like a DTB header after a reboot if no actual DTB is appended
1998 to zImage. Do not leave this option active in a production kernel
1999 if you don't intend to always append a DTB. Proper passing of the
2000 location into r2 of a bootloader provided DTB is always preferable
2003 config ARM_ATAG_DTB_COMPAT
2004 bool "Supplement the appended DTB with traditional ATAG information"
2005 depends on ARM_APPENDED_DTB
2007 Some old bootloaders can't be updated to a DTB capable one, yet
2008 they provide ATAGs with memory configuration, the ramdisk address,
2009 the kernel cmdline string, etc. Such information is dynamically
2010 provided by the bootloader and can't always be stored in a static
2011 DTB. To allow a device tree enabled kernel to be used with such
2012 bootloaders, this option allows zImage to extract the information
2013 from the ATAG list and store it at run time into the appended DTB.
2016 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2017 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2019 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2020 bool "Use bootloader kernel arguments if available"
2022 Uses the command-line options passed by the boot loader instead of
2023 the device tree bootargs property. If the boot loader doesn't provide
2024 any, the device tree bootargs property will be used.
2026 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2027 bool "Extend with bootloader kernel arguments"
2029 The command-line arguments provided by the boot loader will be
2030 appended to the the device tree bootargs property.
2035 string "Default kernel command string"
2038 On some architectures (EBSA110 and CATS), there is currently no way
2039 for the boot loader to pass arguments to the kernel. For these
2040 architectures, you should supply some command-line options at build
2041 time by entering them here. As a minimum, you should specify the
2042 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2045 prompt "Kernel command line type" if CMDLINE != ""
2046 default CMDLINE_FROM_BOOTLOADER
2049 config CMDLINE_FROM_BOOTLOADER
2050 bool "Use bootloader kernel arguments if available"
2052 Uses the command-line options passed by the boot loader. If
2053 the boot loader doesn't provide any, the default kernel command
2054 string provided in CMDLINE will be used.
2056 config CMDLINE_EXTEND
2057 bool "Extend bootloader kernel arguments"
2059 The command-line arguments provided by the boot loader will be
2060 appended to the default kernel command string.
2062 config CMDLINE_FORCE
2063 bool "Always use the default kernel command string"
2065 Always use the default kernel command string, even if the boot
2066 loader passes other arguments to the kernel.
2067 This is useful if you cannot or don't want to change the
2068 command-line options your boot loader passes to the kernel.
2072 bool "Kernel Execute-In-Place from ROM"
2073 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
2075 Execute-In-Place allows the kernel to run from non-volatile storage
2076 directly addressable by the CPU, such as NOR flash. This saves RAM
2077 space since the text section of the kernel is not loaded from flash
2078 to RAM. Read-write sections, such as the data section and stack,
2079 are still copied to RAM. The XIP kernel is not compressed since
2080 it has to run directly from flash, so it will take more space to
2081 store it. The flash address used to link the kernel object files,
2082 and for storing it, is configuration dependent. Therefore, if you
2083 say Y here, you must know the proper physical address where to
2084 store the kernel image depending on your own flash memory usage.
2086 Also note that the make target becomes "make xipImage" rather than
2087 "make zImage" or "make Image". The final kernel binary to put in
2088 ROM memory will be arch/arm/boot/xipImage.
2092 config XIP_PHYS_ADDR
2093 hex "XIP Kernel Physical Location"
2094 depends on XIP_KERNEL
2095 default "0x00080000"
2097 This is the physical address in your flash memory the kernel will
2098 be linked for and stored to. This address is dependent on your
2102 bool "Kexec system call (EXPERIMENTAL)"
2103 depends on (!SMP || PM_SLEEP_SMP)
2105 kexec is a system call that implements the ability to shutdown your
2106 current kernel, and to start another kernel. It is like a reboot
2107 but it is independent of the system firmware. And like a reboot
2108 you can start any kernel with it, not just Linux.
2110 It is an ongoing process to be certain the hardware in a machine
2111 is properly shutdown, so do not be surprised if this code does not
2112 initially work for you.
2115 bool "Export atags in procfs"
2116 depends on ATAGS && KEXEC
2119 Should the atags used to boot the kernel be exported in an "atags"
2120 file in procfs. Useful with kexec.
2123 bool "Build kdump crash kernel (EXPERIMENTAL)"
2125 Generate crash dump after being started by kexec. This should
2126 be normally only set in special crash dump kernels which are
2127 loaded in the main kernel with kexec-tools into a specially
2128 reserved region and then later executed after a crash by
2129 kdump/kexec. The crash dump kernel must be compiled to a
2130 memory address not used by the main kernel
2132 For more details see Documentation/kdump/kdump.txt
2134 config AUTO_ZRELADDR
2135 bool "Auto calculation of the decompressed kernel image address"
2137 ZRELADDR is the physical address where the decompressed kernel
2138 image will be placed. If AUTO_ZRELADDR is selected, the address
2139 will be determined at run-time by masking the current IP with
2140 0xf8000000. This assumes the zImage being placed in the first 128MB
2141 from start of memory.
2145 menu "CPU Power Management"
2148 source "drivers/cpufreq/Kconfig"
2151 source "drivers/cpuidle/Kconfig"
2155 menu "Floating point emulation"
2157 comment "At least one emulation must be selected"
2160 bool "NWFPE math emulation"
2161 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2163 Say Y to include the NWFPE floating point emulator in the kernel.
2164 This is necessary to run most binaries. Linux does not currently
2165 support floating point hardware so you need to say Y here even if
2166 your machine has an FPA or floating point co-processor podule.
2168 You may say N here if you are going to load the Acorn FPEmulator
2169 early in the bootup.
2172 bool "Support extended precision"
2173 depends on FPE_NWFPE
2175 Say Y to include 80-bit support in the kernel floating-point
2176 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2177 Note that gcc does not generate 80-bit operations by default,
2178 so in most cases this option only enlarges the size of the
2179 floating point emulator without any good reason.
2181 You almost surely want to say N here.
2184 bool "FastFPE math emulation (EXPERIMENTAL)"
2185 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2187 Say Y here to include the FAST floating point emulator in the kernel.
2188 This is an experimental much faster emulator which now also has full
2189 precision for the mantissa. It does not support any exceptions.
2190 It is very simple, and approximately 3-6 times faster than NWFPE.
2192 It should be sufficient for most programs. It may be not suitable
2193 for scientific calculations, but you have to check this for yourself.
2194 If you do not feel you need a faster FP emulation you should better
2198 bool "VFP-format floating point maths"
2199 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2201 Say Y to include VFP support code in the kernel. This is needed
2202 if your hardware includes a VFP unit.
2204 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2205 release notes and additional status information.
2207 Say N if your target does not have VFP hardware.
2215 bool "Advanced SIMD (NEON) Extension support"
2216 depends on VFPv3 && CPU_V7
2218 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2221 config KERNEL_MODE_NEON
2222 bool "Support for NEON in kernel mode"
2223 depends on NEON && AEABI
2225 Say Y to include support for NEON in kernel mode.
2229 menu "Userspace binary formats"
2231 source "fs/Kconfig.binfmt"
2234 tristate "RISC OS personality"
2237 Say Y here to include the kernel code necessary if you want to run
2238 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2239 experimental; if this sounds frightening, say N and sleep in peace.
2240 You can also say M here to compile this support as a module (which
2241 will be called arthur).
2245 menu "Power management options"
2247 source "kernel/power/Kconfig"
2249 config ARCH_SUSPEND_POSSIBLE
2250 depends on !ARCH_S5PC100
2251 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2252 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2255 config ARM_CPU_SUSPEND
2260 source "net/Kconfig"
2262 source "drivers/Kconfig"
2266 source "arch/arm/Kconfig.debug"
2268 source "security/Kconfig"
2270 source "crypto/Kconfig"
2272 source "lib/Kconfig"
2274 source "arch/arm/kvm/Kconfig"