1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
15 select INIT_SP_RELATIVE
17 U-Boot expects to be linked to a specific hard-coded address, and to
18 be loaded to and run from that address. This option lifts that
19 restriction, thus allowing the code to be loaded to and executed
20 from almost any address. This logic relies on the relocation
21 information that is embedded in the binary to support U-Boot
22 relocating itself to the top-of-RAM later during execution.
24 config INIT_SP_RELATIVE
25 bool "Specify the early stack pointer relative to the .bss section"
27 U-Boot typically uses a hard-coded value for the stack pointer
28 before relocation. Enable this option to instead calculate the
29 initial SP at run-time. This is useful to avoid hard-coding addresses
30 into U-Boot, so that it can be loaded and executed at arbitrary
31 addresses and thus avoid using arbitrary addresses at runtime.
33 If this option is enabled, the early stack pointer is set to
34 &_bss_start with a offset value added. The offset is specified by
35 SYS_INIT_SP_BSS_OFFSET.
37 config SYS_INIT_SP_BSS_OFFSET
38 int "Early stack offset from the .bss base address"
39 depends on INIT_SP_RELATIVE
42 This option's value is the offset added to &_bss_start in order to
43 calculate the stack pointer. This offset should be large enough so
44 that the early malloc region, global data (gd), and early stack usage
45 do not overlap any appended DTB.
47 config LINUX_KERNEL_IMAGE_HEADER
50 Place a Linux kernel image header at the start of the U-Boot binary.
51 The format of the header is described in the Linux kernel source at
52 Documentation/arm64/booting.txt. This feature is useful since the
53 image header reports the amount of memory (BSS and similar) that
54 U-Boot needs to use, but which isn't part of the binary.
56 if LINUX_KERNEL_IMAGE_HEADER
57 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
60 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
61 TEXT_OFFSET value written to the Linux kernel image header.
70 ARM GICV3 Interrupt translation service (ITS).
71 Basic support for programming locality specific peripheral
72 interrupts (LPI) configuration tables and enable LPI tables.
73 LPI configuration table can be used by u-boot or Linux.
74 ARM GICV3 has limitation, once the LPI table is enabled, LPI
75 configuration table can not be re-programmed, unless GICV3 reset.
79 default y if ARM64 && !POSITION_INDEPENDENT
81 config DMA_ADDR_T_64BIT
91 # Used for compatibility with asm files copied from the kernel
92 config ARM_ASM_UNIFIED
96 # Used for compatibility with asm files copied from the kernel
100 config SYS_ICACHE_OFF
101 bool "Do not enable icache"
104 Do not enable instruction cache in U-Boot.
106 config SPL_SYS_ICACHE_OFF
107 bool "Do not enable icache in SPL"
109 default SYS_ICACHE_OFF
111 Do not enable instruction cache in SPL.
113 config SYS_DCACHE_OFF
114 bool "Do not enable dcache"
117 Do not enable data cache in U-Boot.
119 config SPL_SYS_DCACHE_OFF
120 bool "Do not enable dcache in SPL"
122 default SYS_DCACHE_OFF
124 Do not enable data cache in SPL.
126 config SYS_ARM_CACHE_CP15
127 bool "CP15 based cache enabling support"
129 Select this if your processor suports enabling caches by using
133 bool "MMU-based Paged Memory Management Support"
134 select SYS_ARM_CACHE_CP15
136 Select if you want MMU-based virtualised addressing space
137 support via paged memory management.
140 bool 'Use the ARM v7 PMSA Compliant MPU'
142 Some ARM systems without an MMU have instead a Memory Protection
143 Unit (MPU) that defines the type and permissions for regions of
145 If your CPU has an MPU then you should choose 'y' here unless you
146 know that you do not want to use the MPU.
148 # If set, the workarounds for these ARM errata are applied early during U-Boot
149 # startup. Note that in general these options force the workarounds to be
150 # applied; no CPU-type/version detection exists, unlike the similar options in
151 # the Linux kernel. Do not set these options unless they apply! Also note that
152 # the following can be machine-specific errata. These do have ability to
153 # provide rudimentary version and machine-specific checks, but expect no
155 # CONFIG_ARM_ERRATA_430973
156 # CONFIG_ARM_ERRATA_454179
157 # CONFIG_ARM_ERRATA_621766
158 # CONFIG_ARM_ERRATA_798870
159 # CONFIG_ARM_ERRATA_801819
160 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
161 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
163 config ARM_ERRATA_430973
166 config ARM_ERRATA_454179
169 config ARM_ERRATA_621766
172 config ARM_ERRATA_716044
175 config ARM_ERRATA_725233
178 config ARM_ERRATA_742230
181 config ARM_ERRATA_743622
184 config ARM_ERRATA_751472
187 config ARM_ERRATA_761320
190 config ARM_ERRATA_773022
193 config ARM_ERRATA_774769
196 config ARM_ERRATA_794072
199 config ARM_ERRATA_798870
202 config ARM_ERRATA_801819
205 config ARM_ERRATA_826974
208 config ARM_ERRATA_828024
211 config ARM_ERRATA_829520
214 config ARM_ERRATA_833069
217 config ARM_ERRATA_833471
220 config ARM_ERRATA_845369
223 config ARM_ERRATA_852421
226 config ARM_ERRATA_852423
229 config ARM_ERRATA_855873
232 config ARM_CORTEX_A8_CVE_2017_5715
235 config ARM_CORTEX_A15_CVE_2017_5715
240 select SYS_CACHE_SHIFT_5
245 select SYS_CACHE_SHIFT_5
250 select SYS_CACHE_SHIFT_5
255 select SYS_CACHE_SHIFT_5
260 select SYS_CACHE_SHIFT_5
266 select SYS_CACHE_SHIFT_5
273 select SYS_CACHE_SHIFT_6
280 select SYS_CACHE_SHIFT_5
281 select SYS_THUMB_BUILD
287 select SYS_ARM_CACHE_CP15
289 select SYS_CACHE_SHIFT_6
293 select SYS_CACHE_SHIFT_5
298 select SYS_CACHE_SHIFT_5
302 default "arm720t" if CPU_ARM720T
303 default "arm920t" if CPU_ARM920T
304 default "arm926ejs" if CPU_ARM926EJS
305 default "arm946es" if CPU_ARM946ES
306 default "arm1136" if CPU_ARM1136
307 default "arm1176" if CPU_ARM1176
308 default "armv7" if CPU_V7A
309 default "armv7" if CPU_V7R
310 default "armv7m" if CPU_V7M
311 default "pxa" if CPU_PXA
312 default "sa1100" if CPU_SA1100
313 default "armv8" if ARM64
317 default 4 if CPU_ARM720T
318 default 4 if CPU_ARM920T
319 default 5 if CPU_ARM926EJS
320 default 5 if CPU_ARM946ES
321 default 6 if CPU_ARM1136
322 default 6 if CPU_ARM1176
327 default 4 if CPU_SA1100
330 config SYS_CACHE_SHIFT_5
333 config SYS_CACHE_SHIFT_6
336 config SYS_CACHE_SHIFT_7
339 config SYS_CACHELINE_SIZE
341 default 128 if SYS_CACHE_SHIFT_7
342 default 64 if SYS_CACHE_SHIFT_6
343 default 32 if SYS_CACHE_SHIFT_5
346 prompt "Select the ARM data write cache policy"
347 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
348 TARGET_BCMNSP || CPU_PXA || RZA1
349 default SYS_ARM_CACHE_WRITEBACK
351 config SYS_ARM_CACHE_WRITEBACK
352 bool "Write-back (WB)"
354 A write updates the cache only and marks the cache line as dirty.
355 External memory is updated only when the line is evicted or explicitly
358 config SYS_ARM_CACHE_WRITETHROUGH
359 bool "Write-through (WT)"
361 A write updates both the cache and the external memory system.
362 This does not mark the cache line as dirty.
364 config SYS_ARM_CACHE_WRITEALLOC
365 bool "Write allocation (WA)"
367 A cache line is allocated on a write miss. This means that executing a
368 store instruction on the processor might cause a burst read to occur.
369 There is a linefill to obtain the data for the cache line, before the
374 bool "Enable ARCH_CPU_INIT"
376 Some architectures require a call to arch_cpu_init().
377 Say Y here to enable it
379 config SYS_ARCH_TIMER
380 bool "ARM Generic Timer support"
381 depends on CPU_V7A || ARM64
384 The ARM Generic Timer (aka arch-timer) provides an architected
385 interface to a timer source on an SoC.
386 It is mandatory for ARMv8 implementation and widely available
390 bool "Support for ARM SMC Calling Convention (SMCCC)"
391 depends on CPU_V7A || ARM64
394 Say Y here if you want to enable ARM SMC Calling Convention.
395 This should be enabled if U-Boot needs to communicate with system
396 firmware (for example, PSCI) according to SMCCC.
399 bool "support boot from semihosting"
401 In emulated environments, semihosting is a way for
402 the hosted environment to call out to the emulator to
403 retrieve files from the host machine.
405 config SYS_THUMB_BUILD
406 bool "Build U-Boot using the Thumb instruction set"
409 Use this flag to build U-Boot using the Thumb instruction set for
410 ARM architectures. Thumb instruction set provides better code
411 density. For ARM architectures that support Thumb2 this flag will
412 result in Thumb2 code generated by GCC.
414 config SPL_SYS_THUMB_BUILD
415 bool "Build SPL using the Thumb instruction set"
416 default y if SYS_THUMB_BUILD
417 depends on !ARM64 && SPL
419 Use this flag to build SPL using the Thumb instruction set for
420 ARM architectures. Thumb instruction set provides better code
421 density. For ARM architectures that support Thumb2 this flag will
422 result in Thumb2 code generated by GCC.
424 config TPL_SYS_THUMB_BUILD
425 bool "Build TPL using the Thumb instruction set"
426 default y if SYS_THUMB_BUILD
427 depends on TPL && !ARM64
429 Use this flag to build TPL using the Thumb instruction set for
430 ARM architectures. Thumb instruction set provides better code
431 density. For ARM architectures that support Thumb2 this flag will
432 result in Thumb2 code generated by GCC.
435 config SYS_L2CACHE_OFF
438 If SoC does not support L2CACHE or one does not want to enable
439 L2CACHE, choose this option.
441 config ENABLE_ARM_SOC_BOOT0_HOOK
442 bool "prepare BOOT0 header"
444 If the SoC's BOOT0 requires a header area filled with (magic)
445 values, then choose this option, and create a file included as
446 <asm/arch/boot0.h> which contains the required assembler code.
448 config ARM_CORTEX_CPU_IS_UP
452 config USE_ARCH_MEMCPY
453 bool "Use an assembly optimized implementation of memcpy"
457 Enable the generation of an optimized version of memcpy.
458 Such an implementation may be faster under some conditions
459 but may increase the binary size.
461 config SPL_USE_ARCH_MEMCPY
462 bool "Use an assembly optimized implementation of memcpy for SPL"
463 default y if USE_ARCH_MEMCPY
464 depends on !ARM64 && SPL
466 Enable the generation of an optimized version of memcpy.
467 Such an implementation may be faster under some conditions
468 but may increase the binary size.
470 config TPL_USE_ARCH_MEMCPY
471 bool "Use an assembly optimized implementation of memcpy for TPL"
472 default y if USE_ARCH_MEMCPY
473 depends on !ARM64 && TPL
475 Enable the generation of an optimized version of memcpy.
476 Such an implementation may be faster under some conditions
477 but may increase the binary size.
479 config USE_ARCH_MEMSET
480 bool "Use an assembly optimized implementation of memset"
484 Enable the generation of an optimized version of memset.
485 Such an implementation may be faster under some conditions
486 but may increase the binary size.
488 config SPL_USE_ARCH_MEMSET
489 bool "Use an assembly optimized implementation of memset for SPL"
490 default y if USE_ARCH_MEMSET
491 depends on !ARM64 && SPL
493 Enable the generation of an optimized version of memset.
494 Such an implementation may be faster under some conditions
495 but may increase the binary size.
497 config TPL_USE_ARCH_MEMSET
498 bool "Use an assembly optimized implementation of memset for TPL"
499 default y if USE_ARCH_MEMSET
500 depends on !ARM64 && TPL
502 Enable the generation of an optimized version of memset.
503 Such an implementation may be faster under some conditions
504 but may increase the binary size.
506 config SET_STACK_SIZE
507 bool "Enable an option to set max stack size that can be used"
508 default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ
510 This will enable an option to set max stack size that can be
514 hex "Define max stack size that can be used by U-Boot"
515 depends on SET_STACK_SIZE
516 default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
517 default 0x1000000 if ARCH_ZYNQ
519 Define Max stack size that can be used by U-Boot so that the
520 initrd_high will be calculated as base stack pointer minus this
523 config ARM64_SUPPORT_AARCH32
524 bool "ARM64 system support AArch32 execution state"
526 default y if !TARGET_THUNDERX_88XX
528 This ARM64 system supports AArch32 execution state.
531 prompt "Target select"
536 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
537 select SPL_SEPARATE_BSS if SPL
539 config TARGET_EDB93XX
540 bool "Support edb93xx"
544 config TARGET_ASPENITE
545 bool "Support aspenite"
549 bool "Support gplugd"
555 select SPL_DM_SPI if SPL
558 Support for TI's DaVinci platform.
561 bool "Marvell Kirkwood"
562 select ARCH_MISC_INIT
563 select BOARD_EARLY_INIT_F
567 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
573 select SPL_DM_SPI if SPL
574 select SPL_DM_SPI_FLASH if SPL
589 config TARGET_SPEAR300
590 bool "Support spear300"
591 select BOARD_EARLY_INIT_F
596 config TARGET_SPEAR310
597 bool "Support spear310"
598 select BOARD_EARLY_INIT_F
603 config TARGET_SPEAR320
604 bool "Support spear320"
605 select BOARD_EARLY_INIT_F
610 config TARGET_SPEAR600
611 bool "Support spear600"
612 select BOARD_EARLY_INIT_F
617 config TARGET_STV0991
618 bool "Support stv0991"
631 select BOARD_LATE_INIT
640 config TARGET_MX35PDK
641 bool "Support mx35pdk"
642 select BOARD_LATE_INIT
646 bool "Broadcom BCM283X family"
652 select SERIAL_SEARCH_ALL
657 bool "Broadcom BCM63158 family"
663 bool "Broadcom BCM68360 family"
669 bool "Broadcom BCM6858 family"
674 config TARGET_VEXPRESS_CA15_TC2
675 bool "Support vexpress_ca15_tc2"
677 select CPU_V7_HAS_NONSEC
678 select CPU_V7_HAS_VIRT
682 bool "Broadcom BCM7XXX family"
686 select OF_PRIOR_STAGE
689 This enables support for Broadcom ARM-based set-top box
690 chipsets, including the 7445 family of chips.
692 config TARGET_VEXPRESS_CA5X2
693 bool "Support vexpress_ca5x2"
697 config TARGET_VEXPRESS_CA9X4
698 bool "Support vexpress_ca9x4"
702 config TARGET_BCM23550_W1D
703 bool "Support bcm23550_w1d"
708 config TARGET_BCM28155_AP
709 bool "Support bcm28155_ap"
714 config TARGET_BCMCYGNUS
715 bool "Support bcmcygnus"
718 imply BCM_SF2_ETH_GMAC
726 bool "Support bcmnsp"
730 bool "Support Broadcom Northstar2"
733 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
734 ARMv8 Cortex-A57 processors targeting a broad range of networking
738 bool "Support Broadcom NS3"
740 select BOARD_LATE_INIT
742 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
743 ARMv8 Cortex-A72 processors targeting a broad range of networking
747 bool "Samsung EXYNOS"
756 imply SYS_THUMB_BUILD
761 bool "Samsung S5PC1XX"
770 bool "Calxeda Highbank"
774 config ARCH_INTEGRATOR
775 bool "ARM Ltd. Integrator family"
782 bool "Qualcomm IPQ40xx SoCs"
797 select SYS_ARCH_TIMER
798 select SYS_THUMB_BUILD
804 bool "Texas Instruments' K3 Architecture"
809 config ARCH_OMAP2PLUS
812 select SPL_BOARD_INIT if SPL
813 select SPL_STACK_R if SPL
819 imply DISTRO_DEFAULTS
822 Support for the Meson SoC family developed by Amlogic Inc.,
823 targeted at media players and tablet computers. We currently
824 support the S905 (GXBaby) 64-bit SoC.
831 select SPL_LIBCOMMON_SUPPORT if SPL
832 select SPL_LIBGENERIC_SUPPORT if SPL
833 select SPL_OF_CONTROL if SPL
836 Support for the MediaTek SoCs family developed by MediaTek Inc.
837 Please refer to doc/README.mediatek for more information.
840 bool "NXP LPC32xx platform"
850 bool "NXP i.MX8 platform"
854 select ENABLE_ARM_SOC_BOOT0_HOOK
857 bool "NXP i.MX8M platform"
864 bool "NXP i.MXRT platform"
872 bool "NXP i.MX23 family"
883 bool "NXP i.MX28 family"
889 bool "NXP i.MX31 family"
895 select ROM_UNIFIED_SECTIONS
897 imply SYS_THUMB_BUILD
901 select ARCH_MISC_INIT
903 select SYS_FSL_HAS_SEC if IMX_HAB
904 select SYS_FSL_SEC_COMPAT_4
905 select SYS_FSL_SEC_LE
906 imply BOARD_EARLY_INIT_F
908 imply SYS_THUMB_BUILD
913 select SYS_FSL_HAS_SEC
914 select SYS_FSL_SEC_COMPAT_4
915 select SYS_FSL_SEC_LE
917 imply SYS_THUMB_BUILD
921 default "arch/arm/mach-omap2/u-boot-spl.lds"
926 select BOARD_EARLY_INIT_F
931 bool "Nexell S5P4418/S5P6818 SoC"
932 select ENABLE_ARM_SOC_BOOT0_HOOK
936 bool "Actions Semi OWL SoCs"
944 select SYS_RELOC_GD_ENV_ADDR
948 bool "QEMU Virtual Platform"
949 select ARCH_SUPPORT_TFABOOT
959 bool "Renesas ARM SoCs"
960 select BOARD_EARLY_INIT_F if !RZA1
965 imply SYS_THUMB_BUILD
966 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
968 config TARGET_S32V234EVB
969 bool "Support s32v234evb"
971 select SYS_FSL_ERRATUM_ESDHC111
973 config ARCH_SNAPDRAGON
974 bool "Qualcomm Snapdragon SoCs"
987 bool "Altera SOCFPGA family"
988 select ARCH_EARLY_INIT_R
989 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
990 select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
991 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
994 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
996 select SPL_DM_RESET if DM_RESET
998 select SPL_LIBCOMMON_SUPPORT
999 select SPL_LIBGENERIC_SUPPORT
1000 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
1001 select SPL_OF_CONTROL
1002 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
1003 select SPL_SERIAL_SUPPORT
1005 select SPL_WATCHDOG_SUPPORT
1008 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1010 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1011 select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
1021 imply SPL_DM_SPI_FLASH
1022 imply SPL_LIBDISK_SUPPORT
1023 imply SPL_MMC_SUPPORT
1024 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1025 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1026 imply SPL_SPI_FLASH_SUPPORT
1027 imply SPL_SPI_SUPPORT
1031 bool "Support sunxi (Allwinner) SoCs"
1034 select CMD_MMC if MMC
1035 select CMD_USB if DISTRO_DEFAULTS
1041 select DM_MMC if MMC
1042 select DM_SCSI if SCSI
1044 select DM_USB if DISTRO_DEFAULTS
1045 select OF_BOARD_SETUP
1048 select SPECIFY_CONSOLE_INDEX
1049 select SPL_STACK_R if SPL
1050 select SPL_SYS_MALLOC_SIMPLE if SPL
1051 select SPL_SYS_THUMB_BUILD if !ARM64
1054 select SYS_THUMB_BUILD if !ARM64
1055 select USB if DISTRO_DEFAULTS
1056 select USB_KEYBOARD if DISTRO_DEFAULTS
1057 select USB_STORAGE if DISTRO_DEFAULTS
1058 select SPL_USE_TINY_PRINTF
1060 select SYS_RELOC_GD_ENV_ADDR
1063 imply CMD_UBI if MTD_RAW_NAND
1064 imply DISTRO_DEFAULTS
1067 imply OF_LIBFDT_OVERLAY
1068 imply PRE_CONSOLE_BUFFER
1069 imply SPL_GPIO_SUPPORT
1070 imply SPL_LIBCOMMON_SUPPORT
1071 imply SPL_LIBGENERIC_SUPPORT
1072 imply SPL_MMC_SUPPORT if MMC
1073 imply SPL_POWER_SUPPORT
1074 imply SPL_SERIAL_SUPPORT
1078 bool "ST-Ericsson U8500 Series"
1082 select DM_MMC if MMC
1084 select DM_USB if USB
1088 imply ARM_PL180_MMCI
1090 imply NOMADIK_MTU_TIMER
1093 imply SYSRESET_SYSCON
1096 bool "Support Xilinx Versal Platform"
1100 select DM_ETH if NET
1101 select DM_MMC if MMC
1104 imply BOARD_LATE_INIT
1107 bool "Freescale Vybrid"
1109 select SYS_FSL_ERRATUM_ESDHC111
1114 bool "Xilinx Zynq based platform"
1119 select DM_ETH if NET
1120 select DM_MMC if MMC
1124 select DM_USB if USB
1127 select SPL_BOARD_INIT if SPL
1128 select SPL_CLK if SPL
1129 select SPL_DM if SPL
1130 select SPL_DM_SPI if SPL
1131 select SPL_DM_SPI_FLASH if SPL
1132 select SPL_OF_CONTROL if SPL
1133 select SPL_SEPARATE_BSS if SPL
1135 imply ARCH_EARLY_INIT_R
1136 imply BOARD_LATE_INIT
1142 config ARCH_ZYNQMP_R5
1143 bool "Xilinx ZynqMP R5 based platform"
1147 select DM_ETH if NET
1148 select DM_MMC if MMC
1155 bool "Xilinx ZynqMP based platform"
1159 select DM_ETH if NET
1161 select DM_MMC if MMC
1163 select DM_SPI if SPI
1164 select DM_SPI_FLASH if DM_SPI
1165 select DM_USB if USB
1168 select SPL_BOARD_INIT if SPL
1169 select SPL_CLK if SPL
1170 select SPL_DM_SPI if SPI
1171 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1172 select SPL_DM_MAILBOX if SPL
1173 select SPL_FIRMWARE if SPL
1174 select SPL_SEPARATE_BSS if SPL
1177 imply BOARD_LATE_INIT
1185 imply DISTRO_DEFAULTS
1188 config TARGET_VEXPRESS64_AEMV8A
1189 bool "Support vexpress_aemv8a"
1193 config TARGET_VEXPRESS64_BASE_FVP
1194 bool "Support Versatile Express ARMv8a FVP BASE model"
1199 config TARGET_VEXPRESS64_JUNO
1200 bool "Support Versatile Express Juno Development Platform"
1215 config TARGET_LS2080A_EMU
1216 bool "Support ls2080a_emu"
1219 select ARMV8_MULTIENTRY
1220 select FSL_DDR_SYNC_REFRESH
1222 Support for Freescale LS2080A_EMU platform.
1223 The LS2080A Development System (EMULATOR) is a pre-silicon
1224 development platform that supports the QorIQ LS2080A
1225 Layerscape Architecture processor.
1227 config TARGET_LS2080A_SIMU
1228 bool "Support ls2080a_simu"
1231 select ARMV8_MULTIENTRY
1232 select BOARD_LATE_INIT
1234 Support for Freescale LS2080A_SIMU platform.
1235 The LS2080A Development System (QDS) is a pre silicon
1236 development platform that supports the QorIQ LS2080A
1237 Layerscape Architecture processor.
1239 config TARGET_LS1088AQDS
1240 bool "Support ls1088aqds"
1243 select ARMV8_MULTIENTRY
1244 select ARCH_SUPPORT_TFABOOT
1245 select BOARD_LATE_INIT
1247 select FSL_DDR_INTERACTIVE if !SD_BOOT
1249 Support for NXP LS1088AQDS platform.
1250 The LS1088A Development System (QDS) is a high-performance
1251 development platform that supports the QorIQ LS1088A
1252 Layerscape Architecture processor.
1254 config TARGET_LS2080AQDS
1255 bool "Support ls2080aqds"
1258 select ARMV8_MULTIENTRY
1259 select ARCH_SUPPORT_TFABOOT
1260 select BOARD_LATE_INIT
1265 select FSL_DDR_INTERACTIVE if !SPL
1267 Support for Freescale LS2080AQDS platform.
1268 The LS2080A Development System (QDS) is a high-performance
1269 development platform that supports the QorIQ LS2080A
1270 Layerscape Architecture processor.
1272 config TARGET_LS2080ARDB
1273 bool "Support ls2080ardb"
1276 select ARMV8_MULTIENTRY
1277 select ARCH_SUPPORT_TFABOOT
1278 select BOARD_LATE_INIT
1281 select FSL_DDR_INTERACTIVE if !SPL
1285 Support for Freescale LS2080ARDB platform.
1286 The LS2080A Reference design board (RDB) is a high-performance
1287 development platform that supports the QorIQ LS2080A
1288 Layerscape Architecture processor.
1290 config TARGET_LS2081ARDB
1291 bool "Support ls2081ardb"
1294 select ARMV8_MULTIENTRY
1295 select BOARD_LATE_INIT
1298 Support for Freescale LS2081ARDB platform.
1299 The LS2081A Reference design board (RDB) is a high-performance
1300 development platform that supports the QorIQ LS2081A/LS2041A
1301 Layerscape Architecture processor.
1303 config TARGET_LX2160ARDB
1304 bool "Support lx2160ardb"
1307 select ARMV8_MULTIENTRY
1308 select ARCH_SUPPORT_TFABOOT
1309 select BOARD_LATE_INIT
1311 Support for NXP LX2160ARDB platform.
1312 The lx2160ardb (LX2160A Reference design board (RDB)
1313 is a high-performance development platform that supports the
1314 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1316 config TARGET_LX2160AQDS
1317 bool "Support lx2160aqds"
1320 select ARMV8_MULTIENTRY
1321 select ARCH_SUPPORT_TFABOOT
1322 select BOARD_LATE_INIT
1324 Support for NXP LX2160AQDS platform.
1325 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1326 is a high-performance development platform that supports the
1327 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1330 bool "Support HiKey 96boards Consumer Edition Platform"
1337 select SPECIFY_CONSOLE_INDEX
1340 Support for HiKey 96boards platform. It features a HI6220
1341 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1343 config TARGET_HIKEY960
1344 bool "Support HiKey960 96boards Consumer Edition Platform"
1352 Support for HiKey960 96boards platform. It features a HI3660
1353 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1355 config TARGET_POPLAR
1356 bool "Support Poplar 96boards Enterprise Edition Platform"
1365 Support for Poplar 96boards EE platform. It features a HI3798cv200
1366 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1367 making it capable of running any commercial set-top solution based on
1370 config TARGET_LS1012AQDS
1371 bool "Support ls1012aqds"
1374 select ARCH_SUPPORT_TFABOOT
1375 select BOARD_LATE_INIT
1377 Support for Freescale LS1012AQDS platform.
1378 The LS1012A Development System (QDS) is a high-performance
1379 development platform that supports the QorIQ LS1012A
1380 Layerscape Architecture processor.
1382 config TARGET_LS1012ARDB
1383 bool "Support ls1012ardb"
1386 select ARCH_SUPPORT_TFABOOT
1387 select BOARD_LATE_INIT
1391 Support for Freescale LS1012ARDB platform.
1392 The LS1012A Reference design board (RDB) is a high-performance
1393 development platform that supports the QorIQ LS1012A
1394 Layerscape Architecture processor.
1396 config TARGET_LS1012A2G5RDB
1397 bool "Support ls1012a2g5rdb"
1400 select ARCH_SUPPORT_TFABOOT
1401 select BOARD_LATE_INIT
1404 Support for Freescale LS1012A2G5RDB platform.
1405 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1406 development platform that supports the QorIQ LS1012A
1407 Layerscape Architecture processor.
1409 config TARGET_LS1012AFRWY
1410 bool "Support ls1012afrwy"
1413 select ARCH_SUPPORT_TFABOOT
1414 select BOARD_LATE_INIT
1418 Support for Freescale LS1012AFRWY platform.
1419 The LS1012A FRWY board (FRWY) is a high-performance
1420 development platform that supports the QorIQ LS1012A
1421 Layerscape Architecture processor.
1423 config TARGET_LS1012AFRDM
1424 bool "Support ls1012afrdm"
1427 select ARCH_SUPPORT_TFABOOT
1429 Support for Freescale LS1012AFRDM platform.
1430 The LS1012A Freedom board (FRDM) is a high-performance
1431 development platform that supports the QorIQ LS1012A
1432 Layerscape Architecture processor.
1434 config TARGET_LS1028AQDS
1435 bool "Support ls1028aqds"
1438 select ARMV8_MULTIENTRY
1439 select ARCH_SUPPORT_TFABOOT
1440 select BOARD_LATE_INIT
1442 Support for Freescale LS1028AQDS platform
1443 The LS1028A Development System (QDS) is a high-performance
1444 development platform that supports the QorIQ LS1028A
1445 Layerscape Architecture processor.
1447 config TARGET_LS1028ARDB
1448 bool "Support ls1028ardb"
1451 select ARMV8_MULTIENTRY
1452 select ARCH_SUPPORT_TFABOOT
1453 select BOARD_LATE_INIT
1455 Support for Freescale LS1028ARDB platform
1456 The LS1028A Development System (RDB) is a high-performance
1457 development platform that supports the QorIQ LS1028A
1458 Layerscape Architecture processor.
1460 config TARGET_LS1088ARDB
1461 bool "Support ls1088ardb"
1464 select ARMV8_MULTIENTRY
1465 select ARCH_SUPPORT_TFABOOT
1466 select BOARD_LATE_INIT
1468 select FSL_DDR_INTERACTIVE if !SD_BOOT
1470 Support for NXP LS1088ARDB platform.
1471 The LS1088A Reference design board (RDB) is a high-performance
1472 development platform that supports the QorIQ LS1088A
1473 Layerscape Architecture processor.
1475 config TARGET_LS1021AQDS
1476 bool "Support ls1021aqds"
1478 select ARCH_SUPPORT_PSCI
1479 select BOARD_EARLY_INIT_F
1480 select BOARD_LATE_INIT
1482 select CPU_V7_HAS_NONSEC
1483 select CPU_V7_HAS_VIRT
1484 select LS1_DEEP_SLEEP
1487 select FSL_DDR_INTERACTIVE
1488 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1489 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1492 config TARGET_LS1021ATWR
1493 bool "Support ls1021atwr"
1495 select ARCH_SUPPORT_PSCI
1496 select BOARD_EARLY_INIT_F
1497 select BOARD_LATE_INIT
1499 select CPU_V7_HAS_NONSEC
1500 select CPU_V7_HAS_VIRT
1501 select LS1_DEEP_SLEEP
1503 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1506 config TARGET_LS1021ATSN
1507 bool "Support ls1021atsn"
1509 select ARCH_SUPPORT_PSCI
1510 select BOARD_EARLY_INIT_F
1511 select BOARD_LATE_INIT
1513 select CPU_V7_HAS_NONSEC
1514 select CPU_V7_HAS_VIRT
1515 select LS1_DEEP_SLEEP
1519 config TARGET_LS1021AIOT
1520 bool "Support ls1021aiot"
1522 select ARCH_SUPPORT_PSCI
1523 select BOARD_LATE_INIT
1525 select CPU_V7_HAS_NONSEC
1526 select CPU_V7_HAS_VIRT
1528 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1531 Support for Freescale LS1021AIOT platform.
1532 The LS1021A Freescale board (IOT) is a high-performance
1533 development platform that supports the QorIQ LS1021A
1534 Layerscape Architecture processor.
1536 config TARGET_LS1043AQDS
1537 bool "Support ls1043aqds"
1540 select ARMV8_MULTIENTRY
1541 select ARCH_SUPPORT_TFABOOT
1542 select BOARD_EARLY_INIT_F
1543 select BOARD_LATE_INIT
1545 select FSL_DDR_INTERACTIVE if !SPL
1546 select FSL_DSPI if !SPL_NO_DSPI
1547 select DM_SPI_FLASH if FSL_DSPI
1551 Support for Freescale LS1043AQDS platform.
1553 config TARGET_LS1043ARDB
1554 bool "Support ls1043ardb"
1557 select ARMV8_MULTIENTRY
1558 select ARCH_SUPPORT_TFABOOT
1559 select BOARD_EARLY_INIT_F
1560 select BOARD_LATE_INIT
1562 select FSL_DSPI if !SPL_NO_DSPI
1563 select DM_SPI_FLASH if FSL_DSPI
1565 Support for Freescale LS1043ARDB platform.
1567 config TARGET_LS1046AQDS
1568 bool "Support ls1046aqds"
1571 select ARMV8_MULTIENTRY
1572 select ARCH_SUPPORT_TFABOOT
1573 select BOARD_EARLY_INIT_F
1574 select BOARD_LATE_INIT
1575 select DM_SPI_FLASH if DM_SPI
1577 select FSL_DDR_BIST if !SPL
1578 select FSL_DDR_INTERACTIVE if !SPL
1579 select FSL_DDR_INTERACTIVE if !SPL
1582 Support for Freescale LS1046AQDS platform.
1583 The LS1046A Development System (QDS) is a high-performance
1584 development platform that supports the QorIQ LS1046A
1585 Layerscape Architecture processor.
1587 config TARGET_LS1046ARDB
1588 bool "Support ls1046ardb"
1591 select ARMV8_MULTIENTRY
1592 select ARCH_SUPPORT_TFABOOT
1593 select BOARD_EARLY_INIT_F
1594 select BOARD_LATE_INIT
1595 select DM_SPI_FLASH if DM_SPI
1596 select POWER_MC34VR500
1599 select FSL_DDR_INTERACTIVE if !SPL
1602 Support for Freescale LS1046ARDB platform.
1603 The LS1046A Reference Design Board (RDB) is a high-performance
1604 development platform that supports the QorIQ LS1046A
1605 Layerscape Architecture processor.
1607 config TARGET_LS1046AFRWY
1608 bool "Support ls1046afrwy"
1611 select ARMV8_MULTIENTRY
1612 select ARCH_SUPPORT_TFABOOT
1613 select BOARD_EARLY_INIT_F
1614 select BOARD_LATE_INIT
1615 select DM_SPI_FLASH if DM_SPI
1618 Support for Freescale LS1046AFRWY platform.
1619 The LS1046A Freeway Board (FRWY) is a high-performance
1620 development platform that supports the QorIQ LS1046A
1621 Layerscape Architecture processor.
1623 config TARGET_COLIBRI_PXA270
1624 bool "Support colibri_pxa270"
1627 config ARCH_UNIPHIER
1628 bool "Socionext UniPhier SoCs"
1629 select BOARD_LATE_INIT
1639 select OF_BOARD_SETUP
1643 select SPL_BOARD_INIT if SPL
1644 select SPL_DM if SPL
1645 select SPL_LIBCOMMON_SUPPORT if SPL
1646 select SPL_LIBGENERIC_SUPPORT if SPL
1647 select SPL_OF_CONTROL if SPL
1648 select SPL_PINCTRL if SPL
1651 imply DISTRO_DEFAULTS
1654 Support for UniPhier SoC family developed by Socionext Inc.
1655 (formerly, System LSI Business Division of Panasonic Corporation)
1658 bool "Support STMicroelectronics STM32 MCU with cortex M"
1665 bool "Support STMicrolectronics SoCs"
1674 Support for STMicroelectronics STiH407/10 SoC family.
1675 This SoC is used on Linaro 96Board STiH410-B2260
1678 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1679 select ARCH_MISC_INIT
1680 select ARCH_SUPPORT_TFABOOT
1681 select BOARD_LATE_INIT
1690 select OF_SYSTEM_SETUP
1696 select SYS_THUMB_BUILD
1700 imply OF_LIBFDT_OVERLAY
1701 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1704 Support for STM32MP SoC family developed by STMicroelectronics,
1705 MPUs based on ARM cortex A core
1706 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1707 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1709 SPL is the unsecure FSBL for the basic boot chain.
1711 config ARCH_ROCKCHIP
1712 bool "Support Rockchip SoCs"
1714 select BINMAN if !ARM64
1724 select DM_USB if USB
1725 select ENABLE_ARM_SOC_BOOT0_HOOK
1728 select SPL_DM if SPL
1729 select SPL_DM_SPI if SPL
1730 select SPL_DM_SPI_FLASH if SPL
1732 select SYS_THUMB_BUILD if !ARM64
1735 imply DEBUG_UART_BOARD_INIT
1736 imply DISTRO_DEFAULTS
1738 imply SARADC_ROCKCHIP
1740 imply SPL_SYS_MALLOC_SIMPLE
1743 imply USB_FUNCTION_FASTBOOT
1745 config TARGET_THUNDERX_88XX
1746 bool "Support ThunderX 88xx"
1750 select SYS_CACHE_SHIFT_7
1753 bool "Support Aspeed SoCs"
1758 config TARGET_DURIAN
1759 bool "Support Phytium Durian Platform"
1762 Support for durian platform.
1763 It has 2GB Sdram, uart and pcie.
1765 config TARGET_PRESIDIO_ASIC
1766 bool "Support Cortina Presidio ASIC Platform"
1771 config ARCH_SUPPORT_TFABOOT
1775 bool "Support for booting from TF-A"
1776 depends on ARCH_SUPPORT_TFABOOT
1779 Enabling this will make a U-Boot binary that is capable of being
1780 booted via TF-A (Trusted Firmware for Cortex-A).
1782 config TI_SECURE_DEVICE
1783 bool "HS Device Type Support"
1784 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1786 If a high secure (HS) device type is being used, this config
1787 must be set. This option impacts various aspects of the
1788 build system (to create signed boot images that can be
1789 authenticated) and the code. See the doc/README.ti-secure
1790 file for further details.
1792 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1793 config ISW_ENTRY_ADDR
1794 hex "Address in memory or XIP address of bootloader entry point"
1795 default 0x402F4000 if AM43XX
1796 default 0x402F0400 if AM33XX
1797 default 0x40301350 if OMAP54XX
1799 After any reset, the boot ROM searches the boot media for a valid
1800 boot image. For non-XIP devices, the ROM then copies the image into
1801 internal memory. For all boot modes, after the ROM processes the
1802 boot image it eventually computes the entry point address depending
1803 on the device type (secure/non-secure), boot media (xip/non-xip) and
1807 source "arch/arm/mach-aspeed/Kconfig"
1809 source "arch/arm/mach-at91/Kconfig"
1811 source "arch/arm/mach-bcm283x/Kconfig"
1813 source "arch/arm/mach-bcmstb/Kconfig"
1815 source "arch/arm/mach-davinci/Kconfig"
1817 source "arch/arm/mach-exynos/Kconfig"
1819 source "arch/arm/mach-highbank/Kconfig"
1821 source "arch/arm/mach-integrator/Kconfig"
1823 source "arch/arm/mach-ipq40xx/Kconfig"
1825 source "arch/arm/mach-k3/Kconfig"
1827 source "arch/arm/mach-keystone/Kconfig"
1829 source "arch/arm/mach-kirkwood/Kconfig"
1831 source "arch/arm/mach-lpc32xx/Kconfig"
1833 source "arch/arm/mach-mvebu/Kconfig"
1835 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1837 source "arch/arm/mach-imx/mx2/Kconfig"
1839 source "arch/arm/mach-imx/mx3/Kconfig"
1841 source "arch/arm/mach-imx/mx5/Kconfig"
1843 source "arch/arm/mach-imx/mx6/Kconfig"
1845 source "arch/arm/mach-imx/mx7/Kconfig"
1847 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1849 source "arch/arm/mach-imx/imx8/Kconfig"
1851 source "arch/arm/mach-imx/imx8m/Kconfig"
1853 source "arch/arm/mach-imx/imxrt/Kconfig"
1855 source "arch/arm/mach-imx/mxs/Kconfig"
1857 source "arch/arm/mach-omap2/Kconfig"
1859 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1861 source "arch/arm/mach-orion5x/Kconfig"
1863 source "arch/arm/mach-owl/Kconfig"
1865 source "arch/arm/mach-rmobile/Kconfig"
1867 source "arch/arm/mach-meson/Kconfig"
1869 source "arch/arm/mach-mediatek/Kconfig"
1871 source "arch/arm/mach-qemu/Kconfig"
1873 source "arch/arm/mach-rockchip/Kconfig"
1875 source "arch/arm/mach-s5pc1xx/Kconfig"
1877 source "arch/arm/mach-snapdragon/Kconfig"
1879 source "arch/arm/mach-socfpga/Kconfig"
1881 source "arch/arm/mach-sti/Kconfig"
1883 source "arch/arm/mach-stm32/Kconfig"
1885 source "arch/arm/mach-stm32mp/Kconfig"
1887 source "arch/arm/mach-sunxi/Kconfig"
1889 source "arch/arm/mach-tegra/Kconfig"
1891 source "arch/arm/mach-u8500/Kconfig"
1893 source "arch/arm/mach-uniphier/Kconfig"
1895 source "arch/arm/cpu/armv7/vf610/Kconfig"
1897 source "arch/arm/mach-zynq/Kconfig"
1899 source "arch/arm/mach-zynqmp/Kconfig"
1901 source "arch/arm/mach-versal/Kconfig"
1903 source "arch/arm/mach-zynqmp-r5/Kconfig"
1905 source "arch/arm/cpu/armv7/Kconfig"
1907 source "arch/arm/cpu/armv8/Kconfig"
1909 source "arch/arm/mach-imx/Kconfig"
1911 source "arch/arm/mach-nexell/Kconfig"
1913 source "board/bosch/shc/Kconfig"
1914 source "board/bosch/guardian/Kconfig"
1915 source "board/CarMediaLab/flea3/Kconfig"
1916 source "board/Marvell/aspenite/Kconfig"
1917 source "board/Marvell/gplugd/Kconfig"
1918 source "board/armadeus/apf27/Kconfig"
1919 source "board/armltd/vexpress/Kconfig"
1920 source "board/armltd/vexpress64/Kconfig"
1921 source "board/cortina/presidio-asic/Kconfig"
1922 source "board/broadcom/bcm23550_w1d/Kconfig"
1923 source "board/broadcom/bcm28155_ap/Kconfig"
1924 source "board/broadcom/bcm963158/Kconfig"
1925 source "board/broadcom/bcm968360bg/Kconfig"
1926 source "board/broadcom/bcm968580xref/Kconfig"
1927 source "board/broadcom/bcmcygnus/Kconfig"
1928 source "board/broadcom/bcmnsp/Kconfig"
1929 source "board/broadcom/bcmns2/Kconfig"
1930 source "board/broadcom/bcmns3/Kconfig"
1931 source "board/cavium/thunderx/Kconfig"
1932 source "board/cirrus/edb93xx/Kconfig"
1933 source "board/eets/pdu001/Kconfig"
1934 source "board/emulation/qemu-arm/Kconfig"
1935 source "board/freescale/ls2080a/Kconfig"
1936 source "board/freescale/ls2080aqds/Kconfig"
1937 source "board/freescale/ls2080ardb/Kconfig"
1938 source "board/freescale/ls1088a/Kconfig"
1939 source "board/freescale/ls1028a/Kconfig"
1940 source "board/freescale/ls1021aqds/Kconfig"
1941 source "board/freescale/ls1043aqds/Kconfig"
1942 source "board/freescale/ls1021atwr/Kconfig"
1943 source "board/freescale/ls1021atsn/Kconfig"
1944 source "board/freescale/ls1021aiot/Kconfig"
1945 source "board/freescale/ls1046aqds/Kconfig"
1946 source "board/freescale/ls1043ardb/Kconfig"
1947 source "board/freescale/ls1046ardb/Kconfig"
1948 source "board/freescale/ls1046afrwy/Kconfig"
1949 source "board/freescale/ls1012aqds/Kconfig"
1950 source "board/freescale/ls1012ardb/Kconfig"
1951 source "board/freescale/ls1012afrdm/Kconfig"
1952 source "board/freescale/lx2160a/Kconfig"
1953 source "board/freescale/mx35pdk/Kconfig"
1954 source "board/freescale/s32v234evb/Kconfig"
1955 source "board/grinn/chiliboard/Kconfig"
1956 source "board/hisilicon/hikey/Kconfig"
1957 source "board/hisilicon/hikey960/Kconfig"
1958 source "board/hisilicon/poplar/Kconfig"
1959 source "board/isee/igep003x/Kconfig"
1960 source "board/spear/spear300/Kconfig"
1961 source "board/spear/spear310/Kconfig"
1962 source "board/spear/spear320/Kconfig"
1963 source "board/spear/spear600/Kconfig"
1964 source "board/spear/x600/Kconfig"
1965 source "board/st/stv0991/Kconfig"
1966 source "board/tcl/sl50/Kconfig"
1967 source "board/toradex/colibri_pxa270/Kconfig"
1968 source "board/variscite/dart_6ul/Kconfig"
1969 source "board/vscom/baltos/Kconfig"
1970 source "board/xilinx/Kconfig"
1971 source "board/xilinx/zynq/Kconfig"
1972 source "board/xilinx/zynqmp/Kconfig"
1973 source "board/phytium/durian/Kconfig"
1975 source "arch/arm/Kconfig.debug"
1980 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
1981 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
1982 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64