4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_WANT_IPC_PARSE_VERSION
9 select BUILDTIME_EXTABLE_SORT if MMU
10 select CLONE_BACKWARDS
11 select CPU_PM if (SUSPEND || CPU_IDLE)
12 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
13 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
14 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
15 select GENERIC_IDLE_POLL_SETUP
16 select GENERIC_IRQ_PROBE
17 select GENERIC_IRQ_SHOW
18 select GENERIC_PCI_IOMAP
19 select GENERIC_SCHED_CLOCK
20 select GENERIC_SMP_IDLE_THREAD
21 select GENERIC_STRNCPY_FROM_USER
22 select GENERIC_STRNLEN_USER
23 select HARDIRQS_SW_RESEND
24 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
26 select HAVE_ARCH_SECCOMP_FILTER
27 select HAVE_ARCH_TRACEHOOK
29 select HAVE_CONTEXT_TRACKING
30 select HAVE_C_RECORDMCOUNT
31 select HAVE_DEBUG_KMEMLEAK
32 select HAVE_DMA_API_DEBUG
34 select HAVE_DMA_CONTIGUOUS if MMU
35 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
36 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
37 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
38 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
39 select HAVE_GENERIC_DMA_COHERENT
40 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
41 select HAVE_IDE if PCI || ISA || PCMCIA
42 select HAVE_IRQ_TIME_ACCOUNTING
43 select HAVE_KERNEL_GZIP
44 select HAVE_KERNEL_LZ4
45 select HAVE_KERNEL_LZMA
46 select HAVE_KERNEL_LZO
48 select HAVE_KPROBES if !XIP_KERNEL
49 select HAVE_KRETPROBES if (HAVE_KPROBES)
51 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
52 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
53 select HAVE_PERF_EVENTS
54 select HAVE_REGS_AND_STACK_ACCESS_API
55 select HAVE_SYSCALL_TRACEPOINTS
57 select IRQ_FORCED_THREADING
59 select MODULES_USE_ELF_REL
61 select OLD_SIGSUSPEND3
62 select PERF_USE_VMALLOC
64 select SYS_SUPPORTS_APM_EMULATION
65 # Above selects are sorted alphabetically; please add new ones
66 # according to that. Thanks.
68 The ARM series is a line of low-power-consumption RISC chip designs
69 licensed by ARM Ltd and targeted at embedded applications and
70 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
71 manufactured, but legacy ARM-based PC hardware remains popular in
72 Europe. There is an ARM Linux project with a web page at
73 <http://www.arm.linux.org.uk/>.
75 config ARM_HAS_SG_CHAIN
78 config NEED_SG_DMA_LENGTH
81 config ARM_DMA_USE_IOMMU
83 select ARM_HAS_SG_CHAIN
84 select NEED_SG_DMA_LENGTH
88 config ARM_DMA_IOMMU_ALIGNMENT
89 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
93 DMA mapping framework by default aligns all buffers to the smallest
94 PAGE_SIZE order which is greater than or equal to the requested buffer
95 size. This works well for buffers up to a few hundreds kilobytes, but
96 for larger buffers it just a waste of address space. Drivers which has
97 relatively small addressing window (like 64Mib) might run out of
98 virtual space with just a few allocations.
100 With this parameter you can specify the maximum PAGE_SIZE order for
101 DMA IOMMU buffers. Larger buffers will be aligned only to this
102 specified order. The order is expressed as a power of two multiplied
110 config MIGHT_HAVE_PCI
113 config SYS_SUPPORTS_APM_EMULATION
118 select GENERIC_ALLOCATOR
129 The Extended Industry Standard Architecture (EISA) bus was
130 developed as an open alternative to the IBM MicroChannel bus.
132 The EISA bus provided some of the features of the IBM MicroChannel
133 bus while maintaining backward compatibility with cards made for
134 the older ISA bus. The EISA bus saw limited use between 1988 and
135 1995 when it was made obsolete by the PCI bus.
137 Say Y here if you are building a kernel for an EISA-based machine.
144 config STACKTRACE_SUPPORT
148 config HAVE_LATENCYTOP_SUPPORT
153 config LOCKDEP_SUPPORT
157 config TRACE_IRQFLAGS_SUPPORT
161 config RWSEM_GENERIC_SPINLOCK
165 config RWSEM_XCHGADD_ALGORITHM
168 config ARCH_HAS_ILOG2_U32
171 config ARCH_HAS_ILOG2_U64
174 config ARCH_HAS_CPUFREQ
177 Internal node to signify that the ARCH has CPUFREQ support
178 and that the relevant menu configurations are displayed for
181 config ARCH_HAS_BANDGAP
184 config GENERIC_HWEIGHT
188 config GENERIC_CALIBRATE_DELAY
192 config ARCH_MAY_HAVE_PC_FDC
198 config NEED_DMA_MAP_STATE
201 config ARCH_HAS_DMA_SET_COHERENT_MASK
204 config GENERIC_ISA_DMA
210 config NEED_RET_TO_USER
218 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
219 default DRAM_BASE if REMAP_VECTORS_TO_RAM
222 The base address of exception vectors. This must be two pages
225 config ARM_PATCH_PHYS_VIRT
226 bool "Patch physical to virtual translations at runtime" if EMBEDDED
228 depends on !XIP_KERNEL && MMU
229 depends on !ARCH_REALVIEW || !SPARSEMEM
231 Patch phys-to-virt and virt-to-phys translation functions at
232 boot and module load time according to the position of the
233 kernel in system memory.
235 This can only be used with non-XIP MMU kernels where the base
236 of physical memory is at a 16MB boundary.
238 Only disable this option if you know that you do not require
239 this feature (eg, building a kernel for a single machine) and
240 you need to shrink the kernel to the minimal size.
242 config NEED_MACH_GPIO_H
245 Select this when mach/gpio.h is required to provide special
246 definitions for this platform. The need for mach/gpio.h should
247 be avoided when possible.
249 config NEED_MACH_IO_H
252 Select this when mach/io.h is required to provide special
253 definitions for this platform. The need for mach/io.h should
254 be avoided when possible.
256 config NEED_MACH_MEMORY_H
259 Select this when mach/memory.h is required to provide special
260 definitions for this platform. The need for mach/memory.h should
261 be avoided when possible.
264 hex "Physical address of main memory" if MMU
265 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
266 default DRAM_BASE if !MMU
268 Please provide the physical address corresponding to the
269 location of main memory in your system.
275 source "init/Kconfig"
277 source "kernel/Kconfig.freezer"
282 bool "MMU-based Paged Memory Management Support"
285 Select if you want MMU-based virtualised addressing space
286 support by paged memory management. If unsure, say 'Y'.
289 # The "ARM system type" choice list is ordered alphabetically by option
290 # text. Please add new entries in the option alphabetic order.
293 prompt "ARM system type"
294 default ARCH_VERSATILE if !MMU
295 default ARCH_MULTIPLATFORM if MMU
297 config ARCH_MULTIPLATFORM
298 bool "Allow multiple platforms to be selected"
300 select ARM_PATCH_PHYS_VIRT
303 select MULTI_IRQ_HANDLER
307 config ARCH_INTEGRATOR
308 bool "ARM Ltd. Integrator family"
309 select ARCH_HAS_CPUFREQ
312 select COMMON_CLK_VERSATILE
313 select GENERIC_CLOCKEVENTS
316 select MULTI_IRQ_HANDLER
317 select NEED_MACH_MEMORY_H
318 select PLAT_VERSATILE
320 select VERSATILE_FPGA_IRQ
322 Support for ARM's Integrator platform.
325 bool "ARM Ltd. RealView family"
326 select ARCH_WANT_OPTIONAL_GPIOLIB
328 select ARM_TIMER_SP804
330 select COMMON_CLK_VERSATILE
331 select GENERIC_CLOCKEVENTS
332 select GPIO_PL061 if GPIOLIB
334 select NEED_MACH_MEMORY_H
335 select PLAT_VERSATILE
336 select PLAT_VERSATILE_CLCD
338 This enables support for ARM Ltd RealView boards.
340 config ARCH_VERSATILE
341 bool "ARM Ltd. Versatile family"
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_TIMER_SP804
347 select GENERIC_CLOCKEVENTS
348 select HAVE_MACH_CLKDEV
350 select PLAT_VERSATILE
351 select PLAT_VERSATILE_CLCD
352 select PLAT_VERSATILE_CLOCK
353 select VERSATILE_FPGA_IRQ
355 This enables support for ARM Ltd Versatile board.
359 select ARCH_REQUIRE_GPIOLIB
362 select NEED_MACH_GPIO_H
363 select NEED_MACH_IO_H if PCCARD
365 select PINCTRL_AT91 if USE_OF
367 This enables support for systems based on Atmel
368 AT91RM9200 and AT91SAM9* processors.
371 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
372 select ARCH_REQUIRE_GPIOLIB
377 select GENERIC_CLOCKEVENTS
379 select MULTI_IRQ_HANDLER
382 Support for Cirrus Logic 711x/721x/731x based boards.
385 bool "Cortina Systems Gemini"
386 select ARCH_REQUIRE_GPIOLIB
387 select ARCH_USES_GETTIMEOFFSET
389 select NEED_MACH_GPIO_H
391 Support for the Cortina Systems Gemini family SoCs
395 select ARCH_USES_GETTIMEOFFSET
398 select NEED_MACH_IO_H
399 select NEED_MACH_MEMORY_H
402 This is an evaluation board for the StrongARM processor available
403 from Digital. It has limited hardware on-board, including an
404 Ethernet interface, two PCMCIA sockets, two serial ports and a
409 select ARCH_HAS_HOLES_MEMORYMODEL
410 select ARCH_REQUIRE_GPIOLIB
411 select ARCH_USES_GETTIMEOFFSET
416 select NEED_MACH_MEMORY_H
418 This enables support for the Cirrus EP93xx series of CPUs.
420 config ARCH_FOOTBRIDGE
424 select GENERIC_CLOCKEVENTS
426 select NEED_MACH_IO_H if !MMU
427 select NEED_MACH_MEMORY_H
429 Support for systems based on the DC21285 companion chip
430 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
433 bool "Hilscher NetX based"
437 select GENERIC_CLOCKEVENTS
439 This enables support for systems based on the Hilscher NetX Soc
445 select NEED_MACH_MEMORY_H
446 select NEED_RET_TO_USER
451 Support for Intel's IOP13XX (XScale) family of processors.
456 select ARCH_REQUIRE_GPIOLIB
458 select NEED_MACH_GPIO_H
459 select NEED_RET_TO_USER
463 Support for Intel's 80219 and IOP32X (XScale) family of
469 select ARCH_REQUIRE_GPIOLIB
471 select NEED_MACH_GPIO_H
472 select NEED_RET_TO_USER
476 Support for Intel's IOP33X (XScale) family of processors.
481 select ARCH_HAS_DMA_SET_COHERENT_MASK
482 select ARCH_REQUIRE_GPIOLIB
485 select DMABOUNCE if PCI
486 select GENERIC_CLOCKEVENTS
487 select MIGHT_HAVE_PCI
488 select NEED_MACH_IO_H
489 select USB_EHCI_BIG_ENDIAN_DESC
490 select USB_EHCI_BIG_ENDIAN_MMIO
492 Support for Intel's IXP4XX (XScale) family of processors.
496 select ARCH_REQUIRE_GPIOLIB
498 select GENERIC_CLOCKEVENTS
499 select MIGHT_HAVE_PCI
503 select PLAT_ORION_LEGACY
504 select USB_ARCH_HAS_EHCI
506 Support for the Marvell Dove SoC 88AP510
509 bool "Marvell Kirkwood"
510 select ARCH_HAS_CPUFREQ
511 select ARCH_REQUIRE_GPIOLIB
513 select GENERIC_CLOCKEVENTS
518 select PINCTRL_KIRKWOOD
519 select PLAT_ORION_LEGACY
521 Support for the following Marvell Kirkwood series SoCs:
522 88F6180, 88F6192 and 88F6281.
525 bool "Marvell MV78xx0"
526 select ARCH_REQUIRE_GPIOLIB
528 select GENERIC_CLOCKEVENTS
531 select PLAT_ORION_LEGACY
533 Support for the following Marvell MV78xx0 series SoCs:
539 select ARCH_REQUIRE_GPIOLIB
541 select GENERIC_CLOCKEVENTS
544 select PLAT_ORION_LEGACY
546 Support for the following Marvell Orion 5x series SoCs:
547 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
548 Orion-2 (5281), Orion-1-90 (6183).
551 bool "Marvell PXA168/910/MMP2"
553 select ARCH_REQUIRE_GPIOLIB
555 select GENERIC_ALLOCATOR
556 select GENERIC_CLOCKEVENTS
559 select MULTI_IRQ_HANDLER
560 select NEED_MACH_GPIO_H
565 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
568 bool "Micrel/Kendin KS8695"
569 select ARCH_REQUIRE_GPIOLIB
572 select GENERIC_CLOCKEVENTS
573 select NEED_MACH_MEMORY_H
575 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
576 System-on-Chip devices.
579 bool "Nuvoton W90X900 CPU"
580 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
586 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
587 At present, the w90x900 has been renamed nuc900, regarding
588 the ARM series product line, you can login the following
589 link address to know more.
591 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
592 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
596 select ARCH_REQUIRE_GPIOLIB
601 select GENERIC_CLOCKEVENTS
604 select USB_ARCH_HAS_OHCI
607 Support for the NXP LPC32XX family of processors
610 bool "PXA2xx/PXA3xx-based"
612 select ARCH_HAS_CPUFREQ
614 select ARCH_REQUIRE_GPIOLIB
615 select ARM_CPU_SUSPEND if PM
619 select GENERIC_CLOCKEVENTS
622 select MULTI_IRQ_HANDLER
623 select NEED_MACH_GPIO_H
627 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
631 select ARCH_REQUIRE_GPIOLIB
632 select CLKSRC_OF if OF
634 select GENERIC_CLOCKEVENTS
636 Support for Qualcomm MSM/QSD based systems. This runs on the
637 apps processor of the MSM/QSD and depends on a shared memory
638 interface to the modem processor which runs the baseband
639 stack and controls some vital subsystems
640 (clock and power control, etc).
643 bool "Renesas SH-Mobile / R-Mobile"
644 select ARM_PATCH_PHYS_VIRT
646 select GENERIC_CLOCKEVENTS
647 select HAVE_ARM_SCU if SMP
648 select HAVE_ARM_TWD if SMP
649 select HAVE_MACH_CLKDEV
651 select MIGHT_HAVE_CACHE_L2X0
652 select MULTI_IRQ_HANDLER
655 select PM_GENERIC_DOMAINS if PM
658 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
663 select ARCH_MAY_HAVE_PC_FDC
664 select ARCH_SPARSEMEM_ENABLE
665 select ARCH_USES_GETTIMEOFFSET
668 select HAVE_PATA_PLATFORM
670 select NEED_MACH_IO_H
671 select NEED_MACH_MEMORY_H
675 On the Acorn Risc-PC, Linux can support the internal IDE disk and
676 CD-ROM interface, serial and parallel port, and the floppy drive.
680 select ARCH_HAS_CPUFREQ
682 select ARCH_REQUIRE_GPIOLIB
683 select ARCH_SPARSEMEM_ENABLE
688 select GENERIC_CLOCKEVENTS
691 select NEED_MACH_GPIO_H
692 select NEED_MACH_MEMORY_H
695 Support for StrongARM 11x0 based boards.
698 bool "Samsung S3C24XX SoCs"
699 select ARCH_HAS_CPUFREQ
700 select ARCH_REQUIRE_GPIOLIB
702 select CLKSRC_SAMSUNG_PWM
703 select GENERIC_CLOCKEVENTS
705 select HAVE_S3C2410_I2C if I2C
706 select HAVE_S3C2410_WATCHDOG if WATCHDOG
707 select HAVE_S3C_RTC if RTC_CLASS
708 select MULTI_IRQ_HANDLER
709 select NEED_MACH_GPIO_H
710 select NEED_MACH_IO_H
713 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
714 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
715 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
716 Samsung SMDK2410 development board (and derivatives).
719 bool "Samsung S3C64XX"
720 select ARCH_HAS_CPUFREQ
721 select ARCH_REQUIRE_GPIOLIB
724 select CLKSRC_SAMSUNG_PWM
726 select GENERIC_CLOCKEVENTS
728 select HAVE_S3C2410_I2C if I2C
729 select HAVE_S3C2410_WATCHDOG if WATCHDOG
731 select NEED_MACH_GPIO_H
735 select S3C_GPIO_TRACK
737 select SAMSUNG_CLKSRC
738 select SAMSUNG_GPIOLIB_4BIT
739 select SAMSUNG_WDT_RESET
740 select USB_ARCH_HAS_OHCI
742 Samsung S3C64XX series based systems
745 bool "Samsung S5P6440 S5P6450"
747 select CLKSRC_SAMSUNG_PWM
749 select GENERIC_CLOCKEVENTS
751 select HAVE_S3C2410_I2C if I2C
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
753 select HAVE_S3C_RTC if RTC_CLASS
754 select NEED_MACH_GPIO_H
756 select SAMSUNG_WDT_RESET
758 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
762 bool "Samsung S5PC100"
763 select ARCH_REQUIRE_GPIOLIB
765 select CLKSRC_SAMSUNG_PWM
767 select GENERIC_CLOCKEVENTS
769 select HAVE_S3C2410_I2C if I2C
770 select HAVE_S3C2410_WATCHDOG if WATCHDOG
771 select HAVE_S3C_RTC if RTC_CLASS
772 select NEED_MACH_GPIO_H
774 select SAMSUNG_WDT_RESET
776 Samsung S5PC100 series based systems
779 bool "Samsung S5PV210/S5PC110"
780 select ARCH_HAS_CPUFREQ
781 select ARCH_HAS_HOLES_MEMORYMODEL
782 select ARCH_SPARSEMEM_ENABLE
784 select CLKSRC_SAMSUNG_PWM
786 select GENERIC_CLOCKEVENTS
788 select HAVE_S3C2410_I2C if I2C
789 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 select HAVE_S3C_RTC if RTC_CLASS
791 select NEED_MACH_GPIO_H
792 select NEED_MACH_MEMORY_H
795 Samsung S5PV210/S5PC110 series based systems
798 bool "Samsung EXYNOS"
799 select ARCH_HAS_CPUFREQ
800 select ARCH_HAS_HOLES_MEMORYMODEL
801 select ARCH_REQUIRE_GPIOLIB
802 select ARCH_SPARSEMEM_ENABLE
806 select GENERIC_CLOCKEVENTS
807 select HAVE_S3C2410_I2C if I2C
808 select HAVE_S3C2410_WATCHDOG if WATCHDOG
809 select HAVE_S3C_RTC if RTC_CLASS
810 select NEED_MACH_MEMORY_H
814 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
818 select ARCH_HAS_HOLES_MEMORYMODEL
819 select ARCH_REQUIRE_GPIOLIB
821 select GENERIC_ALLOCATOR
822 select GENERIC_CLOCKEVENTS
823 select GENERIC_IRQ_CHIP
825 select NEED_MACH_GPIO_H
830 Support for TI's DaVinci platform.
835 select ARCH_HAS_CPUFREQ
836 select ARCH_HAS_HOLES_MEMORYMODEL
838 select ARCH_REQUIRE_GPIOLIB
841 select GENERIC_CLOCKEVENTS
842 select GENERIC_IRQ_CHIP
845 select NEED_MACH_IO_H if PCCARD
846 select NEED_MACH_MEMORY_H
848 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
852 menu "Multiple platform selection"
853 depends on ARCH_MULTIPLATFORM
855 comment "CPU Core family selection"
857 config ARCH_MULTI_V4T
858 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
859 depends on !ARCH_MULTI_V6_V7
860 select ARCH_MULTI_V4_V5
861 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
862 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
863 CPU_ARM925T || CPU_ARM940T)
866 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
867 depends on !ARCH_MULTI_V6_V7
868 select ARCH_MULTI_V4_V5
869 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
870 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
871 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
873 config ARCH_MULTI_V4_V5
877 bool "ARMv6 based platforms (ARM11)"
878 select ARCH_MULTI_V6_V7
882 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
884 select ARCH_MULTI_V6_V7
887 config ARCH_MULTI_V6_V7
890 config ARCH_MULTI_CPU_AUTO
891 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
897 # This is sorted alphabetically by mach-* pathname. However, plat-*
898 # Kconfigs may be included either alphabetically (according to the
899 # plat- suffix) or along side the corresponding mach-* source.
901 source "arch/arm/mach-mvebu/Kconfig"
903 source "arch/arm/mach-at91/Kconfig"
905 source "arch/arm/mach-bcm/Kconfig"
907 source "arch/arm/mach-bcm2835/Kconfig"
909 source "arch/arm/mach-clps711x/Kconfig"
911 source "arch/arm/mach-cns3xxx/Kconfig"
913 source "arch/arm/mach-davinci/Kconfig"
915 source "arch/arm/mach-dove/Kconfig"
917 source "arch/arm/mach-ep93xx/Kconfig"
919 source "arch/arm/mach-footbridge/Kconfig"
921 source "arch/arm/mach-gemini/Kconfig"
923 source "arch/arm/mach-highbank/Kconfig"
925 source "arch/arm/mach-integrator/Kconfig"
927 source "arch/arm/mach-iop32x/Kconfig"
929 source "arch/arm/mach-iop33x/Kconfig"
931 source "arch/arm/mach-iop13xx/Kconfig"
933 source "arch/arm/mach-ixp4xx/Kconfig"
935 source "arch/arm/mach-keystone/Kconfig"
937 source "arch/arm/mach-kirkwood/Kconfig"
939 source "arch/arm/mach-ks8695/Kconfig"
941 source "arch/arm/mach-msm/Kconfig"
943 source "arch/arm/mach-mv78xx0/Kconfig"
945 source "arch/arm/mach-imx/Kconfig"
947 source "arch/arm/mach-mxs/Kconfig"
949 source "arch/arm/mach-netx/Kconfig"
951 source "arch/arm/mach-nomadik/Kconfig"
953 source "arch/arm/mach-nspire/Kconfig"
955 source "arch/arm/plat-omap/Kconfig"
957 source "arch/arm/mach-omap1/Kconfig"
959 source "arch/arm/mach-omap2/Kconfig"
961 source "arch/arm/mach-orion5x/Kconfig"
963 source "arch/arm/mach-picoxcell/Kconfig"
965 source "arch/arm/mach-pxa/Kconfig"
966 source "arch/arm/plat-pxa/Kconfig"
968 source "arch/arm/mach-mmp/Kconfig"
970 source "arch/arm/mach-realview/Kconfig"
972 source "arch/arm/mach-rockchip/Kconfig"
974 source "arch/arm/mach-sa1100/Kconfig"
976 source "arch/arm/plat-samsung/Kconfig"
978 source "arch/arm/mach-socfpga/Kconfig"
980 source "arch/arm/mach-spear/Kconfig"
982 source "arch/arm/mach-sti/Kconfig"
984 source "arch/arm/mach-s3c24xx/Kconfig"
987 source "arch/arm/mach-s3c64xx/Kconfig"
990 source "arch/arm/mach-s5p64x0/Kconfig"
992 source "arch/arm/mach-s5pc100/Kconfig"
994 source "arch/arm/mach-s5pv210/Kconfig"
996 source "arch/arm/mach-exynos/Kconfig"
998 source "arch/arm/mach-shmobile/Kconfig"
1000 source "arch/arm/mach-sunxi/Kconfig"
1002 source "arch/arm/mach-prima2/Kconfig"
1004 source "arch/arm/mach-tegra/Kconfig"
1006 source "arch/arm/mach-u300/Kconfig"
1008 source "arch/arm/mach-ux500/Kconfig"
1010 source "arch/arm/mach-versatile/Kconfig"
1012 source "arch/arm/mach-vexpress/Kconfig"
1013 source "arch/arm/plat-versatile/Kconfig"
1015 source "arch/arm/mach-virt/Kconfig"
1017 source "arch/arm/mach-vt8500/Kconfig"
1019 source "arch/arm/mach-w90x900/Kconfig"
1021 source "arch/arm/mach-zynq/Kconfig"
1023 # Definitions to make life easier
1029 select GENERIC_CLOCKEVENTS
1035 select GENERIC_IRQ_CHIP
1038 config PLAT_ORION_LEGACY
1045 config PLAT_VERSATILE
1048 config ARM_TIMER_SP804
1051 select CLKSRC_OF if OF
1053 source arch/arm/mm/Kconfig
1057 default 16 if ARCH_EP93XX
1061 bool "Enable iWMMXt support" if !CPU_PJ4
1062 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1063 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1065 Enable support for iWMMXt context switching at run time if
1066 running on a CPU that supports it.
1070 depends on CPU_XSCALE
1073 config MULTI_IRQ_HANDLER
1076 Allow each machine to specify it's own IRQ handler at run time.
1079 source "arch/arm/Kconfig-nommu"
1082 config PJ4B_ERRATA_4742
1083 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1084 depends on CPU_PJ4B && MACH_ARMADA_370
1087 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1088 Event (WFE) IDLE states, a specific timing sensitivity exists between
1089 the retiring WFI/WFE instructions and the newly issued subsequent
1090 instructions. This sensitivity can result in a CPU hang scenario.
1092 The software must insert either a Data Synchronization Barrier (DSB)
1093 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1096 config ARM_ERRATA_326103
1097 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1100 Executing a SWP instruction to read-only memory does not set bit 11
1101 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1102 treat the access as a read, preventing a COW from occurring and
1103 causing the faulting task to livelock.
1105 config ARM_ERRATA_411920
1106 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1107 depends on CPU_V6 || CPU_V6K
1109 Invalidation of the Instruction Cache operation can
1110 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1111 It does not affect the MPCore. This option enables the ARM Ltd.
1112 recommended workaround.
1114 config ARM_ERRATA_430973
1115 bool "ARM errata: Stale prediction on replaced interworking branch"
1118 This option enables the workaround for the 430973 Cortex-A8
1119 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1120 interworking branch is replaced with another code sequence at the
1121 same virtual address, whether due to self-modifying code or virtual
1122 to physical address re-mapping, Cortex-A8 does not recover from the
1123 stale interworking branch prediction. This results in Cortex-A8
1124 executing the new code sequence in the incorrect ARM or Thumb state.
1125 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1126 and also flushes the branch target cache at every context switch.
1127 Note that setting specific bits in the ACTLR register may not be
1128 available in non-secure mode.
1130 config ARM_ERRATA_458693
1131 bool "ARM errata: Processor deadlock when a false hazard is created"
1133 depends on !ARCH_MULTIPLATFORM
1135 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1136 erratum. For very specific sequences of memory operations, it is
1137 possible for a hazard condition intended for a cache line to instead
1138 be incorrectly associated with a different cache line. This false
1139 hazard might then cause a processor deadlock. The workaround enables
1140 the L1 caching of the NEON accesses and disables the PLD instruction
1141 in the ACTLR register. Note that setting specific bits in the ACTLR
1142 register may not be available in non-secure mode.
1144 config ARM_ERRATA_460075
1145 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1147 depends on !ARCH_MULTIPLATFORM
1149 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1150 erratum. Any asynchronous access to the L2 cache may encounter a
1151 situation in which recent store transactions to the L2 cache are lost
1152 and overwritten with stale memory contents from external memory. The
1153 workaround disables the write-allocate mode for the L2 cache via the
1154 ACTLR register. Note that setting specific bits in the ACTLR register
1155 may not be available in non-secure mode.
1157 config ARM_ERRATA_742230
1158 bool "ARM errata: DMB operation may be faulty"
1159 depends on CPU_V7 && SMP
1160 depends on !ARCH_MULTIPLATFORM
1162 This option enables the workaround for the 742230 Cortex-A9
1163 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1164 between two write operations may not ensure the correct visibility
1165 ordering of the two writes. This workaround sets a specific bit in
1166 the diagnostic register of the Cortex-A9 which causes the DMB
1167 instruction to behave as a DSB, ensuring the correct behaviour of
1170 config ARM_ERRATA_742231
1171 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1172 depends on CPU_V7 && SMP
1173 depends on !ARCH_MULTIPLATFORM
1175 This option enables the workaround for the 742231 Cortex-A9
1176 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1177 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1178 accessing some data located in the same cache line, may get corrupted
1179 data due to bad handling of the address hazard when the line gets
1180 replaced from one of the CPUs at the same time as another CPU is
1181 accessing it. This workaround sets specific bits in the diagnostic
1182 register of the Cortex-A9 which reduces the linefill issuing
1183 capabilities of the processor.
1185 config PL310_ERRATA_588369
1186 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1187 depends on CACHE_L2X0
1189 The PL310 L2 cache controller implements three types of Clean &
1190 Invalidate maintenance operations: by Physical Address
1191 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1192 They are architecturally defined to behave as the execution of a
1193 clean operation followed immediately by an invalidate operation,
1194 both performing to the same memory location. This functionality
1195 is not correctly implemented in PL310 as clean lines are not
1196 invalidated as a result of these operations.
1198 config ARM_ERRATA_643719
1199 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1200 depends on CPU_V7 && SMP
1202 This option enables the workaround for the 643719 Cortex-A9 (prior to
1203 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1204 register returns zero when it should return one. The workaround
1205 corrects this value, ensuring cache maintenance operations which use
1206 it behave as intended and avoiding data corruption.
1208 config ARM_ERRATA_720789
1209 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1212 This option enables the workaround for the 720789 Cortex-A9 (prior to
1213 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1214 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1215 As a consequence of this erratum, some TLB entries which should be
1216 invalidated are not, resulting in an incoherency in the system page
1217 tables. The workaround changes the TLB flushing routines to invalidate
1218 entries regardless of the ASID.
1220 config PL310_ERRATA_727915
1221 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1222 depends on CACHE_L2X0
1224 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1225 operation (offset 0x7FC). This operation runs in background so that
1226 PL310 can handle normal accesses while it is in progress. Under very
1227 rare circumstances, due to this erratum, write data can be lost when
1228 PL310 treats a cacheable write transaction during a Clean &
1229 Invalidate by Way operation.
1231 config ARM_ERRATA_743622
1232 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1234 depends on !ARCH_MULTIPLATFORM
1236 This option enables the workaround for the 743622 Cortex-A9
1237 (r2p*) erratum. Under very rare conditions, a faulty
1238 optimisation in the Cortex-A9 Store Buffer may lead to data
1239 corruption. This workaround sets a specific bit in the diagnostic
1240 register of the Cortex-A9 which disables the Store Buffer
1241 optimisation, preventing the defect from occurring. This has no
1242 visible impact on the overall performance or power consumption of the
1245 config ARM_ERRATA_751472
1246 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1248 depends on !ARCH_MULTIPLATFORM
1250 This option enables the workaround for the 751472 Cortex-A9 (prior
1251 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1252 completion of a following broadcasted operation if the second
1253 operation is received by a CPU before the ICIALLUIS has completed,
1254 potentially leading to corrupted entries in the cache or TLB.
1256 config PL310_ERRATA_753970
1257 bool "PL310 errata: cache sync operation may be faulty"
1258 depends on CACHE_PL310
1260 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1262 Under some condition the effect of cache sync operation on
1263 the store buffer still remains when the operation completes.
1264 This means that the store buffer is always asked to drain and
1265 this prevents it from merging any further writes. The workaround
1266 is to replace the normal offset of cache sync operation (0x730)
1267 by another offset targeting an unmapped PL310 register 0x740.
1268 This has the same effect as the cache sync operation: store buffer
1269 drain and waiting for all buffers empty.
1271 config ARM_ERRATA_754322
1272 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1275 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1276 r3p*) erratum. A speculative memory access may cause a page table walk
1277 which starts prior to an ASID switch but completes afterwards. This
1278 can populate the micro-TLB with a stale entry which may be hit with
1279 the new ASID. This workaround places two dsb instructions in the mm
1280 switching code so that no page table walks can cross the ASID switch.
1282 config ARM_ERRATA_754327
1283 bool "ARM errata: no automatic Store Buffer drain"
1284 depends on CPU_V7 && SMP
1286 This option enables the workaround for the 754327 Cortex-A9 (prior to
1287 r2p0) erratum. The Store Buffer does not have any automatic draining
1288 mechanism and therefore a livelock may occur if an external agent
1289 continuously polls a memory location waiting to observe an update.
1290 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1291 written polling loops from denying visibility of updates to memory.
1293 config ARM_ERRATA_364296
1294 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1297 This options enables the workaround for the 364296 ARM1136
1298 r0p2 erratum (possible cache data corruption with
1299 hit-under-miss enabled). It sets the undocumented bit 31 in
1300 the auxiliary control register and the FI bit in the control
1301 register, thus disabling hit-under-miss without putting the
1302 processor into full low interrupt latency mode. ARM11MPCore
1305 config ARM_ERRATA_764369
1306 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1307 depends on CPU_V7 && SMP
1309 This option enables the workaround for erratum 764369
1310 affecting Cortex-A9 MPCore with two or more processors (all
1311 current revisions). Under certain timing circumstances, a data
1312 cache line maintenance operation by MVA targeting an Inner
1313 Shareable memory region may fail to proceed up to either the
1314 Point of Coherency or to the Point of Unification of the
1315 system. This workaround adds a DSB instruction before the
1316 relevant cache maintenance functions and sets a specific bit
1317 in the diagnostic control register of the SCU.
1319 config PL310_ERRATA_769419
1320 bool "PL310 errata: no automatic Store Buffer drain"
1321 depends on CACHE_L2X0
1323 On revisions of the PL310 prior to r3p2, the Store Buffer does
1324 not automatically drain. This can cause normal, non-cacheable
1325 writes to be retained when the memory system is idle, leading
1326 to suboptimal I/O performance for drivers using coherent DMA.
1327 This option adds a write barrier to the cpu_idle loop so that,
1328 on systems with an outer cache, the store buffer is drained
1331 config ARM_ERRATA_775420
1332 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1335 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1336 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1337 operation aborts with MMU exception, it might cause the processor
1338 to deadlock. This workaround puts DSB before executing ISB if
1339 an abort may occur on cache maintenance.
1341 config ARM_ERRATA_798181
1342 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1343 depends on CPU_V7 && SMP
1345 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1346 adequately shooting down all use of the old entries. This
1347 option enables the Linux kernel workaround for this erratum
1348 which sends an IPI to the CPUs that are running the same ASID
1349 as the one being invalidated.
1351 config ARM_ERRATA_773022
1352 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1355 This option enables the workaround for the 773022 Cortex-A15
1356 (up to r0p4) erratum. In certain rare sequences of code, the
1357 loop buffer may deliver incorrect instructions. This
1358 workaround disables the loop buffer to avoid the erratum.
1362 source "arch/arm/common/Kconfig"
1372 Find out whether you have ISA slots on your motherboard. ISA is the
1373 name of a bus system, i.e. the way the CPU talks to the other stuff
1374 inside your box. Other bus systems are PCI, EISA, MicroChannel
1375 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1376 newer boards don't support it. If you have ISA, say Y, otherwise N.
1378 # Select ISA DMA controller support
1383 # Select ISA DMA interface
1388 bool "PCI support" if MIGHT_HAVE_PCI
1390 Find out whether you have a PCI motherboard. PCI is the name of a
1391 bus system, i.e. the way the CPU talks to the other stuff inside
1392 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1393 VESA. If you have PCI, say Y, otherwise N.
1399 config PCI_NANOENGINE
1400 bool "BSE nanoEngine PCI support"
1401 depends on SA1100_NANOENGINE
1403 Enable PCI on the BSE nanoEngine board.
1408 config PCI_HOST_ITE8152
1410 depends on PCI && MACH_ARMCORE
1414 source "drivers/pci/Kconfig"
1415 source "drivers/pci/pcie/Kconfig"
1417 source "drivers/pcmcia/Kconfig"
1421 menu "Kernel Features"
1426 This option should be selected by machines which have an SMP-
1429 The only effect of this option is to make the SMP-related
1430 options available to the user for configuration.
1433 bool "Symmetric Multi-Processing"
1434 depends on CPU_V6K || CPU_V7
1435 depends on GENERIC_CLOCKEVENTS
1437 depends on MMU || ARM_MPU
1438 select USE_GENERIC_SMP_HELPERS
1440 This enables support for systems with more than one CPU. If you have
1441 a system with only one CPU, like most personal computers, say N. If
1442 you have a system with more than one CPU, say Y.
1444 If you say N here, the kernel will run on single and multiprocessor
1445 machines, but will use only one CPU of a multiprocessor machine. If
1446 you say Y here, the kernel will run on many, but not all, single
1447 processor machines. On a single processor machine, the kernel will
1448 run faster if you say N here.
1450 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1451 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1452 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1454 If you don't know what to do here, say N.
1457 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1458 depends on SMP && !XIP_KERNEL && MMU
1461 SMP kernels contain instructions which fail on non-SMP processors.
1462 Enabling this option allows the kernel to modify itself to make
1463 these instructions safe. Disabling it allows about 1K of space
1466 If you don't know what to do here, say Y.
1468 config ARM_CPU_TOPOLOGY
1469 bool "Support cpu topology definition"
1470 depends on SMP && CPU_V7
1473 Support ARM cpu topology definition. The MPIDR register defines
1474 affinity between processors which is then used to describe the cpu
1475 topology of an ARM System.
1478 bool "Multi-core scheduler support"
1479 depends on ARM_CPU_TOPOLOGY
1481 Multi-core scheduler support improves the CPU scheduler's decision
1482 making when dealing with multi-core CPU chips at a cost of slightly
1483 increased overhead in some places. If unsure say N here.
1486 bool "SMT scheduler support"
1487 depends on ARM_CPU_TOPOLOGY
1489 Improves the CPU scheduler's decision making when dealing with
1490 MultiThreading at a cost of slightly increased overhead in some
1491 places. If unsure say N here.
1496 This option enables support for the ARM system coherency unit
1498 config HAVE_ARM_ARCH_TIMER
1499 bool "Architected timer support"
1501 select ARM_ARCH_TIMER
1503 This option enables support for the ARM architected timer
1508 select CLKSRC_OF if OF
1510 This options enables support for the ARM timer and watchdog unit
1513 bool "Multi-Cluster Power Management"
1514 depends on CPU_V7 && SMP
1516 This option provides the common power management infrastructure
1517 for (multi-)cluster based systems, such as big.LITTLE based
1521 prompt "Memory split"
1524 Select the desired split between kernel and user memory.
1526 If you are not absolutely sure what you are doing, leave this
1530 bool "3G/1G user/kernel split"
1532 bool "2G/2G user/kernel split"
1534 bool "1G/3G user/kernel split"
1539 default 0x40000000 if VMSPLIT_1G
1540 default 0x80000000 if VMSPLIT_2G
1544 int "Maximum number of CPUs (2-32)"
1550 bool "Support for hot-pluggable CPUs"
1553 Say Y here to experiment with turning CPUs off and on. CPUs
1554 can be controlled through /sys/devices/system/cpu.
1557 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1560 Say Y here if you want Linux to communicate with system firmware
1561 implementing the PSCI specification for CPU-centric power
1562 management operations described in ARM document number ARM DEN
1563 0022A ("Power State Coordination Interface System Software on
1566 # The GPIO number here must be sorted by descending number. In case of
1567 # a multiplatform kernel, we just want the highest value required by the
1568 # selected platforms.
1571 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1572 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1573 default 392 if ARCH_U8500
1574 default 352 if ARCH_VT8500
1575 default 288 if ARCH_SUNXI
1576 default 264 if MACH_H4700
1579 Maximum number of GPIOs in the system.
1581 If unsure, leave the default value.
1583 source kernel/Kconfig.preempt
1587 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1588 ARCH_S5PV210 || ARCH_EXYNOS4
1589 default AT91_TIMER_HZ if ARCH_AT91
1590 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1594 depends on HZ_FIXED = 0
1595 prompt "Timer frequency"
1619 default HZ_FIXED if HZ_FIXED != 0
1620 default 100 if HZ_100
1621 default 200 if HZ_200
1622 default 250 if HZ_250
1623 default 300 if HZ_300
1624 default 500 if HZ_500
1628 def_bool HIGH_RES_TIMERS
1631 def_bool HIGH_RES_TIMERS
1633 config THUMB2_KERNEL
1634 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1635 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1636 default y if CPU_THUMBONLY
1638 select ARM_ASM_UNIFIED
1641 By enabling this option, the kernel will be compiled in
1642 Thumb-2 mode. A compiler/assembler that understand the unified
1643 ARM-Thumb syntax is needed.
1647 config THUMB2_AVOID_R_ARM_THM_JUMP11
1648 bool "Work around buggy Thumb-2 short branch relocations in gas"
1649 depends on THUMB2_KERNEL && MODULES
1652 Various binutils versions can resolve Thumb-2 branches to
1653 locally-defined, preemptible global symbols as short-range "b.n"
1654 branch instructions.
1656 This is a problem, because there's no guarantee the final
1657 destination of the symbol, or any candidate locations for a
1658 trampoline, are within range of the branch. For this reason, the
1659 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1660 relocation in modules at all, and it makes little sense to add
1663 The symptom is that the kernel fails with an "unsupported
1664 relocation" error when loading some modules.
1666 Until fixed tools are available, passing
1667 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1668 code which hits this problem, at the cost of a bit of extra runtime
1669 stack usage in some cases.
1671 The problem is described in more detail at:
1672 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1674 Only Thumb-2 kernels are affected.
1676 Unless you are sure your tools don't have this problem, say Y.
1678 config ARM_ASM_UNIFIED
1682 bool "Use the ARM EABI to compile the kernel"
1684 This option allows for the kernel to be compiled using the latest
1685 ARM ABI (aka EABI). This is only useful if you are using a user
1686 space environment that is also compiled with EABI.
1688 Since there are major incompatibilities between the legacy ABI and
1689 EABI, especially with regard to structure member alignment, this
1690 option also changes the kernel syscall calling convention to
1691 disambiguate both ABIs and allow for backward compatibility support
1692 (selected with CONFIG_OABI_COMPAT).
1694 To use this you need GCC version 4.0.0 or later.
1697 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1698 depends on AEABI && !THUMB2_KERNEL
1701 This option preserves the old syscall interface along with the
1702 new (ARM EABI) one. It also provides a compatibility layer to
1703 intercept syscalls that have structure arguments which layout
1704 in memory differs between the legacy ABI and the new ARM EABI
1705 (only for non "thumb" binaries). This option adds a tiny
1706 overhead to all syscalls and produces a slightly larger kernel.
1707 If you know you'll be using only pure EABI user space then you
1708 can say N here. If this option is not selected and you attempt
1709 to execute a legacy ABI binary then the result will be
1710 UNPREDICTABLE (in fact it can be predicted that it won't work
1711 at all). If in doubt say Y.
1713 config ARCH_HAS_HOLES_MEMORYMODEL
1716 config ARCH_SPARSEMEM_ENABLE
1719 config ARCH_SPARSEMEM_DEFAULT
1720 def_bool ARCH_SPARSEMEM_ENABLE
1722 config ARCH_SELECT_MEMORY_MODEL
1723 def_bool ARCH_SPARSEMEM_ENABLE
1725 config HAVE_ARCH_PFN_VALID
1726 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1729 bool "High Memory Support"
1732 The address space of ARM processors is only 4 Gigabytes large
1733 and it has to accommodate user address space, kernel address
1734 space as well as some memory mapped IO. That means that, if you
1735 have a large amount of physical memory and/or IO, not all of the
1736 memory can be "permanently mapped" by the kernel. The physical
1737 memory that is not permanently mapped is called "high memory".
1739 Depending on the selected kernel/user memory split, minimum
1740 vmalloc space and actual amount of RAM, you may not need this
1741 option which should result in a slightly faster kernel.
1746 bool "Allocate 2nd-level pagetables from highmem"
1749 config HW_PERF_EVENTS
1750 bool "Enable hardware performance counter support for perf events"
1751 depends on PERF_EVENTS
1754 Enable hardware performance counter support for perf events. If
1755 disabled, perf events will use software events only.
1757 config SYS_SUPPORTS_HUGETLBFS
1761 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1765 config ARCH_WANT_GENERAL_HUGETLB
1770 config FORCE_MAX_ZONEORDER
1771 int "Maximum zone order" if ARCH_SHMOBILE
1772 range 11 64 if ARCH_SHMOBILE
1773 default "12" if SOC_AM33XX
1774 default "9" if SA1111
1777 The kernel memory allocator divides physically contiguous memory
1778 blocks into "zones", where each zone is a power of two number of
1779 pages. This option selects the largest power of two that the kernel
1780 keeps in the memory allocator. If you need to allocate very large
1781 blocks of physically contiguous memory, then you may need to
1782 increase this value.
1784 This config option is actually maximum order plus one. For example,
1785 a value of 11 means that the largest free memory block is 2^10 pages.
1787 config ALIGNMENT_TRAP
1789 depends on CPU_CP15_MMU
1790 default y if !ARCH_EBSA110
1791 select HAVE_PROC_CPU if PROC_FS
1793 ARM processors cannot fetch/store information which is not
1794 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1795 address divisible by 4. On 32-bit ARM processors, these non-aligned
1796 fetch/store instructions will be emulated in software if you say
1797 here, which has a severe performance impact. This is necessary for
1798 correct operation of some network protocols. With an IP-only
1799 configuration it is safe to say N, otherwise say Y.
1801 config UACCESS_WITH_MEMCPY
1802 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1804 default y if CPU_FEROCEON
1806 Implement faster copy_to_user and clear_user methods for CPU
1807 cores where a 8-word STM instruction give significantly higher
1808 memory write throughput than a sequence of individual 32bit stores.
1810 A possible side effect is a slight increase in scheduling latency
1811 between threads sharing the same address space if they invoke
1812 such copy operations with large buffers.
1814 However, if the CPU data cache is using a write-allocate mode,
1815 this option is unlikely to provide any performance gain.
1819 prompt "Enable seccomp to safely compute untrusted bytecode"
1821 This kernel feature is useful for number crunching applications
1822 that may need to compute untrusted bytecode during their
1823 execution. By using pipes or other transports made available to
1824 the process as file descriptors supporting the read/write
1825 syscalls, it's possible to isolate those applications in
1826 their own address space using seccomp. Once seccomp is
1827 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1828 and the task is only allowed to execute a few safe syscalls
1829 defined by each seccomp mode.
1831 config CC_STACKPROTECTOR
1832 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1834 This option turns on the -fstack-protector GCC feature. This
1835 feature puts, at the beginning of functions, a canary value on
1836 the stack just before the return address, and validates
1837 the value just before actually returning. Stack based buffer
1838 overflows (that need to overwrite this return address) now also
1839 overwrite the canary, which gets detected and the attack is then
1840 neutralized via a kernel panic.
1841 This feature requires gcc version 4.2 or above.
1848 bool "Xen guest support on ARM (EXPERIMENTAL)"
1849 depends on ARM && AEABI && OF
1850 depends on CPU_V7 && !CPU_V6
1851 depends on !GENERIC_ATOMIC64
1854 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1861 bool "Flattened Device Tree support"
1864 select OF_EARLY_FLATTREE
1866 Include support for flattened device tree machine descriptions.
1869 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1872 This is the traditional way of passing data to the kernel at boot
1873 time. If you are solely relying on the flattened device tree (or
1874 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1875 to remove ATAGS support from your kernel binary. If unsure,
1878 config DEPRECATED_PARAM_STRUCT
1879 bool "Provide old way to pass kernel parameters"
1882 This was deprecated in 2001 and announced to live on for 5 years.
1883 Some old boot loaders still use this way.
1885 # Compressed boot loader in ROM. Yes, we really want to ask about
1886 # TEXT and BSS so we preserve their values in the config files.
1887 config ZBOOT_ROM_TEXT
1888 hex "Compressed ROM boot loader base address"
1891 The physical address at which the ROM-able zImage is to be
1892 placed in the target. Platforms which normally make use of
1893 ROM-able zImage formats normally set this to a suitable
1894 value in their defconfig file.
1896 If ZBOOT_ROM is not enabled, this has no effect.
1898 config ZBOOT_ROM_BSS
1899 hex "Compressed ROM boot loader BSS address"
1902 The base address of an area of read/write memory in the target
1903 for the ROM-able zImage which must be available while the
1904 decompressor is running. It must be large enough to hold the
1905 entire decompressed kernel plus an additional 128 KiB.
1906 Platforms which normally make use of ROM-able zImage formats
1907 normally set this to a suitable value in their defconfig file.
1909 If ZBOOT_ROM is not enabled, this has no effect.
1912 bool "Compressed boot loader in ROM/flash"
1913 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1915 Say Y here if you intend to execute your compressed kernel image
1916 (zImage) directly from ROM or flash. If unsure, say N.
1919 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1920 depends on ZBOOT_ROM && ARCH_SH7372
1921 default ZBOOT_ROM_NONE
1923 Include experimental SD/MMC loading code in the ROM-able zImage.
1924 With this enabled it is possible to write the ROM-able zImage
1925 kernel image to an MMC or SD card and boot the kernel straight
1926 from the reset vector. At reset the processor Mask ROM will load
1927 the first part of the ROM-able zImage which in turn loads the
1928 rest the kernel image to RAM.
1930 config ZBOOT_ROM_NONE
1931 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1933 Do not load image from SD or MMC
1935 config ZBOOT_ROM_MMCIF
1936 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1938 Load image from MMCIF hardware block.
1940 config ZBOOT_ROM_SH_MOBILE_SDHI
1941 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1943 Load image from SDHI hardware block
1947 config ARM_APPENDED_DTB
1948 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1949 depends on OF && !ZBOOT_ROM
1951 With this option, the boot code will look for a device tree binary
1952 (DTB) appended to zImage
1953 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1955 This is meant as a backward compatibility convenience for those
1956 systems with a bootloader that can't be upgraded to accommodate
1957 the documented boot protocol using a device tree.
1959 Beware that there is very little in terms of protection against
1960 this option being confused by leftover garbage in memory that might
1961 look like a DTB header after a reboot if no actual DTB is appended
1962 to zImage. Do not leave this option active in a production kernel
1963 if you don't intend to always append a DTB. Proper passing of the
1964 location into r2 of a bootloader provided DTB is always preferable
1967 config ARM_ATAG_DTB_COMPAT
1968 bool "Supplement the appended DTB with traditional ATAG information"
1969 depends on ARM_APPENDED_DTB
1971 Some old bootloaders can't be updated to a DTB capable one, yet
1972 they provide ATAGs with memory configuration, the ramdisk address,
1973 the kernel cmdline string, etc. Such information is dynamically
1974 provided by the bootloader and can't always be stored in a static
1975 DTB. To allow a device tree enabled kernel to be used with such
1976 bootloaders, this option allows zImage to extract the information
1977 from the ATAG list and store it at run time into the appended DTB.
1980 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1981 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1983 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1984 bool "Use bootloader kernel arguments if available"
1986 Uses the command-line options passed by the boot loader instead of
1987 the device tree bootargs property. If the boot loader doesn't provide
1988 any, the device tree bootargs property will be used.
1990 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1991 bool "Extend with bootloader kernel arguments"
1993 The command-line arguments provided by the boot loader will be
1994 appended to the the device tree bootargs property.
1999 string "Default kernel command string"
2002 On some architectures (EBSA110 and CATS), there is currently no way
2003 for the boot loader to pass arguments to the kernel. For these
2004 architectures, you should supply some command-line options at build
2005 time by entering them here. As a minimum, you should specify the
2006 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2009 prompt "Kernel command line type" if CMDLINE != ""
2010 default CMDLINE_FROM_BOOTLOADER
2013 config CMDLINE_FROM_BOOTLOADER
2014 bool "Use bootloader kernel arguments if available"
2016 Uses the command-line options passed by the boot loader. If
2017 the boot loader doesn't provide any, the default kernel command
2018 string provided in CMDLINE will be used.
2020 config CMDLINE_EXTEND
2021 bool "Extend bootloader kernel arguments"
2023 The command-line arguments provided by the boot loader will be
2024 appended to the default kernel command string.
2026 config CMDLINE_FORCE
2027 bool "Always use the default kernel command string"
2029 Always use the default kernel command string, even if the boot
2030 loader passes other arguments to the kernel.
2031 This is useful if you cannot or don't want to change the
2032 command-line options your boot loader passes to the kernel.
2036 bool "Kernel Execute-In-Place from ROM"
2037 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2039 Execute-In-Place allows the kernel to run from non-volatile storage
2040 directly addressable by the CPU, such as NOR flash. This saves RAM
2041 space since the text section of the kernel is not loaded from flash
2042 to RAM. Read-write sections, such as the data section and stack,
2043 are still copied to RAM. The XIP kernel is not compressed since
2044 it has to run directly from flash, so it will take more space to
2045 store it. The flash address used to link the kernel object files,
2046 and for storing it, is configuration dependent. Therefore, if you
2047 say Y here, you must know the proper physical address where to
2048 store the kernel image depending on your own flash memory usage.
2050 Also note that the make target becomes "make xipImage" rather than
2051 "make zImage" or "make Image". The final kernel binary to put in
2052 ROM memory will be arch/arm/boot/xipImage.
2056 config XIP_PHYS_ADDR
2057 hex "XIP Kernel Physical Location"
2058 depends on XIP_KERNEL
2059 default "0x00080000"
2061 This is the physical address in your flash memory the kernel will
2062 be linked for and stored to. This address is dependent on your
2066 bool "Kexec system call (EXPERIMENTAL)"
2067 depends on (!SMP || PM_SLEEP_SMP)
2069 kexec is a system call that implements the ability to shutdown your
2070 current kernel, and to start another kernel. It is like a reboot
2071 but it is independent of the system firmware. And like a reboot
2072 you can start any kernel with it, not just Linux.
2074 It is an ongoing process to be certain the hardware in a machine
2075 is properly shutdown, so do not be surprised if this code does not
2076 initially work for you.
2079 bool "Export atags in procfs"
2080 depends on ATAGS && KEXEC
2083 Should the atags used to boot the kernel be exported in an "atags"
2084 file in procfs. Useful with kexec.
2087 bool "Build kdump crash kernel (EXPERIMENTAL)"
2089 Generate crash dump after being started by kexec. This should
2090 be normally only set in special crash dump kernels which are
2091 loaded in the main kernel with kexec-tools into a specially
2092 reserved region and then later executed after a crash by
2093 kdump/kexec. The crash dump kernel must be compiled to a
2094 memory address not used by the main kernel
2096 For more details see Documentation/kdump/kdump.txt
2098 config AUTO_ZRELADDR
2099 bool "Auto calculation of the decompressed kernel image address"
2100 depends on !ZBOOT_ROM
2102 ZRELADDR is the physical address where the decompressed kernel
2103 image will be placed. If AUTO_ZRELADDR is selected, the address
2104 will be determined at run-time by masking the current IP with
2105 0xf8000000. This assumes the zImage being placed in the first 128MB
2106 from start of memory.
2110 menu "CPU Power Management"
2113 source "drivers/cpufreq/Kconfig"
2116 source "drivers/cpuidle/Kconfig"
2120 menu "Floating point emulation"
2122 comment "At least one emulation must be selected"
2125 bool "NWFPE math emulation"
2126 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2128 Say Y to include the NWFPE floating point emulator in the kernel.
2129 This is necessary to run most binaries. Linux does not currently
2130 support floating point hardware so you need to say Y here even if
2131 your machine has an FPA or floating point co-processor podule.
2133 You may say N here if you are going to load the Acorn FPEmulator
2134 early in the bootup.
2137 bool "Support extended precision"
2138 depends on FPE_NWFPE
2140 Say Y to include 80-bit support in the kernel floating-point
2141 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2142 Note that gcc does not generate 80-bit operations by default,
2143 so in most cases this option only enlarges the size of the
2144 floating point emulator without any good reason.
2146 You almost surely want to say N here.
2149 bool "FastFPE math emulation (EXPERIMENTAL)"
2150 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2152 Say Y here to include the FAST floating point emulator in the kernel.
2153 This is an experimental much faster emulator which now also has full
2154 precision for the mantissa. It does not support any exceptions.
2155 It is very simple, and approximately 3-6 times faster than NWFPE.
2157 It should be sufficient for most programs. It may be not suitable
2158 for scientific calculations, but you have to check this for yourself.
2159 If you do not feel you need a faster FP emulation you should better
2163 bool "VFP-format floating point maths"
2164 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2166 Say Y to include VFP support code in the kernel. This is needed
2167 if your hardware includes a VFP unit.
2169 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2170 release notes and additional status information.
2172 Say N if your target does not have VFP hardware.
2180 bool "Advanced SIMD (NEON) Extension support"
2181 depends on VFPv3 && CPU_V7
2183 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2186 config KERNEL_MODE_NEON
2187 bool "Support for NEON in kernel mode"
2191 Say Y to include support for NEON in kernel mode.
2195 menu "Userspace binary formats"
2197 source "fs/Kconfig.binfmt"
2200 tristate "RISC OS personality"
2203 Say Y here to include the kernel code necessary if you want to run
2204 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2205 experimental; if this sounds frightening, say N and sleep in peace.
2206 You can also say M here to compile this support as a module (which
2207 will be called arthur).
2211 menu "Power management options"
2213 source "kernel/power/Kconfig"
2215 config ARCH_SUSPEND_POSSIBLE
2216 depends on !ARCH_S5PC100
2217 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2218 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2221 config ARM_CPU_SUSPEND
2226 source "net/Kconfig"
2228 source "drivers/Kconfig"
2232 source "arch/arm/Kconfig.debug"
2234 source "security/Kconfig"
2236 source "crypto/Kconfig"
2238 source "lib/Kconfig"
2240 source "arch/arm/kvm/Kconfig"