1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
15 select INIT_SP_RELATIVE
17 U-Boot expects to be linked to a specific hard-coded address, and to
18 be loaded to and run from that address. This option lifts that
19 restriction, thus allowing the code to be loaded to and executed
20 from almost any address. This logic relies on the relocation
21 information that is embedded in the binary to support U-Boot
22 relocating itself to the top-of-RAM later during execution.
24 config INIT_SP_RELATIVE
25 bool "Specify the early stack pointer relative to the .bss section"
27 U-Boot typically uses a hard-coded value for the stack pointer
28 before relocation. Enable this option to instead calculate the
29 initial SP at run-time. This is useful to avoid hard-coding addresses
30 into U-Boot, so that it can be loaded and executed at arbitrary
31 addresses and thus avoid using arbitrary addresses at runtime.
33 If this option is enabled, the early stack pointer is set to
34 &_bss_start with a offset value added. The offset is specified by
35 SYS_INIT_SP_BSS_OFFSET.
37 config SYS_INIT_SP_BSS_OFFSET
38 int "Early stack offset from the .bss base address"
39 depends on INIT_SP_RELATIVE
42 This option's value is the offset added to &_bss_start in order to
43 calculate the stack pointer. This offset should be large enough so
44 that the early malloc region, global data (gd), and early stack usage
45 do not overlap any appended DTB.
47 config LINUX_KERNEL_IMAGE_HEADER
50 Place a Linux kernel image header at the start of the U-Boot binary.
51 The format of the header is described in the Linux kernel source at
52 Documentation/arm64/booting.txt. This feature is useful since the
53 image header reports the amount of memory (BSS and similar) that
54 U-Boot needs to use, but which isn't part of the binary.
56 if LINUX_KERNEL_IMAGE_HEADER
57 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
60 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
61 TEXT_OFFSET value written to the Linux kernel image header.
68 ARM GICV3 Interrupt translation service (ITS).
69 Basic support for programming locality specific peripheral
70 interrupts (LPI) configuration tables and enable LPI tables.
71 LPI configuration table can be used by u-boot or Linux.
72 ARM GICV3 has limitation, once the LPI table is enabled, LPI
73 configuration table can not be re-programmed, unless GICV3 reset.
77 default y if ARM64 && !POSITION_INDEPENDENT
79 config DMA_ADDR_T_64BIT
89 # Used for compatibility with asm files copied from the kernel
90 config ARM_ASM_UNIFIED
94 # Used for compatibility with asm files copied from the kernel
99 bool "Do not enable icache"
102 Do not enable instruction cache in U-Boot.
104 config SPL_SYS_ICACHE_OFF
105 bool "Do not enable icache in SPL"
107 default SYS_ICACHE_OFF
109 Do not enable instruction cache in SPL.
111 config SYS_DCACHE_OFF
112 bool "Do not enable dcache"
115 Do not enable data cache in U-Boot.
117 config SPL_SYS_DCACHE_OFF
118 bool "Do not enable dcache in SPL"
120 default SYS_DCACHE_OFF
122 Do not enable data cache in SPL.
124 config SYS_ARM_CACHE_CP15
125 bool "CP15 based cache enabling support"
127 Select this if your processor suports enabling caches by using
131 bool "MMU-based Paged Memory Management Support"
132 select SYS_ARM_CACHE_CP15
134 Select if you want MMU-based virtualised addressing space
135 support via paged memory management.
138 bool 'Use the ARM v7 PMSA Compliant MPU'
140 Some ARM systems without an MMU have instead a Memory Protection
141 Unit (MPU) that defines the type and permissions for regions of
143 If your CPU has an MPU then you should choose 'y' here unless you
144 know that you do not want to use the MPU.
146 # If set, the workarounds for these ARM errata are applied early during U-Boot
147 # startup. Note that in general these options force the workarounds to be
148 # applied; no CPU-type/version detection exists, unlike the similar options in
149 # the Linux kernel. Do not set these options unless they apply! Also note that
150 # the following can be machine-specific errata. These do have ability to
151 # provide rudimentary version and machine-specific checks, but expect no
153 # CONFIG_ARM_ERRATA_430973
154 # CONFIG_ARM_ERRATA_454179
155 # CONFIG_ARM_ERRATA_621766
156 # CONFIG_ARM_ERRATA_798870
157 # CONFIG_ARM_ERRATA_801819
158 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
159 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
161 config ARM_ERRATA_430973
164 config ARM_ERRATA_454179
167 config ARM_ERRATA_621766
170 config ARM_ERRATA_716044
173 config ARM_ERRATA_725233
176 config ARM_ERRATA_742230
179 config ARM_ERRATA_743622
182 config ARM_ERRATA_751472
185 config ARM_ERRATA_761320
188 config ARM_ERRATA_773022
191 config ARM_ERRATA_774769
194 config ARM_ERRATA_794072
197 config ARM_ERRATA_798870
200 config ARM_ERRATA_801819
203 config ARM_ERRATA_826974
206 config ARM_ERRATA_828024
209 config ARM_ERRATA_829520
212 config ARM_ERRATA_833069
215 config ARM_ERRATA_833471
218 config ARM_ERRATA_845369
221 config ARM_ERRATA_852421
224 config ARM_ERRATA_852423
227 config ARM_ERRATA_855873
230 config ARM_CORTEX_A8_CVE_2017_5715
233 config ARM_CORTEX_A15_CVE_2017_5715
238 select SYS_CACHE_SHIFT_5
243 select SYS_CACHE_SHIFT_5
248 select SYS_CACHE_SHIFT_5
253 select SYS_CACHE_SHIFT_5
258 select SYS_CACHE_SHIFT_5
264 select SYS_CACHE_SHIFT_5
271 select SYS_CACHE_SHIFT_6
278 select SYS_CACHE_SHIFT_5
279 select SYS_THUMB_BUILD
285 select SYS_ARM_CACHE_CP15
287 select SYS_CACHE_SHIFT_6
291 select SYS_CACHE_SHIFT_5
296 select SYS_CACHE_SHIFT_5
300 default "arm720t" if CPU_ARM720T
301 default "arm920t" if CPU_ARM920T
302 default "arm926ejs" if CPU_ARM926EJS
303 default "arm946es" if CPU_ARM946ES
304 default "arm1136" if CPU_ARM1136
305 default "arm1176" if CPU_ARM1176
306 default "armv7" if CPU_V7A
307 default "armv7" if CPU_V7R
308 default "armv7m" if CPU_V7M
309 default "pxa" if CPU_PXA
310 default "sa1100" if CPU_SA1100
311 default "armv8" if ARM64
315 default 4 if CPU_ARM720T
316 default 4 if CPU_ARM920T
317 default 5 if CPU_ARM926EJS
318 default 5 if CPU_ARM946ES
319 default 6 if CPU_ARM1136
320 default 6 if CPU_ARM1176
325 default 4 if CPU_SA1100
328 config SYS_CACHE_SHIFT_5
331 config SYS_CACHE_SHIFT_6
334 config SYS_CACHE_SHIFT_7
337 config SYS_CACHELINE_SIZE
339 default 128 if SYS_CACHE_SHIFT_7
340 default 64 if SYS_CACHE_SHIFT_6
341 default 32 if SYS_CACHE_SHIFT_5
344 prompt "Select the ARM data write cache policy"
345 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
346 TARGET_BCMNSP || CPU_PXA || RZA1
347 default SYS_ARM_CACHE_WRITEBACK
349 config SYS_ARM_CACHE_WRITEBACK
350 bool "Write-back (WB)"
352 A write updates the cache only and marks the cache line as dirty.
353 External memory is updated only when the line is evicted or explicitly
356 config SYS_ARM_CACHE_WRITETHROUGH
357 bool "Write-through (WT)"
359 A write updates both the cache and the external memory system.
360 This does not mark the cache line as dirty.
362 config SYS_ARM_CACHE_WRITEALLOC
363 bool "Write allocation (WA)"
365 A cache line is allocated on a write miss. This means that executing a
366 store instruction on the processor might cause a burst read to occur.
367 There is a linefill to obtain the data for the cache line, before the
372 bool "Enable ARCH_CPU_INIT"
374 Some architectures require a call to arch_cpu_init().
375 Say Y here to enable it
377 config SYS_ARCH_TIMER
378 bool "ARM Generic Timer support"
379 depends on CPU_V7A || ARM64
382 The ARM Generic Timer (aka arch-timer) provides an architected
383 interface to a timer source on an SoC.
384 It is mandatory for ARMv8 implementation and widely available
388 bool "Support for ARM SMC Calling Convention (SMCCC)"
389 depends on CPU_V7A || ARM64
392 Say Y here if you want to enable ARM SMC Calling Convention.
393 This should be enabled if U-Boot needs to communicate with system
394 firmware (for example, PSCI) according to SMCCC.
397 bool "support boot from semihosting"
399 In emulated environments, semihosting is a way for
400 the hosted environment to call out to the emulator to
401 retrieve files from the host machine.
403 config SYS_THUMB_BUILD
404 bool "Build U-Boot using the Thumb instruction set"
407 Use this flag to build U-Boot using the Thumb instruction set for
408 ARM architectures. Thumb instruction set provides better code
409 density. For ARM architectures that support Thumb2 this flag will
410 result in Thumb2 code generated by GCC.
412 config SPL_SYS_THUMB_BUILD
413 bool "Build SPL using the Thumb instruction set"
414 default y if SYS_THUMB_BUILD
415 depends on !ARM64 && SPL
417 Use this flag to build SPL using the Thumb instruction set for
418 ARM architectures. Thumb instruction set provides better code
419 density. For ARM architectures that support Thumb2 this flag will
420 result in Thumb2 code generated by GCC.
422 config TPL_SYS_THUMB_BUILD
423 bool "Build TPL using the Thumb instruction set"
424 default y if SYS_THUMB_BUILD
425 depends on TPL && !ARM64
427 Use this flag to build TPL using the Thumb instruction set for
428 ARM architectures. Thumb instruction set provides better code
429 density. For ARM architectures that support Thumb2 this flag will
430 result in Thumb2 code generated by GCC.
433 config SYS_L2CACHE_OFF
436 If SoC does not support L2CACHE or one does not want to enable
437 L2CACHE, choose this option.
439 config ENABLE_ARM_SOC_BOOT0_HOOK
440 bool "prepare BOOT0 header"
442 If the SoC's BOOT0 requires a header area filled with (magic)
443 values, then choose this option, and create a file included as
444 <asm/arch/boot0.h> which contains the required assembler code.
446 config ARM_CORTEX_CPU_IS_UP
450 config USE_ARCH_MEMCPY
451 bool "Use an assembly optimized implementation of memcpy"
455 Enable the generation of an optimized version of memcpy.
456 Such an implementation may be faster under some conditions
457 but may increase the binary size.
459 config SPL_USE_ARCH_MEMCPY
460 bool "Use an assembly optimized implementation of memcpy for SPL"
461 default y if USE_ARCH_MEMCPY
462 depends on !ARM64 && SPL
464 Enable the generation of an optimized version of memcpy.
465 Such an implementation may be faster under some conditions
466 but may increase the binary size.
468 config TPL_USE_ARCH_MEMCPY
469 bool "Use an assembly optimized implementation of memcpy for TPL"
470 default y if USE_ARCH_MEMCPY
471 depends on !ARM64 && TPL
473 Enable the generation of an optimized version of memcpy.
474 Such an implementation may be faster under some conditions
475 but may increase the binary size.
477 config USE_ARCH_MEMSET
478 bool "Use an assembly optimized implementation of memset"
482 Enable the generation of an optimized version of memset.
483 Such an implementation may be faster under some conditions
484 but may increase the binary size.
486 config SPL_USE_ARCH_MEMSET
487 bool "Use an assembly optimized implementation of memset for SPL"
488 default y if USE_ARCH_MEMSET
489 depends on !ARM64 && SPL
491 Enable the generation of an optimized version of memset.
492 Such an implementation may be faster under some conditions
493 but may increase the binary size.
495 config TPL_USE_ARCH_MEMSET
496 bool "Use an assembly optimized implementation of memset for TPL"
497 default y if USE_ARCH_MEMSET
498 depends on !ARM64 && TPL
500 Enable the generation of an optimized version of memset.
501 Such an implementation may be faster under some conditions
502 but may increase the binary size.
504 config SET_STACK_SIZE
505 bool "Enable an option to set max stack size that can be used"
506 default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ
508 This will enable an option to set max stack size that can be
512 hex "Define max stack size that can be used by U-Boot"
513 depends on SET_STACK_SIZE
514 default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
515 default 0x1000000 if ARCH_ZYNQ
517 Define Max stack size that can be used by U-Boot so that the
518 initrd_high will be calculated as base stack pointer minus this
521 config ARM64_SUPPORT_AARCH32
522 bool "ARM64 system support AArch32 execution state"
524 default y if !TARGET_THUNDERX_88XX
526 This ARM64 system supports AArch32 execution state.
529 prompt "Target select"
534 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
535 select SPL_SEPARATE_BSS if SPL
537 config TARGET_EDB93XX
538 bool "Support edb93xx"
542 config TARGET_ASPENITE
543 bool "Support aspenite"
547 bool "Support gplugd"
553 select SPL_DM_SPI if SPL
556 Support for TI's DaVinci platform.
559 bool "Marvell Kirkwood"
560 select ARCH_MISC_INIT
561 select BOARD_EARLY_INIT_F
565 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
571 select SPL_DM_SPI if SPL
572 select SPL_DM_SPI_FLASH if SPL
587 config TARGET_SPEAR300
588 bool "Support spear300"
589 select BOARD_EARLY_INIT_F
594 config TARGET_SPEAR310
595 bool "Support spear310"
596 select BOARD_EARLY_INIT_F
601 config TARGET_SPEAR320
602 bool "Support spear320"
603 select BOARD_EARLY_INIT_F
608 config TARGET_SPEAR600
609 bool "Support spear600"
610 select BOARD_EARLY_INIT_F
615 config TARGET_STV0991
616 bool "Support stv0991"
629 select BOARD_LATE_INIT
638 config TARGET_MX35PDK
639 bool "Support mx35pdk"
640 select BOARD_LATE_INIT
644 bool "Broadcom BCM283X family"
650 select SERIAL_SEARCH_ALL
655 bool "Broadcom BCM63158 family"
661 bool "Broadcom BCM68360 family"
667 bool "Broadcom BCM6858 family"
672 config TARGET_VEXPRESS_CA15_TC2
673 bool "Support vexpress_ca15_tc2"
675 select CPU_V7_HAS_NONSEC
676 select CPU_V7_HAS_VIRT
680 bool "Broadcom BCM7XXX family"
684 select OF_PRIOR_STAGE
687 This enables support for Broadcom ARM-based set-top box
688 chipsets, including the 7445 family of chips.
690 config TARGET_VEXPRESS_CA5X2
691 bool "Support vexpress_ca5x2"
695 config TARGET_VEXPRESS_CA9X4
696 bool "Support vexpress_ca9x4"
700 config TARGET_BCM23550_W1D
701 bool "Support bcm23550_w1d"
706 config TARGET_BCM28155_AP
707 bool "Support bcm28155_ap"
712 config TARGET_BCMCYGNUS
713 bool "Support bcmcygnus"
716 imply BCM_SF2_ETH_GMAC
724 bool "Support bcmnsp"
728 bool "Support Broadcom Northstar2"
731 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
732 ARMv8 Cortex-A57 processors targeting a broad range of networking
736 bool "Support Broadcom NS3"
738 select BOARD_LATE_INIT
740 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
741 ARMv8 Cortex-A72 processors targeting a broad range of networking
745 bool "Samsung EXYNOS"
754 imply SYS_THUMB_BUILD
759 bool "Samsung S5PC1XX"
768 bool "Calxeda Highbank"
772 config ARCH_INTEGRATOR
773 bool "ARM Ltd. Integrator family"
780 bool "Qualcomm IPQ40xx SoCs"
795 select SYS_ARCH_TIMER
796 select SYS_THUMB_BUILD
802 bool "Texas Instruments' K3 Architecture"
807 config ARCH_OMAP2PLUS
810 select SPL_BOARD_INIT if SPL
811 select SPL_STACK_R if SPL
817 imply DISTRO_DEFAULTS
820 Support for the Meson SoC family developed by Amlogic Inc.,
821 targeted at media players and tablet computers. We currently
822 support the S905 (GXBaby) 64-bit SoC.
829 select SPL_LIBCOMMON_SUPPORT if SPL
830 select SPL_LIBGENERIC_SUPPORT if SPL
831 select SPL_OF_CONTROL if SPL
834 Support for the MediaTek SoCs family developed by MediaTek Inc.
835 Please refer to doc/README.mediatek for more information.
838 bool "NXP LPC32xx platform"
848 bool "NXP i.MX8 platform"
852 select ENABLE_ARM_SOC_BOOT0_HOOK
855 bool "NXP i.MX8M platform"
862 bool "NXP i.MXRT platform"
870 bool "NXP i.MX23 family"
881 bool "NXP i.MX28 family"
887 bool "NXP i.MX31 family"
893 select ROM_UNIFIED_SECTIONS
895 imply SYS_THUMB_BUILD
899 select ARCH_MISC_INIT
901 select SYS_FSL_HAS_SEC if IMX_HAB
902 select SYS_FSL_SEC_COMPAT_4
903 select SYS_FSL_SEC_LE
904 imply BOARD_EARLY_INIT_F
906 imply SYS_THUMB_BUILD
911 select SYS_FSL_HAS_SEC
912 select SYS_FSL_SEC_COMPAT_4
913 select SYS_FSL_SEC_LE
915 imply SYS_THUMB_BUILD
919 default "arch/arm/mach-omap2/u-boot-spl.lds"
924 select BOARD_EARLY_INIT_F
929 bool "Nexell S5P4418/S5P6818 SoC"
930 select ENABLE_ARM_SOC_BOOT0_HOOK
934 bool "Actions Semi OWL SoCs"
942 select SYS_RELOC_GD_ENV_ADDR
946 bool "QEMU Virtual Platform"
947 select ARCH_SUPPORT_TFABOOT
957 bool "Renesas ARM SoCs"
958 select BOARD_EARLY_INIT_F if !RZA1
963 imply SYS_THUMB_BUILD
964 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
966 config TARGET_S32V234EVB
967 bool "Support s32v234evb"
969 select SYS_FSL_ERRATUM_ESDHC111
971 config ARCH_SNAPDRAGON
972 bool "Qualcomm Snapdragon SoCs"
985 bool "Altera SOCFPGA family"
986 select ARCH_EARLY_INIT_R
987 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
988 select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
989 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
992 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
994 select SPL_DM_RESET if DM_RESET
996 select SPL_LIBCOMMON_SUPPORT
997 select SPL_LIBGENERIC_SUPPORT
998 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
999 select SPL_OF_CONTROL
1000 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
1001 select SPL_SERIAL_SUPPORT
1003 select SPL_WATCHDOG_SUPPORT
1006 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1008 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1009 select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
1019 imply SPL_DM_SPI_FLASH
1020 imply SPL_LIBDISK_SUPPORT
1021 imply SPL_MMC_SUPPORT
1022 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1023 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1024 imply SPL_SPI_FLASH_SUPPORT
1025 imply SPL_SPI_SUPPORT
1029 bool "Support sunxi (Allwinner) SoCs"
1032 select CMD_MMC if MMC
1033 select CMD_USB if DISTRO_DEFAULTS
1039 select DM_MMC if MMC
1040 select DM_SCSI if SCSI
1042 select DM_USB if DISTRO_DEFAULTS
1043 select OF_BOARD_SETUP
1046 select SPECIFY_CONSOLE_INDEX
1047 select SPL_STACK_R if SPL
1048 select SPL_SYS_MALLOC_SIMPLE if SPL
1049 select SPL_SYS_THUMB_BUILD if !ARM64
1052 select SYS_THUMB_BUILD if !ARM64
1053 select USB if DISTRO_DEFAULTS
1054 select USB_KEYBOARD if DISTRO_DEFAULTS
1055 select USB_STORAGE if DISTRO_DEFAULTS
1056 select SPL_USE_TINY_PRINTF
1058 select SYS_RELOC_GD_ENV_ADDR
1061 imply CMD_UBI if MTD_RAW_NAND
1062 imply DISTRO_DEFAULTS
1065 imply OF_LIBFDT_OVERLAY
1066 imply PRE_CONSOLE_BUFFER
1067 imply SPL_GPIO_SUPPORT
1068 imply SPL_LIBCOMMON_SUPPORT
1069 imply SPL_LIBGENERIC_SUPPORT
1070 imply SPL_MMC_SUPPORT if MMC
1071 imply SPL_POWER_SUPPORT
1072 imply SPL_SERIAL_SUPPORT
1076 bool "ST-Ericsson U8500 Series"
1080 select DM_MMC if MMC
1082 select DM_USB if USB
1086 imply ARM_PL180_MMCI
1088 imply NOMADIK_MTU_TIMER
1091 imply SYSRESET_SYSCON
1094 bool "Support Xilinx Versal Platform"
1098 select DM_ETH if NET
1099 select DM_MMC if MMC
1102 imply BOARD_LATE_INIT
1105 bool "Freescale Vybrid"
1107 select SYS_FSL_ERRATUM_ESDHC111
1112 bool "Xilinx Zynq based platform"
1117 select DM_ETH if NET
1118 select DM_MMC if MMC
1122 select DM_USB if USB
1125 select SPL_BOARD_INIT if SPL
1126 select SPL_CLK if SPL
1127 select SPL_DM if SPL
1128 select SPL_DM_SPI if SPL
1129 select SPL_DM_SPI_FLASH if SPL
1130 select SPL_OF_CONTROL if SPL
1131 select SPL_SEPARATE_BSS if SPL
1133 imply ARCH_EARLY_INIT_R
1134 imply BOARD_LATE_INIT
1140 config ARCH_ZYNQMP_R5
1141 bool "Xilinx ZynqMP R5 based platform"
1145 select DM_ETH if NET
1146 select DM_MMC if MMC
1153 bool "Xilinx ZynqMP based platform"
1157 select DM_ETH if NET
1159 select DM_MMC if MMC
1161 select DM_SPI if SPI
1162 select DM_SPI_FLASH if DM_SPI
1163 select DM_USB if USB
1166 select SPL_BOARD_INIT if SPL
1167 select SPL_CLK if SPL
1168 select SPL_DM_SPI if SPI
1169 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1170 select SPL_DM_MAILBOX if SPL
1171 select SPL_FIRMWARE if SPL
1172 select SPL_SEPARATE_BSS if SPL
1175 imply BOARD_LATE_INIT
1183 imply DISTRO_DEFAULTS
1186 config TARGET_VEXPRESS64_AEMV8A
1187 bool "Support vexpress_aemv8a"
1191 config TARGET_VEXPRESS64_BASE_FVP
1192 bool "Support Versatile Express ARMv8a FVP BASE model"
1197 config TARGET_VEXPRESS64_JUNO
1198 bool "Support Versatile Express Juno Development Platform"
1213 config TARGET_LS2080A_EMU
1214 bool "Support ls2080a_emu"
1217 select ARMV8_MULTIENTRY
1218 select FSL_DDR_SYNC_REFRESH
1220 Support for Freescale LS2080A_EMU platform.
1221 The LS2080A Development System (EMULATOR) is a pre-silicon
1222 development platform that supports the QorIQ LS2080A
1223 Layerscape Architecture processor.
1225 config TARGET_LS2080A_SIMU
1226 bool "Support ls2080a_simu"
1229 select ARMV8_MULTIENTRY
1230 select BOARD_LATE_INIT
1232 Support for Freescale LS2080A_SIMU platform.
1233 The LS2080A Development System (QDS) is a pre silicon
1234 development platform that supports the QorIQ LS2080A
1235 Layerscape Architecture processor.
1237 config TARGET_LS1088AQDS
1238 bool "Support ls1088aqds"
1241 select ARMV8_MULTIENTRY
1242 select ARCH_SUPPORT_TFABOOT
1243 select BOARD_LATE_INIT
1245 select FSL_DDR_INTERACTIVE if !SD_BOOT
1247 Support for NXP LS1088AQDS platform.
1248 The LS1088A Development System (QDS) is a high-performance
1249 development platform that supports the QorIQ LS1088A
1250 Layerscape Architecture processor.
1252 config TARGET_LS2080AQDS
1253 bool "Support ls2080aqds"
1256 select ARMV8_MULTIENTRY
1257 select ARCH_SUPPORT_TFABOOT
1258 select BOARD_LATE_INIT
1263 select FSL_DDR_INTERACTIVE if !SPL
1265 Support for Freescale LS2080AQDS platform.
1266 The LS2080A Development System (QDS) is a high-performance
1267 development platform that supports the QorIQ LS2080A
1268 Layerscape Architecture processor.
1270 config TARGET_LS2080ARDB
1271 bool "Support ls2080ardb"
1274 select ARMV8_MULTIENTRY
1275 select ARCH_SUPPORT_TFABOOT
1276 select BOARD_LATE_INIT
1279 select FSL_DDR_INTERACTIVE if !SPL
1283 Support for Freescale LS2080ARDB platform.
1284 The LS2080A Reference design board (RDB) is a high-performance
1285 development platform that supports the QorIQ LS2080A
1286 Layerscape Architecture processor.
1288 config TARGET_LS2081ARDB
1289 bool "Support ls2081ardb"
1292 select ARMV8_MULTIENTRY
1293 select BOARD_LATE_INIT
1296 Support for Freescale LS2081ARDB platform.
1297 The LS2081A Reference design board (RDB) is a high-performance
1298 development platform that supports the QorIQ LS2081A/LS2041A
1299 Layerscape Architecture processor.
1301 config TARGET_LX2160ARDB
1302 bool "Support lx2160ardb"
1305 select ARMV8_MULTIENTRY
1306 select ARCH_SUPPORT_TFABOOT
1307 select BOARD_LATE_INIT
1309 Support for NXP LX2160ARDB platform.
1310 The lx2160ardb (LX2160A Reference design board (RDB)
1311 is a high-performance development platform that supports the
1312 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1314 config TARGET_LX2160AQDS
1315 bool "Support lx2160aqds"
1318 select ARMV8_MULTIENTRY
1319 select ARCH_SUPPORT_TFABOOT
1320 select BOARD_LATE_INIT
1322 Support for NXP LX2160AQDS platform.
1323 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1324 is a high-performance development platform that supports the
1325 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1328 bool "Support HiKey 96boards Consumer Edition Platform"
1335 select SPECIFY_CONSOLE_INDEX
1338 Support for HiKey 96boards platform. It features a HI6220
1339 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1341 config TARGET_HIKEY960
1342 bool "Support HiKey960 96boards Consumer Edition Platform"
1350 Support for HiKey960 96boards platform. It features a HI3660
1351 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1353 config TARGET_POPLAR
1354 bool "Support Poplar 96boards Enterprise Edition Platform"
1363 Support for Poplar 96boards EE platform. It features a HI3798cv200
1364 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1365 making it capable of running any commercial set-top solution based on
1368 config TARGET_LS1012AQDS
1369 bool "Support ls1012aqds"
1372 select ARCH_SUPPORT_TFABOOT
1373 select BOARD_LATE_INIT
1375 Support for Freescale LS1012AQDS platform.
1376 The LS1012A Development System (QDS) is a high-performance
1377 development platform that supports the QorIQ LS1012A
1378 Layerscape Architecture processor.
1380 config TARGET_LS1012ARDB
1381 bool "Support ls1012ardb"
1384 select ARCH_SUPPORT_TFABOOT
1385 select BOARD_LATE_INIT
1389 Support for Freescale LS1012ARDB platform.
1390 The LS1012A Reference design board (RDB) is a high-performance
1391 development platform that supports the QorIQ LS1012A
1392 Layerscape Architecture processor.
1394 config TARGET_LS1012A2G5RDB
1395 bool "Support ls1012a2g5rdb"
1398 select ARCH_SUPPORT_TFABOOT
1399 select BOARD_LATE_INIT
1402 Support for Freescale LS1012A2G5RDB platform.
1403 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1404 development platform that supports the QorIQ LS1012A
1405 Layerscape Architecture processor.
1407 config TARGET_LS1012AFRWY
1408 bool "Support ls1012afrwy"
1411 select ARCH_SUPPORT_TFABOOT
1412 select BOARD_LATE_INIT
1416 Support for Freescale LS1012AFRWY platform.
1417 The LS1012A FRWY board (FRWY) is a high-performance
1418 development platform that supports the QorIQ LS1012A
1419 Layerscape Architecture processor.
1421 config TARGET_LS1012AFRDM
1422 bool "Support ls1012afrdm"
1425 select ARCH_SUPPORT_TFABOOT
1427 Support for Freescale LS1012AFRDM platform.
1428 The LS1012A Freedom board (FRDM) is a high-performance
1429 development platform that supports the QorIQ LS1012A
1430 Layerscape Architecture processor.
1432 config TARGET_LS1028AQDS
1433 bool "Support ls1028aqds"
1436 select ARMV8_MULTIENTRY
1437 select ARCH_SUPPORT_TFABOOT
1438 select BOARD_LATE_INIT
1440 Support for Freescale LS1028AQDS platform
1441 The LS1028A Development System (QDS) is a high-performance
1442 development platform that supports the QorIQ LS1028A
1443 Layerscape Architecture processor.
1445 config TARGET_LS1028ARDB
1446 bool "Support ls1028ardb"
1449 select ARMV8_MULTIENTRY
1450 select ARCH_SUPPORT_TFABOOT
1451 select BOARD_LATE_INIT
1453 Support for Freescale LS1028ARDB platform
1454 The LS1028A Development System (RDB) is a high-performance
1455 development platform that supports the QorIQ LS1028A
1456 Layerscape Architecture processor.
1458 config TARGET_LS1088ARDB
1459 bool "Support ls1088ardb"
1462 select ARMV8_MULTIENTRY
1463 select ARCH_SUPPORT_TFABOOT
1464 select BOARD_LATE_INIT
1466 select FSL_DDR_INTERACTIVE if !SD_BOOT
1468 Support for NXP LS1088ARDB platform.
1469 The LS1088A Reference design board (RDB) is a high-performance
1470 development platform that supports the QorIQ LS1088A
1471 Layerscape Architecture processor.
1473 config TARGET_LS1021AQDS
1474 bool "Support ls1021aqds"
1476 select ARCH_SUPPORT_PSCI
1477 select BOARD_EARLY_INIT_F
1478 select BOARD_LATE_INIT
1480 select CPU_V7_HAS_NONSEC
1481 select CPU_V7_HAS_VIRT
1482 select LS1_DEEP_SLEEP
1485 select FSL_DDR_INTERACTIVE
1486 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1487 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1490 config TARGET_LS1021ATWR
1491 bool "Support ls1021atwr"
1493 select ARCH_SUPPORT_PSCI
1494 select BOARD_EARLY_INIT_F
1495 select BOARD_LATE_INIT
1497 select CPU_V7_HAS_NONSEC
1498 select CPU_V7_HAS_VIRT
1499 select LS1_DEEP_SLEEP
1501 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1504 config TARGET_LS1021ATSN
1505 bool "Support ls1021atsn"
1507 select ARCH_SUPPORT_PSCI
1508 select BOARD_EARLY_INIT_F
1509 select BOARD_LATE_INIT
1511 select CPU_V7_HAS_NONSEC
1512 select CPU_V7_HAS_VIRT
1513 select LS1_DEEP_SLEEP
1517 config TARGET_LS1021AIOT
1518 bool "Support ls1021aiot"
1520 select ARCH_SUPPORT_PSCI
1521 select BOARD_LATE_INIT
1523 select CPU_V7_HAS_NONSEC
1524 select CPU_V7_HAS_VIRT
1526 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1529 Support for Freescale LS1021AIOT platform.
1530 The LS1021A Freescale board (IOT) is a high-performance
1531 development platform that supports the QorIQ LS1021A
1532 Layerscape Architecture processor.
1534 config TARGET_LS1043AQDS
1535 bool "Support ls1043aqds"
1538 select ARMV8_MULTIENTRY
1539 select ARCH_SUPPORT_TFABOOT
1540 select BOARD_EARLY_INIT_F
1541 select BOARD_LATE_INIT
1543 select FSL_DDR_INTERACTIVE if !SPL
1544 select FSL_DSPI if !SPL_NO_DSPI
1545 select DM_SPI_FLASH if FSL_DSPI
1549 Support for Freescale LS1043AQDS platform.
1551 config TARGET_LS1043ARDB
1552 bool "Support ls1043ardb"
1555 select ARMV8_MULTIENTRY
1556 select ARCH_SUPPORT_TFABOOT
1557 select BOARD_EARLY_INIT_F
1558 select BOARD_LATE_INIT
1560 select FSL_DSPI if !SPL_NO_DSPI
1561 select DM_SPI_FLASH if FSL_DSPI
1563 Support for Freescale LS1043ARDB platform.
1565 config TARGET_LS1046AQDS
1566 bool "Support ls1046aqds"
1569 select ARMV8_MULTIENTRY
1570 select ARCH_SUPPORT_TFABOOT
1571 select BOARD_EARLY_INIT_F
1572 select BOARD_LATE_INIT
1573 select DM_SPI_FLASH if DM_SPI
1575 select FSL_DDR_BIST if !SPL
1576 select FSL_DDR_INTERACTIVE if !SPL
1577 select FSL_DDR_INTERACTIVE if !SPL
1580 Support for Freescale LS1046AQDS platform.
1581 The LS1046A Development System (QDS) is a high-performance
1582 development platform that supports the QorIQ LS1046A
1583 Layerscape Architecture processor.
1585 config TARGET_LS1046ARDB
1586 bool "Support ls1046ardb"
1589 select ARMV8_MULTIENTRY
1590 select ARCH_SUPPORT_TFABOOT
1591 select BOARD_EARLY_INIT_F
1592 select BOARD_LATE_INIT
1593 select DM_SPI_FLASH if DM_SPI
1594 select POWER_MC34VR500
1597 select FSL_DDR_INTERACTIVE if !SPL
1600 Support for Freescale LS1046ARDB platform.
1601 The LS1046A Reference Design Board (RDB) is a high-performance
1602 development platform that supports the QorIQ LS1046A
1603 Layerscape Architecture processor.
1605 config TARGET_LS1046AFRWY
1606 bool "Support ls1046afrwy"
1609 select ARMV8_MULTIENTRY
1610 select ARCH_SUPPORT_TFABOOT
1611 select BOARD_EARLY_INIT_F
1612 select BOARD_LATE_INIT
1613 select DM_SPI_FLASH if DM_SPI
1616 Support for Freescale LS1046AFRWY platform.
1617 The LS1046A Freeway Board (FRWY) is a high-performance
1618 development platform that supports the QorIQ LS1046A
1619 Layerscape Architecture processor.
1621 config TARGET_COLIBRI_PXA270
1622 bool "Support colibri_pxa270"
1625 config ARCH_UNIPHIER
1626 bool "Socionext UniPhier SoCs"
1627 select BOARD_LATE_INIT
1637 select OF_BOARD_SETUP
1641 select SPL_BOARD_INIT if SPL
1642 select SPL_DM if SPL
1643 select SPL_LIBCOMMON_SUPPORT if SPL
1644 select SPL_LIBGENERIC_SUPPORT if SPL
1645 select SPL_OF_CONTROL if SPL
1646 select SPL_PINCTRL if SPL
1649 imply DISTRO_DEFAULTS
1652 Support for UniPhier SoC family developed by Socionext Inc.
1653 (formerly, System LSI Business Division of Panasonic Corporation)
1656 bool "Support STMicroelectronics STM32 MCU with cortex M"
1663 bool "Support STMicrolectronics SoCs"
1672 Support for STMicroelectronics STiH407/10 SoC family.
1673 This SoC is used on Linaro 96Board STiH410-B2260
1676 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1677 select ARCH_MISC_INIT
1678 select ARCH_SUPPORT_TFABOOT
1679 select BOARD_LATE_INIT
1688 select OF_SYSTEM_SETUP
1694 select SYS_THUMB_BUILD
1698 imply OF_LIBFDT_OVERLAY
1699 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1702 Support for STM32MP SoC family developed by STMicroelectronics,
1703 MPUs based on ARM cortex A core
1704 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1705 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1707 SPL is the unsecure FSBL for the basic boot chain.
1709 config ARCH_ROCKCHIP
1710 bool "Support Rockchip SoCs"
1712 select BINMAN if !ARM64
1722 select DM_USB if USB
1723 select ENABLE_ARM_SOC_BOOT0_HOOK
1726 select SPL_DM if SPL
1727 select SPL_DM_SPI if SPL
1728 select SPL_DM_SPI_FLASH if SPL
1730 select SYS_THUMB_BUILD if !ARM64
1733 imply DEBUG_UART_BOARD_INIT
1734 imply DISTRO_DEFAULTS
1736 imply SARADC_ROCKCHIP
1738 imply SPL_SYS_MALLOC_SIMPLE
1741 imply USB_FUNCTION_FASTBOOT
1743 config TARGET_THUNDERX_88XX
1744 bool "Support ThunderX 88xx"
1748 select SYS_CACHE_SHIFT_7
1751 bool "Support Aspeed SoCs"
1756 config TARGET_DURIAN
1757 bool "Support Phytium Durian Platform"
1760 Support for durian platform.
1761 It has 2GB Sdram, uart and pcie.
1763 config TARGET_PRESIDIO_ASIC
1764 bool "Support Cortina Presidio ASIC Platform"
1769 config ARCH_SUPPORT_TFABOOT
1773 bool "Support for booting from TF-A"
1774 depends on ARCH_SUPPORT_TFABOOT
1777 Enabling this will make a U-Boot binary that is capable of being
1778 booted via TF-A (Trusted Firmware for Cortex-A).
1780 config TI_SECURE_DEVICE
1781 bool "HS Device Type Support"
1782 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1784 If a high secure (HS) device type is being used, this config
1785 must be set. This option impacts various aspects of the
1786 build system (to create signed boot images that can be
1787 authenticated) and the code. See the doc/README.ti-secure
1788 file for further details.
1790 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1791 config ISW_ENTRY_ADDR
1792 hex "Address in memory or XIP address of bootloader entry point"
1793 default 0x402F4000 if AM43XX
1794 default 0x402F0400 if AM33XX
1795 default 0x40301350 if OMAP54XX
1797 After any reset, the boot ROM searches the boot media for a valid
1798 boot image. For non-XIP devices, the ROM then copies the image into
1799 internal memory. For all boot modes, after the ROM processes the
1800 boot image it eventually computes the entry point address depending
1801 on the device type (secure/non-secure), boot media (xip/non-xip) and
1805 source "arch/arm/mach-aspeed/Kconfig"
1807 source "arch/arm/mach-at91/Kconfig"
1809 source "arch/arm/mach-bcm283x/Kconfig"
1811 source "arch/arm/mach-bcmstb/Kconfig"
1813 source "arch/arm/mach-davinci/Kconfig"
1815 source "arch/arm/mach-exynos/Kconfig"
1817 source "arch/arm/mach-highbank/Kconfig"
1819 source "arch/arm/mach-integrator/Kconfig"
1821 source "arch/arm/mach-ipq40xx/Kconfig"
1823 source "arch/arm/mach-k3/Kconfig"
1825 source "arch/arm/mach-keystone/Kconfig"
1827 source "arch/arm/mach-kirkwood/Kconfig"
1829 source "arch/arm/mach-lpc32xx/Kconfig"
1831 source "arch/arm/mach-mvebu/Kconfig"
1833 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1835 source "arch/arm/mach-imx/mx2/Kconfig"
1837 source "arch/arm/mach-imx/mx3/Kconfig"
1839 source "arch/arm/mach-imx/mx5/Kconfig"
1841 source "arch/arm/mach-imx/mx6/Kconfig"
1843 source "arch/arm/mach-imx/mx7/Kconfig"
1845 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1847 source "arch/arm/mach-imx/imx8/Kconfig"
1849 source "arch/arm/mach-imx/imx8m/Kconfig"
1851 source "arch/arm/mach-imx/imxrt/Kconfig"
1853 source "arch/arm/mach-imx/mxs/Kconfig"
1855 source "arch/arm/mach-omap2/Kconfig"
1857 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1859 source "arch/arm/mach-orion5x/Kconfig"
1861 source "arch/arm/mach-owl/Kconfig"
1863 source "arch/arm/mach-rmobile/Kconfig"
1865 source "arch/arm/mach-meson/Kconfig"
1867 source "arch/arm/mach-mediatek/Kconfig"
1869 source "arch/arm/mach-qemu/Kconfig"
1871 source "arch/arm/mach-rockchip/Kconfig"
1873 source "arch/arm/mach-s5pc1xx/Kconfig"
1875 source "arch/arm/mach-snapdragon/Kconfig"
1877 source "arch/arm/mach-socfpga/Kconfig"
1879 source "arch/arm/mach-sti/Kconfig"
1881 source "arch/arm/mach-stm32/Kconfig"
1883 source "arch/arm/mach-stm32mp/Kconfig"
1885 source "arch/arm/mach-sunxi/Kconfig"
1887 source "arch/arm/mach-tegra/Kconfig"
1889 source "arch/arm/mach-u8500/Kconfig"
1891 source "arch/arm/mach-uniphier/Kconfig"
1893 source "arch/arm/cpu/armv7/vf610/Kconfig"
1895 source "arch/arm/mach-zynq/Kconfig"
1897 source "arch/arm/mach-zynqmp/Kconfig"
1899 source "arch/arm/mach-versal/Kconfig"
1901 source "arch/arm/mach-zynqmp-r5/Kconfig"
1903 source "arch/arm/cpu/armv7/Kconfig"
1905 source "arch/arm/cpu/armv8/Kconfig"
1907 source "arch/arm/mach-imx/Kconfig"
1909 source "arch/arm/mach-nexell/Kconfig"
1911 source "board/bosch/shc/Kconfig"
1912 source "board/bosch/guardian/Kconfig"
1913 source "board/CarMediaLab/flea3/Kconfig"
1914 source "board/Marvell/aspenite/Kconfig"
1915 source "board/Marvell/gplugd/Kconfig"
1916 source "board/armadeus/apf27/Kconfig"
1917 source "board/armltd/vexpress/Kconfig"
1918 source "board/armltd/vexpress64/Kconfig"
1919 source "board/cortina/presidio-asic/Kconfig"
1920 source "board/broadcom/bcm23550_w1d/Kconfig"
1921 source "board/broadcom/bcm28155_ap/Kconfig"
1922 source "board/broadcom/bcm963158/Kconfig"
1923 source "board/broadcom/bcm968360bg/Kconfig"
1924 source "board/broadcom/bcm968580xref/Kconfig"
1925 source "board/broadcom/bcmcygnus/Kconfig"
1926 source "board/broadcom/bcmnsp/Kconfig"
1927 source "board/broadcom/bcmns2/Kconfig"
1928 source "board/broadcom/bcmns3/Kconfig"
1929 source "board/cavium/thunderx/Kconfig"
1930 source "board/cirrus/edb93xx/Kconfig"
1931 source "board/eets/pdu001/Kconfig"
1932 source "board/emulation/qemu-arm/Kconfig"
1933 source "board/freescale/ls2080a/Kconfig"
1934 source "board/freescale/ls2080aqds/Kconfig"
1935 source "board/freescale/ls2080ardb/Kconfig"
1936 source "board/freescale/ls1088a/Kconfig"
1937 source "board/freescale/ls1028a/Kconfig"
1938 source "board/freescale/ls1021aqds/Kconfig"
1939 source "board/freescale/ls1043aqds/Kconfig"
1940 source "board/freescale/ls1021atwr/Kconfig"
1941 source "board/freescale/ls1021atsn/Kconfig"
1942 source "board/freescale/ls1021aiot/Kconfig"
1943 source "board/freescale/ls1046aqds/Kconfig"
1944 source "board/freescale/ls1043ardb/Kconfig"
1945 source "board/freescale/ls1046ardb/Kconfig"
1946 source "board/freescale/ls1046afrwy/Kconfig"
1947 source "board/freescale/ls1012aqds/Kconfig"
1948 source "board/freescale/ls1012ardb/Kconfig"
1949 source "board/freescale/ls1012afrdm/Kconfig"
1950 source "board/freescale/lx2160a/Kconfig"
1951 source "board/freescale/mx35pdk/Kconfig"
1952 source "board/freescale/s32v234evb/Kconfig"
1953 source "board/grinn/chiliboard/Kconfig"
1954 source "board/hisilicon/hikey/Kconfig"
1955 source "board/hisilicon/hikey960/Kconfig"
1956 source "board/hisilicon/poplar/Kconfig"
1957 source "board/isee/igep003x/Kconfig"
1958 source "board/spear/spear300/Kconfig"
1959 source "board/spear/spear310/Kconfig"
1960 source "board/spear/spear320/Kconfig"
1961 source "board/spear/spear600/Kconfig"
1962 source "board/spear/x600/Kconfig"
1963 source "board/st/stv0991/Kconfig"
1964 source "board/tcl/sl50/Kconfig"
1965 source "board/toradex/colibri_pxa270/Kconfig"
1966 source "board/variscite/dart_6ul/Kconfig"
1967 source "board/vscom/baltos/Kconfig"
1968 source "board/xilinx/Kconfig"
1969 source "board/xilinx/zynq/Kconfig"
1970 source "board/xilinx/zynqmp/Kconfig"
1971 source "board/phytium/durian/Kconfig"
1973 source "arch/arm/Kconfig.debug"
1978 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
1979 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
1980 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64