1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
17 be loaded to and run from that address. This option lifts that
18 restriction, thus allowing the code to be loaded to and executed from
19 almost any 4K aligned address. This logic relies on the relocation
20 information that is embedded in the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
23 config INIT_SP_RELATIVE
24 bool "Specify the early stack pointer relative to the .bss section"
25 default n if ARCH_QEMU
26 default y if POSITION_INDEPENDENT
28 U-Boot typically uses a hard-coded value for the stack pointer
29 before relocation. Enable this option to instead calculate the
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that it can be loaded and executed at arbitrary
32 addresses and thus avoid using arbitrary addresses at runtime.
34 If this option is enabled, the early stack pointer is set to
35 &_bss_start with a offset value added. The offset is specified by
36 SYS_INIT_SP_BSS_OFFSET.
38 config SYS_INIT_SP_BSS_OFFSET
39 int "Early stack offset from the .bss base address"
40 depends on INIT_SP_RELATIVE
43 This option's value is the offset added to &_bss_start in order to
44 calculate the stack pointer. This offset should be large enough so
45 that the early malloc region, global data (gd), and early stack usage
46 do not overlap any appended DTB.
48 config LINUX_KERNEL_IMAGE_HEADER
51 Place a Linux kernel image header at the start of the U-Boot binary.
52 The format of the header is described in the Linux kernel source at
53 Documentation/arm64/booting.txt. This feature is useful since the
54 image header reports the amount of memory (BSS and similar) that
55 U-Boot needs to use, but which isn't part of the binary.
57 if LINUX_KERNEL_IMAGE_HEADER
58 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
61 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
62 TEXT_OFFSET value written to the Linux kernel image header.
72 ARM GICV3 Interrupt translation service (ITS).
73 Basic support for programming locality specific peripheral
74 interrupts (LPI) configuration tables and enable LPI tables.
75 LPI configuration table can be used by u-boot or Linux.
76 ARM GICV3 has limitation, once the LPI table is enabled, LPI
77 configuration table can not be re-programmed, unless GICV3 reset.
83 config DMA_ADDR_T_64BIT
93 config GPIO_EXTRA_HEADER
96 # Used for compatibility with asm files copied from the kernel
97 config ARM_ASM_UNIFIED
101 # Used for compatibility with asm files copied from the kernel
105 config SYS_ICACHE_OFF
106 bool "Do not enable icache"
109 Do not enable instruction cache in U-Boot.
111 config SPL_SYS_ICACHE_OFF
112 bool "Do not enable icache in SPL"
114 default SYS_ICACHE_OFF
116 Do not enable instruction cache in SPL.
118 config SYS_DCACHE_OFF
119 bool "Do not enable dcache"
122 Do not enable data cache in U-Boot.
124 config SPL_SYS_DCACHE_OFF
125 bool "Do not enable dcache in SPL"
127 default SYS_DCACHE_OFF
129 Do not enable data cache in SPL.
131 config SYS_ARM_CACHE_CP15
132 bool "CP15 based cache enabling support"
134 Select this if your processor suports enabling caches by using
138 bool "MMU-based Paged Memory Management Support"
139 select SYS_ARM_CACHE_CP15
141 Select if you want MMU-based virtualised addressing space
142 support via paged memory management.
145 bool 'Use the ARM v7 PMSA Compliant MPU'
147 Some ARM systems without an MMU have instead a Memory Protection
148 Unit (MPU) that defines the type and permissions for regions of
150 If your CPU has an MPU then you should choose 'y' here unless you
151 know that you do not want to use the MPU.
153 # If set, the workarounds for these ARM errata are applied early during U-Boot
154 # startup. Note that in general these options force the workarounds to be
155 # applied; no CPU-type/version detection exists, unlike the similar options in
156 # the Linux kernel. Do not set these options unless they apply! Also note that
157 # the following can be machine-specific errata. These do have ability to
158 # provide rudimentary version and machine-specific checks, but expect no
160 # CONFIG_ARM_ERRATA_430973
161 # CONFIG_ARM_ERRATA_454179
162 # CONFIG_ARM_ERRATA_621766
163 # CONFIG_ARM_ERRATA_798870
164 # CONFIG_ARM_ERRATA_801819
165 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
166 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
168 config ARM_ERRATA_430973
171 config ARM_ERRATA_454179
174 config ARM_ERRATA_621766
177 config ARM_ERRATA_716044
180 config ARM_ERRATA_725233
183 config ARM_ERRATA_742230
186 config ARM_ERRATA_743622
189 config ARM_ERRATA_751472
192 config ARM_ERRATA_761320
195 config ARM_ERRATA_773022
198 config ARM_ERRATA_774769
201 config ARM_ERRATA_794072
204 config ARM_ERRATA_798870
207 config ARM_ERRATA_801819
210 config ARM_ERRATA_826974
213 config ARM_ERRATA_828024
216 config ARM_ERRATA_829520
219 config ARM_ERRATA_833069
222 config ARM_ERRATA_833471
225 config ARM_ERRATA_845369
228 config ARM_ERRATA_852421
231 config ARM_ERRATA_852423
234 config ARM_ERRATA_855873
237 config ARM_CORTEX_A8_CVE_2017_5715
240 config ARM_CORTEX_A15_CVE_2017_5715
245 select SYS_CACHE_SHIFT_5
250 select SYS_CACHE_SHIFT_5
255 select SYS_CACHE_SHIFT_5
260 select SYS_CACHE_SHIFT_5
265 select SYS_CACHE_SHIFT_5
271 select SYS_CACHE_SHIFT_5
278 select SYS_CACHE_SHIFT_6
285 select SYS_CACHE_SHIFT_5
286 select SYS_THUMB_BUILD
292 select SYS_ARM_CACHE_CP15
294 select SYS_CACHE_SHIFT_6
298 select SYS_CACHE_SHIFT_5
303 select SYS_CACHE_SHIFT_5
307 default "arm720t" if CPU_ARM720T
308 default "arm920t" if CPU_ARM920T
309 default "arm926ejs" if CPU_ARM926EJS
310 default "arm946es" if CPU_ARM946ES
311 default "arm1136" if CPU_ARM1136
312 default "arm1176" if CPU_ARM1176
313 default "armv7" if CPU_V7A
314 default "armv7" if CPU_V7R
315 default "armv7m" if CPU_V7M
316 default "pxa" if CPU_PXA
317 default "sa1100" if CPU_SA1100
318 default "armv8" if ARM64
322 default 4 if CPU_ARM720T
323 default 4 if CPU_ARM920T
324 default 5 if CPU_ARM926EJS
325 default 5 if CPU_ARM946ES
326 default 6 if CPU_ARM1136
327 default 6 if CPU_ARM1176
332 default 4 if CPU_SA1100
335 config SYS_CACHE_SHIFT_5
338 config SYS_CACHE_SHIFT_6
341 config SYS_CACHE_SHIFT_7
344 config SYS_CACHELINE_SIZE
346 default 128 if SYS_CACHE_SHIFT_7
347 default 64 if SYS_CACHE_SHIFT_6
348 default 32 if SYS_CACHE_SHIFT_5
351 prompt "Select the ARM data write cache policy"
352 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
354 default SYS_ARM_CACHE_WRITEBACK
356 config SYS_ARM_CACHE_WRITEBACK
357 bool "Write-back (WB)"
359 A write updates the cache only and marks the cache line as dirty.
360 External memory is updated only when the line is evicted or explicitly
363 config SYS_ARM_CACHE_WRITETHROUGH
364 bool "Write-through (WT)"
366 A write updates both the cache and the external memory system.
367 This does not mark the cache line as dirty.
369 config SYS_ARM_CACHE_WRITEALLOC
370 bool "Write allocation (WA)"
372 A cache line is allocated on a write miss. This means that executing a
373 store instruction on the processor might cause a burst read to occur.
374 There is a linefill to obtain the data for the cache line, before the
379 bool "Enable ARCH_CPU_INIT"
381 Some architectures require a call to arch_cpu_init().
382 Say Y here to enable it
384 config SYS_ARCH_TIMER
385 bool "ARM Generic Timer support"
386 depends on CPU_V7A || ARM64
389 The ARM Generic Timer (aka arch-timer) provides an architected
390 interface to a timer source on an SoC.
391 It is mandatory for ARMv8 implementation and widely available
395 bool "Support for ARM SMC Calling Convention (SMCCC)"
396 depends on CPU_V7A || ARM64
399 Say Y here if you want to enable ARM SMC Calling Convention.
400 This should be enabled if U-Boot needs to communicate with system
401 firmware (for example, PSCI) according to SMCCC.
404 bool "support boot from semihosting"
406 In emulated environments, semihosting is a way for
407 the hosted environment to call out to the emulator to
408 retrieve files from the host machine.
410 config SYS_THUMB_BUILD
411 bool "Build U-Boot using the Thumb instruction set"
414 Use this flag to build U-Boot using the Thumb instruction set for
415 ARM architectures. Thumb instruction set provides better code
416 density. For ARM architectures that support Thumb2 this flag will
417 result in Thumb2 code generated by GCC.
419 config SPL_SYS_THUMB_BUILD
420 bool "Build SPL using the Thumb instruction set"
421 default y if SYS_THUMB_BUILD
422 depends on !ARM64 && SPL
424 Use this flag to build SPL using the Thumb instruction set for
425 ARM architectures. Thumb instruction set provides better code
426 density. For ARM architectures that support Thumb2 this flag will
427 result in Thumb2 code generated by GCC.
429 config TPL_SYS_THUMB_BUILD
430 bool "Build TPL using the Thumb instruction set"
431 default y if SYS_THUMB_BUILD
432 depends on TPL && !ARM64
434 Use this flag to build TPL using the Thumb instruction set for
435 ARM architectures. Thumb instruction set provides better code
436 density. For ARM architectures that support Thumb2 this flag will
437 result in Thumb2 code generated by GCC.
440 config SYS_L2CACHE_OFF
443 If SoC does not support L2CACHE or one does not want to enable
444 L2CACHE, choose this option.
446 config ENABLE_ARM_SOC_BOOT0_HOOK
447 bool "prepare BOOT0 header"
449 If the SoC's BOOT0 requires a header area filled with (magic)
450 values, then choose this option, and create a file included as
451 <asm/arch/boot0.h> which contains the required assembler code.
453 config ARM_CORTEX_CPU_IS_UP
457 config USE_ARCH_MEMCPY
458 bool "Use an assembly optimized implementation of memcpy"
462 Enable the generation of an optimized version of memcpy.
463 Such an implementation may be faster under some conditions
464 but may increase the binary size.
466 config SPL_USE_ARCH_MEMCPY
467 bool "Use an assembly optimized implementation of memcpy for SPL"
468 default y if USE_ARCH_MEMCPY
469 depends on !ARM64 && SPL
471 Enable the generation of an optimized version of memcpy.
472 Such an implementation may be faster under some conditions
473 but may increase the binary size.
475 config TPL_USE_ARCH_MEMCPY
476 bool "Use an assembly optimized implementation of memcpy for TPL"
477 default y if USE_ARCH_MEMCPY
478 depends on !ARM64 && TPL
480 Enable the generation of an optimized version of memcpy.
481 Such an implementation may be faster under some conditions
482 but may increase the binary size.
484 config USE_ARCH_MEMSET
485 bool "Use an assembly optimized implementation of memset"
489 Enable the generation of an optimized version of memset.
490 Such an implementation may be faster under some conditions
491 but may increase the binary size.
493 config SPL_USE_ARCH_MEMSET
494 bool "Use an assembly optimized implementation of memset for SPL"
495 default y if USE_ARCH_MEMSET
496 depends on !ARM64 && SPL
498 Enable the generation of an optimized version of memset.
499 Such an implementation may be faster under some conditions
500 but may increase the binary size.
502 config TPL_USE_ARCH_MEMSET
503 bool "Use an assembly optimized implementation of memset for TPL"
504 default y if USE_ARCH_MEMSET
505 depends on !ARM64 && TPL
507 Enable the generation of an optimized version of memset.
508 Such an implementation may be faster under some conditions
509 but may increase the binary size.
511 config ARM64_SUPPORT_AARCH32
512 bool "ARM64 system support AArch32 execution state"
514 default y if !TARGET_THUNDERX_88XX
516 This ARM64 system supports AArch32 execution state.
519 prompt "Target select"
524 select GPIO_EXTRA_HEADER
525 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
526 select SPL_SEPARATE_BSS if SPL
528 config TARGET_ASPENITE
529 bool "Support aspenite"
531 select GPIO_EXTRA_HEADER
536 select GPIO_EXTRA_HEADER
537 select SPL_DM_SPI if SPL
540 Support for TI's DaVinci platform.
543 bool "Marvell Kirkwood"
544 select ARCH_MISC_INIT
545 select BOARD_EARLY_INIT_F
547 select GPIO_EXTRA_HEADER
550 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
556 select GPIO_EXTRA_HEADER
557 select SPL_DM_SPI if SPL
558 select SPL_DM_SPI_FLASH if SPL
567 select GPIO_EXTRA_HEADER
569 config TARGET_SPEAR320
570 bool "Support spear320"
571 select BOARD_EARLY_INIT_F
573 select GPIO_EXTRA_HEADER
577 config TARGET_SPEAR600
578 bool "Support spear600"
579 select BOARD_EARLY_INIT_F
581 select GPIO_EXTRA_HEADER
585 config TARGET_STV0991
586 bool "Support stv0991"
592 select GPIO_EXTRA_HEADER
600 select BOARD_LATE_INIT
602 select GPIO_EXTRA_HEADER
609 select GPIO_EXTRA_HEADER
612 bool "Broadcom BCM283X family"
616 select GPIO_EXTRA_HEADER
619 select SERIAL_SEARCH_ALL
624 bool "Broadcom BCM63158 family"
630 bool "Broadcom BCM68360 family"
636 bool "Broadcom BCM6858 family"
642 bool "Broadcom BCM7XXX family"
645 select GPIO_EXTRA_HEADER
647 select OF_PRIOR_STAGE
650 This enables support for Broadcom ARM-based set-top box
651 chipsets, including the 7445 family of chips.
653 config TARGET_BCMCYGNUS
654 bool "Support bcmcygnus"
656 select GPIO_EXTRA_HEADER
658 imply BCM_SF2_ETH_GMAC
666 bool "Support Broadcom Northstar2"
668 select GPIO_EXTRA_HEADER
670 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
671 ARMv8 Cortex-A57 processors targeting a broad range of networking
675 bool "Support Broadcom NS3"
677 select BOARD_LATE_INIT
679 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
680 ARMv8 Cortex-A72 processors targeting a broad range of networking
684 bool "Samsung EXYNOS"
693 select GPIO_EXTRA_HEADER
694 imply SYS_THUMB_BUILD
699 bool "Samsung S5PC1XX"
705 select GPIO_EXTRA_HEADER
709 bool "Calxeda Highbank"
722 config ARCH_INTEGRATOR
723 bool "ARM Ltd. Integrator family"
726 select GPIO_EXTRA_HEADER
731 bool "Qualcomm IPQ40xx SoCs"
737 select GPIO_EXTRA_HEADER
749 select GPIO_EXTRA_HEADER
751 select SYS_ARCH_TIMER
752 select SYS_THUMB_BUILD
758 bool "Texas Instruments' K3 Architecture"
763 config ARCH_OMAP2PLUS
766 select GPIO_EXTRA_HEADER
767 select SPL_BOARD_INIT if SPL
768 select SPL_STACK_R if SPL
770 imply TI_SYSC if DM && OF_CONTROL
775 select GPIO_EXTRA_HEADER
776 imply DISTRO_DEFAULTS
779 Support for the Meson SoC family developed by Amlogic Inc.,
780 targeted at media players and tablet computers. We currently
781 support the S905 (GXBaby) 64-bit SoC.
786 select GPIO_EXTRA_HEADER
789 select SPL_LIBCOMMON_SUPPORT if SPL
790 select SPL_LIBGENERIC_SUPPORT if SPL
791 select SPL_OF_CONTROL if SPL
794 Support for the MediaTek SoCs family developed by MediaTek Inc.
795 Please refer to doc/README.mediatek for more information.
798 bool "NXP LPC32xx platform"
803 select GPIO_EXTRA_HEADER
809 bool "NXP i.MX8 platform"
812 select GPIO_EXTRA_HEADER
814 select ENABLE_ARM_SOC_BOOT0_HOOK
817 bool "NXP i.MX8M platform"
819 select GPIO_EXTRA_HEADER
820 select SYS_FSL_HAS_SEC if IMX_HAB
821 select SYS_FSL_SEC_COMPAT_4
822 select SYS_FSL_SEC_LE
828 bool "NXP i.MXRT platform"
832 select GPIO_EXTRA_HEADER
837 bool "NXP i.MX23 family"
839 select GPIO_EXTRA_HEADER
846 select GPIO_EXTRA_HEADER
850 bool "NXP i.MX28 family"
852 select GPIO_EXTRA_HEADER
857 bool "NXP i.MX31 family"
859 select GPIO_EXTRA_HEADER
864 select GPIO_EXTRA_HEADER
865 select SYS_FSL_HAS_SEC if IMX_HAB
866 select SYS_FSL_SEC_COMPAT_4
867 select SYS_FSL_SEC_LE
868 select ROM_UNIFIED_SECTIONS
870 imply SYS_THUMB_BUILD
874 select ARCH_MISC_INIT
876 select GPIO_EXTRA_HEADER
877 select SYS_FSL_HAS_SEC if IMX_HAB
878 select SYS_FSL_SEC_COMPAT_4
879 select SYS_FSL_SEC_LE
880 imply BOARD_EARLY_INIT_F
882 imply SYS_THUMB_BUILD
887 select GPIO_EXTRA_HEADER
888 select SYS_FSL_HAS_SEC
889 select SYS_FSL_SEC_COMPAT_4
890 select SYS_FSL_SEC_LE
892 imply SYS_THUMB_BUILD
896 default "arch/arm/mach-omap2/u-boot-spl.lds"
901 select BOARD_EARLY_INIT_F
903 select GPIO_EXTRA_HEADER
907 bool "Nexell S5P4418/S5P6818 SoC"
908 select ENABLE_ARM_SOC_BOOT0_HOOK
910 select GPIO_EXTRA_HEADER
913 bool "Actions Semi OWL SoCs"
917 select GPIO_EXTRA_HEADER
922 select SYS_RELOC_GD_ENV_ADDR
926 bool "QEMU Virtual Platform"
937 bool "Renesas ARM SoCs"
940 select GPIO_EXTRA_HEADER
941 imply BOARD_EARLY_INIT_F
944 imply SYS_THUMB_BUILD
945 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
947 config ARCH_SNAPDRAGON
948 bool "Qualcomm Snapdragon SoCs"
953 select GPIO_EXTRA_HEADER
962 bool "Altera SOCFPGA family"
963 select ARCH_EARLY_INIT_R
964 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
965 select ARM64 if TARGET_SOCFPGA_SOC64
966 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
969 select GPIO_EXTRA_HEADER
970 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
972 select SPL_DM_RESET if DM_RESET
974 select SPL_LIBCOMMON_SUPPORT
975 select SPL_LIBGENERIC_SUPPORT
976 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
977 select SPL_OF_CONTROL
978 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
979 select SPL_SERIAL_SUPPORT
981 select SPL_WATCHDOG_SUPPORT
984 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
986 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
987 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
997 imply SPL_DM_SPI_FLASH
998 imply SPL_LIBDISK_SUPPORT
999 imply SPL_MMC_SUPPORT
1000 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1001 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1002 imply SPL_SPI_FLASH_SUPPORT
1003 imply SPL_SPI_SUPPORT
1007 bool "Support sunxi (Allwinner) SoCs"
1010 select CMD_MMC if MMC
1011 select CMD_USB if DISTRO_DEFAULTS
1017 select DM_MMC if MMC
1018 select DM_SCSI if SCSI
1020 select DM_USB if DISTRO_DEFAULTS
1021 select GPIO_EXTRA_HEADER
1022 select OF_BOARD_SETUP
1025 select SPECIFY_CONSOLE_INDEX
1026 select SPL_STACK_R if SPL
1027 select SPL_SYS_MALLOC_SIMPLE if SPL
1028 select SPL_SYS_THUMB_BUILD if !ARM64
1031 select SYS_THUMB_BUILD if !ARM64
1032 select USB if DISTRO_DEFAULTS
1033 select USB_KEYBOARD if DISTRO_DEFAULTS
1034 select USB_STORAGE if DISTRO_DEFAULTS
1035 select SPL_USE_TINY_PRINTF
1037 select SYS_RELOC_GD_ENV_ADDR
1038 imply BOARD_LATE_INIT
1041 imply CMD_UBI if MTD_RAW_NAND
1042 imply DISTRO_DEFAULTS
1045 imply OF_LIBFDT_OVERLAY
1046 imply PRE_CONSOLE_BUFFER
1047 imply SPL_GPIO_SUPPORT
1048 imply SPL_LIBCOMMON_SUPPORT
1049 imply SPL_LIBGENERIC_SUPPORT
1050 imply SPL_MMC_SUPPORT if MMC
1051 imply SPL_POWER_SUPPORT
1052 imply SPL_SERIAL_SUPPORT
1056 bool "ST-Ericsson U8500 Series"
1060 select DM_MMC if MMC
1062 select DM_USB if USB
1066 imply ARM_PL180_MMCI
1068 imply NOMADIK_MTU_TIMER
1071 imply SYSRESET_SYSCON
1074 bool "Support Xilinx Versal Platform"
1078 select DM_ETH if NET
1079 select DM_MMC if MMC
1081 select GPIO_EXTRA_HEADER
1083 imply BOARD_LATE_INIT
1084 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1087 bool "Freescale Vybrid"
1089 select GPIO_EXTRA_HEADER
1090 select SYS_FSL_ERRATUM_ESDHC111
1095 bool "Xilinx Zynq based platform"
1100 select DM_ETH if NET
1101 select DM_MMC if MMC
1105 select DM_USB if USB
1106 select GPIO_EXTRA_HEADER
1109 select SPL_BOARD_INIT if SPL
1110 select SPL_CLK if SPL
1111 select SPL_DM if SPL
1112 select SPL_DM_SPI if SPL
1113 select SPL_DM_SPI_FLASH if SPL
1114 select SPL_OF_CONTROL if SPL
1115 select SPL_SEPARATE_BSS if SPL
1117 imply ARCH_EARLY_INIT_R
1118 imply BOARD_LATE_INIT
1122 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1125 config ARCH_ZYNQMP_R5
1126 bool "Xilinx ZynqMP R5 based platform"
1130 select DM_ETH if NET
1131 select DM_MMC if MMC
1133 select GPIO_EXTRA_HEADER
1139 bool "Xilinx ZynqMP based platform"
1143 select DM_ETH if NET
1145 select DM_MMC if MMC
1147 select DM_SPI if SPI
1148 select DM_SPI_FLASH if DM_SPI
1149 select DM_USB if USB
1151 select GPIO_EXTRA_HEADER
1153 select SPL_BOARD_INIT if SPL
1154 select SPL_CLK if SPL
1155 select SPL_DM if SPL
1156 select SPL_DM_SPI if SPI && SPL_DM
1157 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1158 select SPL_DM_MAILBOX if SPL
1159 select SPL_FIRMWARE if SPL
1160 select SPL_SEPARATE_BSS if SPL
1163 imply BOARD_LATE_INIT
1165 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1172 select GPIO_EXTRA_HEADER
1173 imply DISTRO_DEFAULTS
1176 config TARGET_VEXPRESS64_AEMV8A
1177 bool "Support vexpress_aemv8a"
1179 select GPIO_EXTRA_HEADER
1182 config TARGET_VEXPRESS64_BASE_FVP
1183 bool "Support Versatile Express ARMv8a FVP BASE model"
1185 select GPIO_EXTRA_HEADER
1189 config TARGET_VEXPRESS64_JUNO
1190 bool "Support Versatile Express Juno Development Platform"
1192 select GPIO_EXTRA_HEADER
1206 config TARGET_TOTAL_COMPUTE
1207 bool "Support Total Compute Platform"
1215 config TARGET_LS2080A_EMU
1216 bool "Support ls2080a_emu"
1219 select ARMV8_MULTIENTRY
1220 select FSL_DDR_SYNC_REFRESH
1221 select GPIO_EXTRA_HEADER
1223 Support for Freescale LS2080A_EMU platform.
1224 The LS2080A Development System (EMULATOR) is a pre-silicon
1225 development platform that supports the QorIQ LS2080A
1226 Layerscape Architecture processor.
1228 config TARGET_LS1088AQDS
1229 bool "Support ls1088aqds"
1232 select ARMV8_MULTIENTRY
1233 select ARCH_SUPPORT_TFABOOT
1234 select BOARD_LATE_INIT
1235 select GPIO_EXTRA_HEADER
1237 select FSL_DDR_INTERACTIVE if !SD_BOOT
1239 Support for NXP LS1088AQDS platform.
1240 The LS1088A Development System (QDS) is a high-performance
1241 development platform that supports the QorIQ LS1088A
1242 Layerscape Architecture processor.
1244 config TARGET_LS2080AQDS
1245 bool "Support ls2080aqds"
1248 select ARMV8_MULTIENTRY
1249 select ARCH_SUPPORT_TFABOOT
1250 select BOARD_LATE_INIT
1251 select GPIO_EXTRA_HEADER
1256 select FSL_DDR_INTERACTIVE if !SPL
1258 Support for Freescale LS2080AQDS platform.
1259 The LS2080A Development System (QDS) is a high-performance
1260 development platform that supports the QorIQ LS2080A
1261 Layerscape Architecture processor.
1263 config TARGET_LS2080ARDB
1264 bool "Support ls2080ardb"
1267 select ARMV8_MULTIENTRY
1268 select ARCH_SUPPORT_TFABOOT
1269 select BOARD_LATE_INIT
1272 select FSL_DDR_INTERACTIVE if !SPL
1273 select GPIO_EXTRA_HEADER
1277 Support for Freescale LS2080ARDB platform.
1278 The LS2080A Reference design board (RDB) is a high-performance
1279 development platform that supports the QorIQ LS2080A
1280 Layerscape Architecture processor.
1282 config TARGET_LS2081ARDB
1283 bool "Support ls2081ardb"
1286 select ARMV8_MULTIENTRY
1287 select BOARD_LATE_INIT
1288 select GPIO_EXTRA_HEADER
1291 Support for Freescale LS2081ARDB platform.
1292 The LS2081A Reference design board (RDB) is a high-performance
1293 development platform that supports the QorIQ LS2081A/LS2041A
1294 Layerscape Architecture processor.
1296 config TARGET_LX2160ARDB
1297 bool "Support lx2160ardb"
1300 select ARMV8_MULTIENTRY
1301 select ARCH_SUPPORT_TFABOOT
1302 select BOARD_LATE_INIT
1303 select GPIO_EXTRA_HEADER
1305 Support for NXP LX2160ARDB platform.
1306 The lx2160ardb (LX2160A Reference design board (RDB)
1307 is a high-performance development platform that supports the
1308 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1310 config TARGET_LX2160AQDS
1311 bool "Support lx2160aqds"
1314 select ARMV8_MULTIENTRY
1315 select ARCH_SUPPORT_TFABOOT
1316 select BOARD_LATE_INIT
1317 select GPIO_EXTRA_HEADER
1319 Support for NXP LX2160AQDS platform.
1320 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1321 is a high-performance development platform that supports the
1322 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1324 config TARGET_LX2162AQDS
1325 bool "Support lx2162aqds"
1327 select ARCH_MISC_INIT
1329 select ARMV8_MULTIENTRY
1330 select ARCH_SUPPORT_TFABOOT
1331 select BOARD_LATE_INIT
1332 select GPIO_EXTRA_HEADER
1334 Support for NXP LX2162AQDS platform.
1335 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1338 bool "Support HiKey 96boards Consumer Edition Platform"
1343 select GPIO_EXTRA_HEADER
1346 select SPECIFY_CONSOLE_INDEX
1349 Support for HiKey 96boards platform. It features a HI6220
1350 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1352 config TARGET_HIKEY960
1353 bool "Support HiKey960 96boards Consumer Edition Platform"
1357 select GPIO_EXTRA_HEADER
1362 Support for HiKey960 96boards platform. It features a HI3660
1363 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1365 config TARGET_POPLAR
1366 bool "Support Poplar 96boards Enterprise Edition Platform"
1371 select GPIO_EXTRA_HEADER
1376 Support for Poplar 96boards EE platform. It features a HI3798cv200
1377 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1378 making it capable of running any commercial set-top solution based on
1381 config TARGET_LS1012AQDS
1382 bool "Support ls1012aqds"
1385 select ARCH_SUPPORT_TFABOOT
1386 select BOARD_LATE_INIT
1387 select GPIO_EXTRA_HEADER
1389 Support for Freescale LS1012AQDS platform.
1390 The LS1012A Development System (QDS) is a high-performance
1391 development platform that supports the QorIQ LS1012A
1392 Layerscape Architecture processor.
1394 config TARGET_LS1012ARDB
1395 bool "Support ls1012ardb"
1398 select ARCH_SUPPORT_TFABOOT
1399 select BOARD_LATE_INIT
1400 select GPIO_EXTRA_HEADER
1404 Support for Freescale LS1012ARDB platform.
1405 The LS1012A Reference design board (RDB) is a high-performance
1406 development platform that supports the QorIQ LS1012A
1407 Layerscape Architecture processor.
1409 config TARGET_LS1012A2G5RDB
1410 bool "Support ls1012a2g5rdb"
1413 select ARCH_SUPPORT_TFABOOT
1414 select BOARD_LATE_INIT
1415 select GPIO_EXTRA_HEADER
1418 Support for Freescale LS1012A2G5RDB platform.
1419 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1420 development platform that supports the QorIQ LS1012A
1421 Layerscape Architecture processor.
1423 config TARGET_LS1012AFRWY
1424 bool "Support ls1012afrwy"
1427 select ARCH_SUPPORT_TFABOOT
1428 select BOARD_LATE_INIT
1429 select GPIO_EXTRA_HEADER
1433 Support for Freescale LS1012AFRWY platform.
1434 The LS1012A FRWY board (FRWY) is a high-performance
1435 development platform that supports the QorIQ LS1012A
1436 Layerscape Architecture processor.
1438 config TARGET_LS1012AFRDM
1439 bool "Support ls1012afrdm"
1442 select ARCH_SUPPORT_TFABOOT
1443 select GPIO_EXTRA_HEADER
1445 Support for Freescale LS1012AFRDM platform.
1446 The LS1012A Freedom board (FRDM) is a high-performance
1447 development platform that supports the QorIQ LS1012A
1448 Layerscape Architecture processor.
1450 config TARGET_LS1028AQDS
1451 bool "Support ls1028aqds"
1454 select ARMV8_MULTIENTRY
1455 select ARCH_SUPPORT_TFABOOT
1456 select BOARD_LATE_INIT
1457 select GPIO_EXTRA_HEADER
1459 Support for Freescale LS1028AQDS platform
1460 The LS1028A Development System (QDS) is a high-performance
1461 development platform that supports the QorIQ LS1028A
1462 Layerscape Architecture processor.
1464 config TARGET_LS1028ARDB
1465 bool "Support ls1028ardb"
1468 select ARMV8_MULTIENTRY
1469 select ARCH_SUPPORT_TFABOOT
1470 select BOARD_LATE_INIT
1471 select GPIO_EXTRA_HEADER
1473 Support for Freescale LS1028ARDB platform
1474 The LS1028A Development System (RDB) is a high-performance
1475 development platform that supports the QorIQ LS1028A
1476 Layerscape Architecture processor.
1478 config TARGET_LS1088ARDB
1479 bool "Support ls1088ardb"
1482 select ARMV8_MULTIENTRY
1483 select ARCH_SUPPORT_TFABOOT
1484 select BOARD_LATE_INIT
1486 select FSL_DDR_INTERACTIVE if !SD_BOOT
1487 select GPIO_EXTRA_HEADER
1489 Support for NXP LS1088ARDB platform.
1490 The LS1088A Reference design board (RDB) is a high-performance
1491 development platform that supports the QorIQ LS1088A
1492 Layerscape Architecture processor.
1494 config TARGET_LS1021AQDS
1495 bool "Support ls1021aqds"
1497 select ARCH_SUPPORT_PSCI
1498 select BOARD_EARLY_INIT_F
1499 select BOARD_LATE_INIT
1501 select CPU_V7_HAS_NONSEC
1502 select CPU_V7_HAS_VIRT
1503 select LS1_DEEP_SLEEP
1506 select FSL_DDR_INTERACTIVE
1507 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1508 select GPIO_EXTRA_HEADER
1509 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1512 config TARGET_LS1021ATWR
1513 bool "Support ls1021atwr"
1515 select ARCH_SUPPORT_PSCI
1516 select BOARD_EARLY_INIT_F
1517 select BOARD_LATE_INIT
1519 select CPU_V7_HAS_NONSEC
1520 select CPU_V7_HAS_VIRT
1521 select LS1_DEEP_SLEEP
1523 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1524 select GPIO_EXTRA_HEADER
1527 config TARGET_PG_WCOM_SELI8
1528 bool "Support Hitachi-Powergrids SELI8 service unit card"
1530 select ARCH_SUPPORT_PSCI
1531 select BOARD_EARLY_INIT_F
1532 select BOARD_LATE_INIT
1534 select CPU_V7_HAS_NONSEC
1535 select CPU_V7_HAS_VIRT
1537 select FSL_DDR_INTERACTIVE
1538 select GPIO_EXTRA_HEADER
1542 Support for Hitachi-Powergrids SELI8 service unit card.
1543 SELI8 is a QorIQ LS1021a based service unit card used
1544 in XMC20 and FOX615 product families.
1546 config TARGET_PG_WCOM_EXPU1
1547 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1549 select ARCH_SUPPORT_PSCI
1550 select BOARD_EARLY_INIT_F
1551 select BOARD_LATE_INIT
1553 select CPU_V7_HAS_NONSEC
1554 select CPU_V7_HAS_VIRT
1556 select FSL_DDR_INTERACTIVE
1560 Support for Hitachi-Powergrids EXPU1 service unit card.
1561 EXPU1 is a QorIQ LS1021a based service unit card used
1562 in XMC20 and FOX615 product families.
1564 config TARGET_LS1021ATSN
1565 bool "Support ls1021atsn"
1567 select ARCH_SUPPORT_PSCI
1568 select BOARD_EARLY_INIT_F
1569 select BOARD_LATE_INIT
1571 select CPU_V7_HAS_NONSEC
1572 select CPU_V7_HAS_VIRT
1573 select LS1_DEEP_SLEEP
1575 select GPIO_EXTRA_HEADER
1578 config TARGET_LS1021AIOT
1579 bool "Support ls1021aiot"
1581 select ARCH_SUPPORT_PSCI
1582 select BOARD_LATE_INIT
1584 select CPU_V7_HAS_NONSEC
1585 select CPU_V7_HAS_VIRT
1587 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1588 select GPIO_EXTRA_HEADER
1591 Support for Freescale LS1021AIOT platform.
1592 The LS1021A Freescale board (IOT) is a high-performance
1593 development platform that supports the QorIQ LS1021A
1594 Layerscape Architecture processor.
1596 config TARGET_LS1043AQDS
1597 bool "Support ls1043aqds"
1600 select ARMV8_MULTIENTRY
1601 select ARCH_SUPPORT_TFABOOT
1602 select BOARD_EARLY_INIT_F
1603 select BOARD_LATE_INIT
1605 select FSL_DDR_INTERACTIVE if !SPL
1606 select FSL_DSPI if !SPL_NO_DSPI
1607 select DM_SPI_FLASH if FSL_DSPI
1608 select GPIO_EXTRA_HEADER
1612 Support for Freescale LS1043AQDS platform.
1614 config TARGET_LS1043ARDB
1615 bool "Support ls1043ardb"
1618 select ARMV8_MULTIENTRY
1619 select ARCH_SUPPORT_TFABOOT
1620 select BOARD_EARLY_INIT_F
1621 select BOARD_LATE_INIT
1623 select FSL_DSPI if !SPL_NO_DSPI
1624 select DM_SPI_FLASH if FSL_DSPI
1625 select GPIO_EXTRA_HEADER
1627 Support for Freescale LS1043ARDB platform.
1629 config TARGET_LS1046AQDS
1630 bool "Support ls1046aqds"
1633 select ARMV8_MULTIENTRY
1634 select ARCH_SUPPORT_TFABOOT
1635 select BOARD_EARLY_INIT_F
1636 select BOARD_LATE_INIT
1637 select DM_SPI_FLASH if DM_SPI
1639 select FSL_DDR_BIST if !SPL
1640 select FSL_DDR_INTERACTIVE if !SPL
1641 select FSL_DDR_INTERACTIVE if !SPL
1642 select GPIO_EXTRA_HEADER
1645 Support for Freescale LS1046AQDS platform.
1646 The LS1046A Development System (QDS) is a high-performance
1647 development platform that supports the QorIQ LS1046A
1648 Layerscape Architecture processor.
1650 config TARGET_LS1046ARDB
1651 bool "Support ls1046ardb"
1654 select ARMV8_MULTIENTRY
1655 select ARCH_SUPPORT_TFABOOT
1656 select BOARD_EARLY_INIT_F
1657 select BOARD_LATE_INIT
1658 select DM_SPI_FLASH if DM_SPI
1659 select POWER_MC34VR500
1662 select FSL_DDR_INTERACTIVE if !SPL
1663 select GPIO_EXTRA_HEADER
1666 Support for Freescale LS1046ARDB platform.
1667 The LS1046A Reference Design Board (RDB) is a high-performance
1668 development platform that supports the QorIQ LS1046A
1669 Layerscape Architecture processor.
1671 config TARGET_LS1046AFRWY
1672 bool "Support ls1046afrwy"
1675 select ARMV8_MULTIENTRY
1676 select ARCH_SUPPORT_TFABOOT
1677 select BOARD_EARLY_INIT_F
1678 select BOARD_LATE_INIT
1679 select DM_SPI_FLASH if DM_SPI
1680 select GPIO_EXTRA_HEADER
1683 Support for Freescale LS1046AFRWY platform.
1684 The LS1046A Freeway Board (FRWY) is a high-performance
1685 development platform that supports the QorIQ LS1046A
1686 Layerscape Architecture processor.
1692 select ARMV8_MULTIENTRY
1709 select GPIO_EXTRA_HEADER
1710 select SPL_DM if SPL
1711 select SPL_DM_SPI if SPL
1712 select SPL_DM_SPI_FLASH if SPL
1713 select SPL_DM_I2C if SPL
1714 select SPL_DM_MMC if SPL
1715 select SPL_DM_SERIAL if SPL
1717 Support for Kontron SMARC-sAL28 board.
1719 config TARGET_COLIBRI_PXA270
1720 bool "Support colibri_pxa270"
1722 select GPIO_EXTRA_HEADER
1724 config ARCH_UNIPHIER
1725 bool "Socionext UniPhier SoCs"
1726 select BOARD_LATE_INIT
1736 select OF_BOARD_SETUP
1740 select SPL_BOARD_INIT if SPL
1741 select SPL_DM if SPL
1742 select SPL_LIBCOMMON_SUPPORT if SPL
1743 select SPL_LIBGENERIC_SUPPORT if SPL
1744 select SPL_OF_CONTROL if SPL
1745 select SPL_PINCTRL if SPL
1748 imply DISTRO_DEFAULTS
1751 Support for UniPhier SoC family developed by Socionext Inc.
1752 (formerly, System LSI Business Division of Panasonic Corporation)
1754 config ARCH_SYNQUACER
1755 bool "Socionext SynQuacer SoCs"
1761 select SYSRESET_PSCI
1764 Support for SynQuacer SoC family developed by Socionext Inc.
1765 This SoC is used on 96boards EE DeveloperBox.
1768 bool "Support STMicroelectronics STM32 MCU with cortex M"
1772 select GPIO_EXTRA_HEADER
1776 bool "Support STMicrolectronics SoCs"
1785 Support for STMicroelectronics STiH407/10 SoC family.
1786 This SoC is used on Linaro 96Board STiH410-B2260
1789 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1790 select ARCH_MISC_INIT
1791 select ARCH_SUPPORT_TFABOOT
1792 select BOARD_LATE_INIT
1798 select GPIO_EXTRA_HEADER
1802 select OF_SYSTEM_SETUP
1808 select SYS_THUMB_BUILD
1812 imply OF_LIBFDT_OVERLAY
1813 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1816 Support for STM32MP SoC family developed by STMicroelectronics,
1817 MPUs based on ARM cortex A core
1818 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1819 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1821 SPL is the unsecure FSBL for the basic boot chain.
1823 config ARCH_ROCKCHIP
1824 bool "Support Rockchip SoCs"
1826 select BINMAN if SPL_OPTEE
1836 select DM_USB if USB
1837 select ENABLE_ARM_SOC_BOOT0_HOOK
1840 select SPL_DM if SPL
1841 select SPL_DM_SPI if SPL
1842 select SPL_DM_SPI_FLASH if SPL
1844 select SYS_THUMB_BUILD if !ARM64
1847 imply DEBUG_UART_BOARD_INIT
1848 imply DISTRO_DEFAULTS
1850 imply SARADC_ROCKCHIP
1852 imply SPL_SYS_MALLOC_SIMPLE
1855 imply USB_FUNCTION_FASTBOOT
1857 config ARCH_OCTEONTX
1858 bool "Support OcteonTX SoCs"
1861 select GPIO_EXTRA_HEADER
1865 select BOARD_LATE_INIT
1866 select SYS_CACHE_SHIFT_7
1868 config ARCH_OCTEONTX2
1869 bool "Support OcteonTX2 SoCs"
1872 select GPIO_EXTRA_HEADER
1876 select BOARD_LATE_INIT
1877 select SYS_CACHE_SHIFT_7
1879 config TARGET_THUNDERX_88XX
1880 bool "Support ThunderX 88xx"
1882 select GPIO_EXTRA_HEADER
1885 select SYS_CACHE_SHIFT_7
1888 bool "Support Aspeed SoCs"
1893 config TARGET_DURIAN
1894 bool "Support Phytium Durian Platform"
1896 select GPIO_EXTRA_HEADER
1898 Support for durian platform.
1899 It has 2GB Sdram, uart and pcie.
1901 config TARGET_PRESIDIO_ASIC
1902 bool "Support Cortina Presidio ASIC Platform"
1905 config TARGET_XENGUEST_ARM64
1906 bool "Xen guest ARM64"
1910 select LINUX_KERNEL_IMAGE_HEADER
1915 config ARCH_SUPPORT_TFABOOT
1919 bool "Support for booting from TF-A"
1920 depends on ARCH_SUPPORT_TFABOOT
1923 Some platforms support the setup of secure registers (for instance
1924 for CPU errata handling) or provide secure services like PSCI.
1925 Those services could also be provided by other firmware parts
1926 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
1927 does not need to (and cannot) execute this code.
1928 Enabling this option will make a U-Boot binary that is relying
1929 on other firmware layers to provide secure functionality.
1931 config TI_SECURE_DEVICE
1932 bool "HS Device Type Support"
1933 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1935 If a high secure (HS) device type is being used, this config
1936 must be set. This option impacts various aspects of the
1937 build system (to create signed boot images that can be
1938 authenticated) and the code. See the doc/README.ti-secure
1939 file for further details.
1941 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1942 config ISW_ENTRY_ADDR
1943 hex "Address in memory or XIP address of bootloader entry point"
1944 default 0x402F4000 if AM43XX
1945 default 0x402F0400 if AM33XX
1946 default 0x40301350 if OMAP54XX
1948 After any reset, the boot ROM searches the boot media for a valid
1949 boot image. For non-XIP devices, the ROM then copies the image into
1950 internal memory. For all boot modes, after the ROM processes the
1951 boot image it eventually computes the entry point address depending
1952 on the device type (secure/non-secure), boot media (xip/non-xip) and
1956 source "arch/arm/mach-aspeed/Kconfig"
1958 source "arch/arm/mach-at91/Kconfig"
1960 source "arch/arm/mach-bcm283x/Kconfig"
1962 source "arch/arm/mach-bcmstb/Kconfig"
1964 source "arch/arm/mach-davinci/Kconfig"
1966 source "arch/arm/mach-exynos/Kconfig"
1968 source "arch/arm/mach-highbank/Kconfig"
1970 source "arch/arm/mach-integrator/Kconfig"
1972 source "arch/arm/mach-ipq40xx/Kconfig"
1974 source "arch/arm/mach-k3/Kconfig"
1976 source "arch/arm/mach-keystone/Kconfig"
1978 source "arch/arm/mach-kirkwood/Kconfig"
1980 source "arch/arm/mach-lpc32xx/Kconfig"
1982 source "arch/arm/mach-mvebu/Kconfig"
1984 source "arch/arm/mach-octeontx/Kconfig"
1986 source "arch/arm/mach-octeontx2/Kconfig"
1988 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1990 source "arch/arm/mach-imx/mx2/Kconfig"
1992 source "arch/arm/mach-imx/mx3/Kconfig"
1994 source "arch/arm/mach-imx/mx5/Kconfig"
1996 source "arch/arm/mach-imx/mx6/Kconfig"
1998 source "arch/arm/mach-imx/mx7/Kconfig"
2000 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2002 source "arch/arm/mach-imx/imx8/Kconfig"
2004 source "arch/arm/mach-imx/imx8m/Kconfig"
2006 source "arch/arm/mach-imx/imxrt/Kconfig"
2008 source "arch/arm/mach-imx/mxs/Kconfig"
2010 source "arch/arm/mach-omap2/Kconfig"
2012 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2014 source "arch/arm/mach-orion5x/Kconfig"
2016 source "arch/arm/mach-owl/Kconfig"
2018 source "arch/arm/mach-rmobile/Kconfig"
2020 source "arch/arm/mach-meson/Kconfig"
2022 source "arch/arm/mach-mediatek/Kconfig"
2024 source "arch/arm/mach-qemu/Kconfig"
2026 source "arch/arm/mach-rockchip/Kconfig"
2028 source "arch/arm/mach-s5pc1xx/Kconfig"
2030 source "arch/arm/mach-snapdragon/Kconfig"
2032 source "arch/arm/mach-socfpga/Kconfig"
2034 source "arch/arm/mach-sti/Kconfig"
2036 source "arch/arm/mach-stm32/Kconfig"
2038 source "arch/arm/mach-stm32mp/Kconfig"
2040 source "arch/arm/mach-sunxi/Kconfig"
2042 source "arch/arm/mach-tegra/Kconfig"
2044 source "arch/arm/mach-u8500/Kconfig"
2046 source "arch/arm/mach-uniphier/Kconfig"
2048 source "arch/arm/cpu/armv7/vf610/Kconfig"
2050 source "arch/arm/mach-zynq/Kconfig"
2052 source "arch/arm/mach-zynqmp/Kconfig"
2054 source "arch/arm/mach-versal/Kconfig"
2056 source "arch/arm/mach-zynqmp-r5/Kconfig"
2058 source "arch/arm/cpu/armv7/Kconfig"
2060 source "arch/arm/cpu/armv8/Kconfig"
2062 source "arch/arm/mach-imx/Kconfig"
2064 source "arch/arm/mach-nexell/Kconfig"
2066 source "board/armltd/total_compute/Kconfig"
2068 source "board/bosch/shc/Kconfig"
2069 source "board/bosch/guardian/Kconfig"
2070 source "board/CarMediaLab/flea3/Kconfig"
2071 source "board/Marvell/aspenite/Kconfig"
2072 source "board/Marvell/octeontx/Kconfig"
2073 source "board/Marvell/octeontx2/Kconfig"
2074 source "board/armltd/vexpress64/Kconfig"
2075 source "board/cortina/presidio-asic/Kconfig"
2076 source "board/broadcom/bcm963158/Kconfig"
2077 source "board/broadcom/bcm968360bg/Kconfig"
2078 source "board/broadcom/bcm968580xref/Kconfig"
2079 source "board/broadcom/bcmns3/Kconfig"
2080 source "board/cavium/thunderx/Kconfig"
2081 source "board/eets/pdu001/Kconfig"
2082 source "board/emulation/qemu-arm/Kconfig"
2083 source "board/freescale/ls2080aqds/Kconfig"
2084 source "board/freescale/ls2080ardb/Kconfig"
2085 source "board/freescale/ls1088a/Kconfig"
2086 source "board/freescale/ls1028a/Kconfig"
2087 source "board/freescale/ls1021aqds/Kconfig"
2088 source "board/freescale/ls1043aqds/Kconfig"
2089 source "board/freescale/ls1021atwr/Kconfig"
2090 source "board/freescale/ls1021atsn/Kconfig"
2091 source "board/freescale/ls1021aiot/Kconfig"
2092 source "board/freescale/ls1046aqds/Kconfig"
2093 source "board/freescale/ls1043ardb/Kconfig"
2094 source "board/freescale/ls1046ardb/Kconfig"
2095 source "board/freescale/ls1046afrwy/Kconfig"
2096 source "board/freescale/ls1012aqds/Kconfig"
2097 source "board/freescale/ls1012ardb/Kconfig"
2098 source "board/freescale/ls1012afrdm/Kconfig"
2099 source "board/freescale/lx2160a/Kconfig"
2100 source "board/grinn/chiliboard/Kconfig"
2101 source "board/hisilicon/hikey/Kconfig"
2102 source "board/hisilicon/hikey960/Kconfig"
2103 source "board/hisilicon/poplar/Kconfig"
2104 source "board/isee/igep003x/Kconfig"
2105 source "board/kontron/sl28/Kconfig"
2106 source "board/myir/mys_6ulx/Kconfig"
2107 source "board/seeed/npi_imx6ull/Kconfig"
2108 source "board/socionext/developerbox/Kconfig"
2109 source "board/spear/spear320/Kconfig"
2110 source "board/spear/spear600/Kconfig"
2111 source "board/spear/x600/Kconfig"
2112 source "board/st/stv0991/Kconfig"
2113 source "board/tcl/sl50/Kconfig"
2114 source "board/toradex/colibri_pxa270/Kconfig"
2115 source "board/variscite/dart_6ul/Kconfig"
2116 source "board/vscom/baltos/Kconfig"
2117 source "board/phytium/durian/Kconfig"
2118 source "board/xen/xenguest_arm64/Kconfig"
2119 source "board/keymile/Kconfig"
2121 source "arch/arm/Kconfig.debug"
2126 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
2127 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
2128 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64