1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 bool "Enable support for CRC32 instruction"
17 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
18 This is faster than software crc32 calculation. This instruction may
19 not be present on all ARMv8.0, but is always present on ARMv8.1 and
22 config POSITION_INDEPENDENT
23 bool "Generate position-independent pre-relocation code"
24 depends on ARM64 || CPU_V7A
26 U-Boot expects to be linked to a specific hard-coded address, and to
27 be loaded to and run from that address. This option lifts that
28 restriction, thus allowing the code to be loaded to and executed from
29 almost any 4K aligned address. This logic relies on the relocation
30 information that is embedded in the binary to support U-Boot
31 relocating itself to the top-of-RAM later during execution.
33 config INIT_SP_RELATIVE
34 bool "Specify the early stack pointer relative to the .bss section"
36 default n if ARCH_QEMU
37 default y if POSITION_INDEPENDENT
39 U-Boot typically uses a hard-coded value for the stack pointer
40 before relocation. Enable this option to instead calculate the
41 initial SP at run-time. This is useful to avoid hard-coding addresses
42 into U-Boot, so that it can be loaded and executed at arbitrary
43 addresses and thus avoid using arbitrary addresses at runtime.
45 If this option is enabled, the early stack pointer is set to
46 &_bss_start with a offset value added. The offset is specified by
47 SYS_INIT_SP_BSS_OFFSET.
49 config SYS_INIT_SP_BSS_OFFSET
50 int "Early stack offset from the .bss base address"
52 depends on INIT_SP_RELATIVE
55 This option's value is the offset added to &_bss_start in order to
56 calculate the stack pointer. This offset should be large enough so
57 that the early malloc region, global data (gd), and early stack usage
58 do not overlap any appended DTB.
60 config LINUX_KERNEL_IMAGE_HEADER
64 Place a Linux kernel image header at the start of the U-Boot binary.
65 The format of the header is described in the Linux kernel source at
66 Documentation/arm64/booting.txt. This feature is useful since the
67 image header reports the amount of memory (BSS and similar) that
68 U-Boot needs to use, but which isn't part of the binary.
70 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
71 depends on LINUX_KERNEL_IMAGE_HEADER
74 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
75 TEXT_OFFSET value written to the Linux kernel image header.
89 ARM GICV3 Interrupt translation service (ITS).
90 Basic support for programming locality specific peripheral
91 interrupts (LPI) configuration tables and enable LPI tables.
92 LPI configuration table can be used by u-boot or Linux.
93 ARM GICV3 has limitation, once the LPI table is enabled, LPI
94 configuration table can not be re-programmed, unless GICV3 reset.
100 config DMA_ADDR_T_64BIT
110 config GPIO_EXTRA_HEADER
113 # Used for compatibility with asm files copied from the kernel
114 config ARM_ASM_UNIFIED
118 # Used for compatibility with asm files copied from the kernel
122 config SYS_ICACHE_OFF
123 bool "Do not enable icache"
125 Do not enable instruction cache in U-Boot.
127 config SPL_SYS_ICACHE_OFF
128 bool "Do not enable icache in SPL"
130 default SYS_ICACHE_OFF
132 Do not enable instruction cache in SPL.
134 config SYS_DCACHE_OFF
135 bool "Do not enable dcache"
137 Do not enable data cache in U-Boot.
139 config SPL_SYS_DCACHE_OFF
140 bool "Do not enable dcache in SPL"
142 default SYS_DCACHE_OFF
144 Do not enable data cache in SPL.
146 config SYS_ARM_CACHE_CP15
147 bool "CP15 based cache enabling support"
149 Select this if your processor suports enabling caches by using
153 bool "MMU-based Paged Memory Management Support"
154 select SYS_ARM_CACHE_CP15
156 Select if you want MMU-based virtualised addressing space
157 support via paged memory management.
160 bool 'Use the ARM v7 PMSA Compliant MPU'
162 Some ARM systems without an MMU have instead a Memory Protection
163 Unit (MPU) that defines the type and permissions for regions of
165 If your CPU has an MPU then you should choose 'y' here unless you
166 know that you do not want to use the MPU.
168 # If set, the workarounds for these ARM errata are applied early during U-Boot
169 # startup. Note that in general these options force the workarounds to be
170 # applied; no CPU-type/version detection exists, unlike the similar options in
171 # the Linux kernel. Do not set these options unless they apply! Also note that
172 # the following can be machine-specific errata. These do have ability to
173 # provide rudimentary version and machine-specific checks, but expect no
175 # CONFIG_ARM_ERRATA_430973
176 # CONFIG_ARM_ERRATA_454179
177 # CONFIG_ARM_ERRATA_621766
178 # CONFIG_ARM_ERRATA_798870
179 # CONFIG_ARM_ERRATA_801819
180 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
181 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
183 config ARM_ERRATA_430973
186 config ARM_ERRATA_454179
189 config ARM_ERRATA_621766
192 config ARM_ERRATA_716044
195 config ARM_ERRATA_725233
198 config ARM_ERRATA_742230
201 config ARM_ERRATA_743622
204 config ARM_ERRATA_751472
207 config ARM_ERRATA_761320
210 config ARM_ERRATA_773022
213 config ARM_ERRATA_774769
216 config ARM_ERRATA_794072
219 config ARM_ERRATA_798870
222 config ARM_ERRATA_801819
225 config ARM_ERRATA_826974
228 config ARM_ERRATA_828024
231 config ARM_ERRATA_829520
234 config ARM_ERRATA_833069
237 config ARM_ERRATA_833471
240 config ARM_ERRATA_845369
243 config ARM_ERRATA_852421
246 config ARM_ERRATA_852423
249 config ARM_ERRATA_855873
252 config ARM_CORTEX_A8_CVE_2017_5715
255 config ARM_CORTEX_A15_CVE_2017_5715
260 select SYS_CACHE_SHIFT_5
265 select SYS_CACHE_SHIFT_5
270 select SYS_CACHE_SHIFT_5
275 select SYS_CACHE_SHIFT_5
280 select SYS_CACHE_SHIFT_5
286 select SYS_CACHE_SHIFT_5
293 select SYS_CACHE_SHIFT_6
300 select SYS_CACHE_SHIFT_5
301 select SYS_THUMB_BUILD
307 select SYS_ARM_CACHE_CP15
309 select SYS_CACHE_SHIFT_6
313 select SYS_CACHE_SHIFT_5
318 select SYS_CACHE_SHIFT_5
322 default "arm720t" if CPU_ARM720T
323 default "arm920t" if CPU_ARM920T
324 default "arm926ejs" if CPU_ARM926EJS
325 default "arm946es" if CPU_ARM946ES
326 default "arm1136" if CPU_ARM1136
327 default "arm1176" if CPU_ARM1176
328 default "armv7" if CPU_V7A
329 default "armv7" if CPU_V7R
330 default "armv7m" if CPU_V7M
331 default "pxa" if CPU_PXA
332 default "sa1100" if CPU_SA1100
333 default "armv8" if ARM64
337 default 4 if CPU_ARM720T
338 default 4 if CPU_ARM920T
339 default 5 if CPU_ARM926EJS
340 default 5 if CPU_ARM946ES
341 default 6 if CPU_ARM1136
342 default 6 if CPU_ARM1176
347 default 4 if CPU_SA1100
351 prompt "Select the ARM data write cache policy"
352 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
354 default SYS_ARM_CACHE_WRITEBACK
356 config SYS_ARM_CACHE_WRITEBACK
357 bool "Write-back (WB)"
359 A write updates the cache only and marks the cache line as dirty.
360 External memory is updated only when the line is evicted or explicitly
363 config SYS_ARM_CACHE_WRITETHROUGH
364 bool "Write-through (WT)"
366 A write updates both the cache and the external memory system.
367 This does not mark the cache line as dirty.
369 config SYS_ARM_CACHE_WRITEALLOC
370 bool "Write allocation (WA)"
372 A cache line is allocated on a write miss. This means that executing a
373 store instruction on the processor might cause a burst read to occur.
374 There is a linefill to obtain the data for the cache line, before the
379 bool "Enable ARCH_CPU_INIT"
381 Some architectures require a call to arch_cpu_init().
382 Say Y here to enable it
384 config SYS_ARCH_TIMER
385 bool "ARM Generic Timer support"
386 depends on CPU_V7A || ARM64
389 The ARM Generic Timer (aka arch-timer) provides an architected
390 interface to a timer source on an SoC.
391 It is mandatory for ARMv8 implementation and widely available
395 bool "Support for ARM SMC Calling Convention (SMCCC)"
396 depends on CPU_V7A || ARM64
399 Say Y here if you want to enable ARM SMC Calling Convention.
400 This should be enabled if U-Boot needs to communicate with system
401 firmware (for example, PSCI) according to SMCCC.
404 bool "support boot from semihosting"
406 In emulated environments, semihosting is a way for
407 the hosted environment to call out to the emulator to
408 retrieve files from the host machine.
410 config SYS_THUMB_BUILD
411 bool "Build U-Boot using the Thumb instruction set"
414 Use this flag to build U-Boot using the Thumb instruction set for
415 ARM architectures. Thumb instruction set provides better code
416 density. For ARM architectures that support Thumb2 this flag will
417 result in Thumb2 code generated by GCC.
419 config SPL_SYS_THUMB_BUILD
420 bool "Build SPL using the Thumb instruction set"
421 default y if SYS_THUMB_BUILD
422 depends on !ARM64 && SPL
424 Use this flag to build SPL using the Thumb instruction set for
425 ARM architectures. Thumb instruction set provides better code
426 density. For ARM architectures that support Thumb2 this flag will
427 result in Thumb2 code generated by GCC.
429 config TPL_SYS_THUMB_BUILD
430 bool "Build TPL using the Thumb instruction set"
431 default y if SYS_THUMB_BUILD
432 depends on TPL && !ARM64
434 Use this flag to build TPL using the Thumb instruction set for
435 ARM architectures. Thumb instruction set provides better code
436 density. For ARM architectures that support Thumb2 this flag will
437 result in Thumb2 code generated by GCC.
440 config SYS_L2CACHE_OFF
443 If SoC does not support L2CACHE or one does not want to enable
444 L2CACHE, choose this option.
446 config ENABLE_ARM_SOC_BOOT0_HOOK
447 bool "prepare BOOT0 header"
449 If the SoC's BOOT0 requires a header area filled with (magic)
450 values, then choose this option, and create a file included as
451 <asm/arch/boot0.h> which contains the required assembler code.
453 config ARM_CORTEX_CPU_IS_UP
456 config USE_ARCH_MEMCPY
457 bool "Use an assembly optimized implementation of memcpy"
459 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
461 Enable the generation of an optimized version of memcpy.
462 Such an implementation may be faster under some conditions
463 but may increase the binary size.
465 config SPL_USE_ARCH_MEMCPY
466 bool "Use an assembly optimized implementation of memcpy for SPL"
467 default y if USE_ARCH_MEMCPY
470 Enable the generation of an optimized version of memcpy.
471 Such an implementation may be faster under some conditions
472 but may increase the binary size.
474 config TPL_USE_ARCH_MEMCPY
475 bool "Use an assembly optimized implementation of memcpy for TPL"
476 default y if USE_ARCH_MEMCPY
479 Enable the generation of an optimized version of memcpy.
480 Such an implementation may be faster under some conditions
481 but may increase the binary size.
483 config USE_ARCH_MEMMOVE
484 bool "Use an assembly optimized implementation of memmove" if !ARM64
485 default USE_ARCH_MEMCPY if ARM64
488 Enable the generation of an optimized version of memmove.
489 Such an implementation may be faster under some conditions
490 but may increase the binary size.
492 config SPL_USE_ARCH_MEMMOVE
493 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
494 default SPL_USE_ARCH_MEMCPY if ARM64
495 depends on SPL && ARM64
497 Enable the generation of an optimized version of memmove.
498 Such an implementation may be faster under some conditions
499 but may increase the binary size.
501 config TPL_USE_ARCH_MEMMOVE
502 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
503 default TPL_USE_ARCH_MEMCPY if ARM64
504 depends on TPL && ARM64
506 Enable the generation of an optimized version of memmove.
507 Such an implementation may be faster under some conditions
508 but may increase the binary size.
510 config USE_ARCH_MEMSET
511 bool "Use an assembly optimized implementation of memset"
513 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
515 Enable the generation of an optimized version of memset.
516 Such an implementation may be faster under some conditions
517 but may increase the binary size.
519 config SPL_USE_ARCH_MEMSET
520 bool "Use an assembly optimized implementation of memset for SPL"
521 default y if USE_ARCH_MEMSET
524 Enable the generation of an optimized version of memset.
525 Such an implementation may be faster under some conditions
526 but may increase the binary size.
528 config TPL_USE_ARCH_MEMSET
529 bool "Use an assembly optimized implementation of memset for TPL"
530 default y if USE_ARCH_MEMSET
533 Enable the generation of an optimized version of memset.
534 Such an implementation may be faster under some conditions
535 but may increase the binary size.
537 config ARM64_SUPPORT_AARCH32
538 bool "ARM64 system support AArch32 execution state"
540 default y if !TARGET_THUNDERX_88XX
542 This ARM64 system supports AArch32 execution state.
545 prompt "Target select"
550 select GPIO_EXTRA_HEADER
551 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
552 select SPL_SEPARATE_BSS if SPL
554 config TARGET_ASPENITE
555 bool "Support aspenite"
557 select GPIO_EXTRA_HEADER
562 select GPIO_EXTRA_HEADER
563 select SPL_DM_SPI if SPL
566 Support for TI's DaVinci platform.
569 bool "Marvell Kirkwood"
570 select ARCH_MISC_INIT
571 select BOARD_EARLY_INIT_F
573 select GPIO_EXTRA_HEADER
576 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
582 select GPIO_EXTRA_HEADER
583 select SPL_DM_SPI if SPL
584 select SPL_DM_SPI_FLASH if SPL
593 select GPIO_EXTRA_HEADER
595 config TARGET_STV0991
596 bool "Support stv0991"
602 select GPIO_EXTRA_HEADER
611 select GPIO_EXTRA_HEADER
614 bool "Broadcom BCM283X family"
618 select GPIO_EXTRA_HEADER
621 select SERIAL_SEARCH_ALL
626 bool "Broadcom BCM63158 family"
632 bool "Broadcom BCM68360 family"
638 bool "Broadcom BCM6858 family"
644 bool "Broadcom BCM7XXX family"
647 select GPIO_EXTRA_HEADER
649 select OF_PRIOR_STAGE
652 This enables support for Broadcom ARM-based set-top box
653 chipsets, including the 7445 family of chips.
655 config TARGET_VEXPRESS_CA9X4
656 bool "Support vexpress_ca9x4"
660 config TARGET_BCMCYGNUS
661 bool "Support bcmcygnus"
663 select GPIO_EXTRA_HEADER
665 imply BCM_SF2_ETH_GMAC
673 bool "Support Broadcom Northstar2"
675 select GPIO_EXTRA_HEADER
677 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
678 ARMv8 Cortex-A57 processors targeting a broad range of networking
682 bool "Support Broadcom NS3"
684 select BOARD_LATE_INIT
686 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
687 ARMv8 Cortex-A72 processors targeting a broad range of networking
691 bool "Samsung EXYNOS"
701 select GPIO_EXTRA_HEADER
702 imply SYS_THUMB_BUILD
707 bool "Samsung S5PC1XX"
713 select GPIO_EXTRA_HEADER
717 bool "Calxeda Highbank"
730 config ARCH_INTEGRATOR
731 bool "ARM Ltd. Integrator family"
734 select GPIO_EXTRA_HEADER
739 bool "Qualcomm IPQ40xx SoCs"
745 select GPIO_EXTRA_HEADER
758 select GPIO_EXTRA_HEADER
760 select SYS_ARCH_TIMER
761 select SYS_THUMB_BUILD
767 bool "Texas Instruments' K3 Architecture"
772 config ARCH_OMAP2PLUS
775 select GPIO_EXTRA_HEADER
776 select SPL_BOARD_INIT if SPL
777 select SPL_STACK_R if SPL
779 imply TI_SYSC if DM && OF_CONTROL
784 select GPIO_EXTRA_HEADER
785 imply DISTRO_DEFAULTS
788 Support for the Meson SoC family developed by Amlogic Inc.,
789 targeted at media players and tablet computers. We currently
790 support the S905 (GXBaby) 64-bit SoC.
795 select GPIO_EXTRA_HEADER
798 select SPL_LIBCOMMON_SUPPORT if SPL
799 select SPL_LIBGENERIC_SUPPORT if SPL
800 select SPL_OF_CONTROL if SPL
803 Support for the MediaTek SoCs family developed by MediaTek Inc.
804 Please refer to doc/README.mediatek for more information.
807 bool "NXP LPC32xx platform"
812 select GPIO_EXTRA_HEADER
818 bool "NXP i.MX8 platform"
821 select GPIO_EXTRA_HEADER
824 select ENABLE_ARM_SOC_BOOT0_HOOK
827 bool "NXP i.MX8M platform"
829 select GPIO_EXTRA_HEADER
831 select SYS_FSL_HAS_SEC if IMX_HAB
832 select SYS_FSL_SEC_COMPAT_4
833 select SYS_FSL_SEC_LE
840 bool "NXP i.MX8ULP platform"
846 select GPIO_EXTRA_HEADER
850 bool "NXP i.MXRT platform"
854 select GPIO_EXTRA_HEADER
860 bool "NXP i.MX23 family"
862 select GPIO_EXTRA_HEADER
870 select GPIO_EXTRA_HEADER
875 bool "NXP i.MX28 family"
877 select GPIO_EXTRA_HEADER
883 bool "NXP i.MX31 family"
885 select GPIO_EXTRA_HEADER
891 select GPIO_EXTRA_HEADER
893 select SYS_FSL_HAS_SEC if IMX_HAB
894 select SYS_FSL_SEC_COMPAT_4
895 select SYS_FSL_SEC_LE
896 select ROM_UNIFIED_SECTIONS
898 imply SYS_THUMB_BUILD
902 select ARCH_MISC_INIT
904 select GPIO_EXTRA_HEADER
906 select SYS_FSL_HAS_SEC if IMX_HAB
907 select SYS_FSL_SEC_COMPAT_4
908 select SYS_FSL_SEC_LE
909 imply BOARD_EARLY_INIT_F
911 imply SYS_THUMB_BUILD
916 select GPIO_EXTRA_HEADER
918 select SYS_FSL_HAS_SEC
919 select SYS_FSL_SEC_COMPAT_4
920 select SYS_FSL_SEC_LE
922 imply SYS_THUMB_BUILD
926 default "arch/arm/mach-omap2/u-boot-spl.lds"
931 select BOARD_EARLY_INIT_F
933 select GPIO_EXTRA_HEADER
938 bool "Nexell S5P4418/S5P6818 SoC"
939 select ENABLE_ARM_SOC_BOOT0_HOOK
941 select GPIO_EXTRA_HEADER
944 bool "Actions Semi OWL SoCs"
948 select GPIO_EXTRA_HEADER
953 select SYS_RELOC_GD_ENV_ADDR
957 bool "QEMU Virtual Platform"
968 bool "Renesas ARM SoCs"
971 select GPIO_EXTRA_HEADER
972 imply BOARD_EARLY_INIT_F
975 imply SYS_THUMB_BUILD
976 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
978 config ARCH_SNAPDRAGON
979 bool "Qualcomm Snapdragon SoCs"
984 select GPIO_EXTRA_HEADER
993 bool "Altera SOCFPGA family"
994 select ARCH_EARLY_INIT_R
995 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
996 select ARM64 if TARGET_SOCFPGA_SOC64
997 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1001 select GPIO_EXTRA_HEADER
1002 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1004 select SPL_DM_RESET if DM_RESET
1005 select SPL_DM_SERIAL
1006 select SPL_LIBCOMMON_SUPPORT
1007 select SPL_LIBGENERIC_SUPPORT
1008 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
1009 select SPL_OF_CONTROL
1010 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1016 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1018 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1019 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1029 imply SPL_DM_SPI_FLASH
1030 imply SPL_LIBDISK_SUPPORT
1032 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1033 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1034 imply SPL_SPI_FLASH_SUPPORT
1039 bool "Support sunxi (Allwinner) SoCs"
1042 select CMD_MMC if MMC
1043 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1049 select DM_MMC if MMC
1050 select DM_SCSI if SCSI
1052 select GPIO_EXTRA_HEADER
1053 select OF_BOARD_SETUP
1056 select SPECIFY_CONSOLE_INDEX
1057 select SPL_STACK_R if SPL
1058 select SPL_SYS_MALLOC_SIMPLE if SPL
1059 select SPL_SYS_THUMB_BUILD if !ARM64
1062 select SYS_THUMB_BUILD if !ARM64
1063 select USB if DISTRO_DEFAULTS
1064 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1065 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1066 select SPL_USE_TINY_PRINTF
1068 select SYS_RELOC_GD_ENV_ADDR
1069 imply BOARD_LATE_INIT
1072 imply CMD_UBI if MTD_RAW_NAND
1073 imply DISTRO_DEFAULTS
1076 imply OF_LIBFDT_OVERLAY
1077 imply PRE_CONSOLE_BUFFER
1079 imply SPL_LIBCOMMON_SUPPORT
1080 imply SPL_LIBGENERIC_SUPPORT
1081 imply SPL_MMC if MMC
1087 bool "ST-Ericsson U8500 Series"
1091 select DM_MMC if MMC
1093 select DM_USB_GADGET if DM_USB
1097 imply AB8500_USB_PHY
1098 imply ARM_PL180_MMCI
1103 imply NOMADIK_MTU_TIMER
1108 imply SYS_THUMB_BUILD
1109 imply SYSRESET_SYSCON
1112 bool "Support Xilinx Versal Platform"
1116 select DM_ETH if NET
1117 select DM_MMC if MMC
1120 select GPIO_EXTRA_HEADER
1123 imply BOARD_LATE_INIT
1124 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1127 bool "Freescale Vybrid"
1129 select GPIO_EXTRA_HEADER
1131 select SYS_FSL_ERRATUM_ESDHC111
1136 bool "Xilinx Zynq based platform"
1141 select DM_ETH if NET
1142 select DM_MMC if MMC
1146 select GPIO_EXTRA_HEADER
1149 select SPL_BOARD_INIT if SPL
1150 select SPL_CLK if SPL
1151 select SPL_DM if SPL
1152 select SPL_DM_SPI if SPL
1153 select SPL_DM_SPI_FLASH if SPL
1154 select SPL_OF_CONTROL if SPL
1155 select SPL_SEPARATE_BSS if SPL
1157 imply ARCH_EARLY_INIT_R
1158 imply BOARD_LATE_INIT
1162 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1165 config ARCH_ZYNQMP_R5
1166 bool "Xilinx ZynqMP R5 based platform"
1170 select DM_ETH if NET
1171 select DM_MMC if MMC
1173 select GPIO_EXTRA_HEADER
1179 bool "Xilinx ZynqMP based platform"
1183 select DM_ETH if NET
1185 select DM_MMC if MMC
1187 select DM_SPI if SPI
1188 select DM_SPI_FLASH if DM_SPI
1191 select GPIO_EXTRA_HEADER
1193 select SPL_BOARD_INIT if SPL
1194 select SPL_CLK if SPL
1195 select SPL_DM if SPL
1196 select SPL_DM_SPI if SPI && SPL_DM
1197 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1198 select SPL_DM_MAILBOX if SPL
1199 select SPL_FIRMWARE if SPL
1200 select SPL_SEPARATE_BSS if SPL
1204 imply BOARD_LATE_INIT
1206 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1213 select GPIO_EXTRA_HEADER
1214 imply DISTRO_DEFAULTS
1217 config TARGET_VEXPRESS64_AEMV8A
1218 bool "Support vexpress_aemv8a"
1220 select GPIO_EXTRA_HEADER
1223 config TARGET_VEXPRESS64_BASE_FVP
1224 bool "Support Versatile Express ARMv8a FVP BASE model"
1226 select GPIO_EXTRA_HEADER
1230 config TARGET_VEXPRESS64_JUNO
1231 bool "Support Versatile Express Juno Development Platform"
1233 select GPIO_EXTRA_HEADER
1246 config TARGET_TOTAL_COMPUTE
1247 bool "Support Total Compute Platform"
1255 config TARGET_LS2080A_EMU
1256 bool "Support ls2080a_emu"
1259 select ARMV8_MULTIENTRY
1260 select FSL_DDR_SYNC_REFRESH
1261 select GPIO_EXTRA_HEADER
1263 Support for Freescale LS2080A_EMU platform.
1264 The LS2080A Development System (EMULATOR) is a pre-silicon
1265 development platform that supports the QorIQ LS2080A
1266 Layerscape Architecture processor.
1268 config TARGET_LS1088AQDS
1269 bool "Support ls1088aqds"
1272 select ARMV8_MULTIENTRY
1273 select ARCH_SUPPORT_TFABOOT
1274 select BOARD_LATE_INIT
1275 select GPIO_EXTRA_HEADER
1277 select FSL_DDR_INTERACTIVE if !SD_BOOT
1279 Support for NXP LS1088AQDS platform.
1280 The LS1088A Development System (QDS) is a high-performance
1281 development platform that supports the QorIQ LS1088A
1282 Layerscape Architecture processor.
1284 config TARGET_LS2080AQDS
1285 bool "Support ls2080aqds"
1288 select ARMV8_MULTIENTRY
1289 select ARCH_SUPPORT_TFABOOT
1290 select BOARD_LATE_INIT
1291 select GPIO_EXTRA_HEADER
1296 select FSL_DDR_INTERACTIVE if !SPL
1298 Support for Freescale LS2080AQDS platform.
1299 The LS2080A Development System (QDS) is a high-performance
1300 development platform that supports the QorIQ LS2080A
1301 Layerscape Architecture processor.
1303 config TARGET_LS2080ARDB
1304 bool "Support ls2080ardb"
1307 select ARMV8_MULTIENTRY
1308 select ARCH_SUPPORT_TFABOOT
1309 select BOARD_LATE_INIT
1312 select FSL_DDR_INTERACTIVE if !SPL
1313 select GPIO_EXTRA_HEADER
1317 Support for Freescale LS2080ARDB platform.
1318 The LS2080A Reference design board (RDB) is a high-performance
1319 development platform that supports the QorIQ LS2080A
1320 Layerscape Architecture processor.
1322 config TARGET_LS2081ARDB
1323 bool "Support ls2081ardb"
1326 select ARMV8_MULTIENTRY
1327 select BOARD_LATE_INIT
1328 select GPIO_EXTRA_HEADER
1331 Support for Freescale LS2081ARDB platform.
1332 The LS2081A Reference design board (RDB) is a high-performance
1333 development platform that supports the QorIQ LS2081A/LS2041A
1334 Layerscape Architecture processor.
1336 config TARGET_LX2160ARDB
1337 bool "Support lx2160ardb"
1340 select ARMV8_MULTIENTRY
1341 select ARCH_SUPPORT_TFABOOT
1342 select BOARD_LATE_INIT
1343 select GPIO_EXTRA_HEADER
1345 Support for NXP LX2160ARDB platform.
1346 The lx2160ardb (LX2160A Reference design board (RDB)
1347 is a high-performance development platform that supports the
1348 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1350 config TARGET_LX2160AQDS
1351 bool "Support lx2160aqds"
1354 select ARMV8_MULTIENTRY
1355 select ARCH_SUPPORT_TFABOOT
1356 select BOARD_LATE_INIT
1357 select GPIO_EXTRA_HEADER
1359 Support for NXP LX2160AQDS platform.
1360 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1361 is a high-performance development platform that supports the
1362 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1364 config TARGET_LX2162AQDS
1365 bool "Support lx2162aqds"
1367 select ARCH_MISC_INIT
1369 select ARMV8_MULTIENTRY
1370 select ARCH_SUPPORT_TFABOOT
1371 select BOARD_LATE_INIT
1372 select GPIO_EXTRA_HEADER
1374 Support for NXP LX2162AQDS platform.
1375 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1378 bool "Support HiKey 96boards Consumer Edition Platform"
1383 select GPIO_EXTRA_HEADER
1386 select SPECIFY_CONSOLE_INDEX
1389 Support for HiKey 96boards platform. It features a HI6220
1390 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1392 config TARGET_HIKEY960
1393 bool "Support HiKey960 96boards Consumer Edition Platform"
1397 select GPIO_EXTRA_HEADER
1402 Support for HiKey960 96boards platform. It features a HI3660
1403 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1405 config TARGET_POPLAR
1406 bool "Support Poplar 96boards Enterprise Edition Platform"
1410 select GPIO_EXTRA_HEADER
1415 Support for Poplar 96boards EE platform. It features a HI3798cv200
1416 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1417 making it capable of running any commercial set-top solution based on
1420 config TARGET_LS1012AQDS
1421 bool "Support ls1012aqds"
1424 select ARCH_SUPPORT_TFABOOT
1425 select BOARD_LATE_INIT
1426 select GPIO_EXTRA_HEADER
1428 Support for Freescale LS1012AQDS platform.
1429 The LS1012A Development System (QDS) is a high-performance
1430 development platform that supports the QorIQ LS1012A
1431 Layerscape Architecture processor.
1433 config TARGET_LS1012ARDB
1434 bool "Support ls1012ardb"
1437 select ARCH_SUPPORT_TFABOOT
1438 select BOARD_LATE_INIT
1439 select GPIO_EXTRA_HEADER
1443 Support for Freescale LS1012ARDB platform.
1444 The LS1012A Reference design board (RDB) is a high-performance
1445 development platform that supports the QorIQ LS1012A
1446 Layerscape Architecture processor.
1448 config TARGET_LS1012A2G5RDB
1449 bool "Support ls1012a2g5rdb"
1452 select ARCH_SUPPORT_TFABOOT
1453 select BOARD_LATE_INIT
1454 select GPIO_EXTRA_HEADER
1457 Support for Freescale LS1012A2G5RDB platform.
1458 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1459 development platform that supports the QorIQ LS1012A
1460 Layerscape Architecture processor.
1462 config TARGET_LS1012AFRWY
1463 bool "Support ls1012afrwy"
1466 select ARCH_SUPPORT_TFABOOT
1467 select BOARD_LATE_INIT
1468 select GPIO_EXTRA_HEADER
1472 Support for Freescale LS1012AFRWY platform.
1473 The LS1012A FRWY board (FRWY) is a high-performance
1474 development platform that supports the QorIQ LS1012A
1475 Layerscape Architecture processor.
1477 config TARGET_LS1012AFRDM
1478 bool "Support ls1012afrdm"
1481 select ARCH_SUPPORT_TFABOOT
1482 select GPIO_EXTRA_HEADER
1484 Support for Freescale LS1012AFRDM platform.
1485 The LS1012A Freedom board (FRDM) is a high-performance
1486 development platform that supports the QorIQ LS1012A
1487 Layerscape Architecture processor.
1489 config TARGET_LS1028AQDS
1490 bool "Support ls1028aqds"
1493 select ARMV8_MULTIENTRY
1494 select ARCH_SUPPORT_TFABOOT
1495 select BOARD_LATE_INIT
1496 select GPIO_EXTRA_HEADER
1498 Support for Freescale LS1028AQDS platform
1499 The LS1028A Development System (QDS) is a high-performance
1500 development platform that supports the QorIQ LS1028A
1501 Layerscape Architecture processor.
1503 config TARGET_LS1028ARDB
1504 bool "Support ls1028ardb"
1507 select ARMV8_MULTIENTRY
1508 select ARCH_SUPPORT_TFABOOT
1509 select BOARD_LATE_INIT
1510 select GPIO_EXTRA_HEADER
1512 Support for Freescale LS1028ARDB platform
1513 The LS1028A Development System (RDB) is a high-performance
1514 development platform that supports the QorIQ LS1028A
1515 Layerscape Architecture processor.
1517 config TARGET_LS1088ARDB
1518 bool "Support ls1088ardb"
1521 select ARMV8_MULTIENTRY
1522 select ARCH_SUPPORT_TFABOOT
1523 select BOARD_LATE_INIT
1525 select FSL_DDR_INTERACTIVE if !SD_BOOT
1526 select GPIO_EXTRA_HEADER
1528 Support for NXP LS1088ARDB platform.
1529 The LS1088A Reference design board (RDB) is a high-performance
1530 development platform that supports the QorIQ LS1088A
1531 Layerscape Architecture processor.
1533 config TARGET_LS1021AQDS
1534 bool "Support ls1021aqds"
1536 select ARCH_SUPPORT_PSCI
1537 select BOARD_EARLY_INIT_F
1538 select BOARD_LATE_INIT
1540 select CPU_V7_HAS_NONSEC
1541 select CPU_V7_HAS_VIRT
1542 select LS1_DEEP_SLEEP
1545 select FSL_DDR_INTERACTIVE
1546 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1547 select GPIO_EXTRA_HEADER
1548 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1551 config TARGET_LS1021ATWR
1552 bool "Support ls1021atwr"
1554 select ARCH_SUPPORT_PSCI
1555 select BOARD_EARLY_INIT_F
1556 select BOARD_LATE_INIT
1558 select CPU_V7_HAS_NONSEC
1559 select CPU_V7_HAS_VIRT
1560 select LS1_DEEP_SLEEP
1562 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1563 select GPIO_EXTRA_HEADER
1566 config TARGET_PG_WCOM_SELI8
1567 bool "Support Hitachi-Powergrids SELI8 service unit card"
1569 select ARCH_SUPPORT_PSCI
1570 select BOARD_EARLY_INIT_F
1571 select BOARD_LATE_INIT
1573 select CPU_V7_HAS_NONSEC
1574 select CPU_V7_HAS_VIRT
1576 select FSL_DDR_INTERACTIVE
1577 select GPIO_EXTRA_HEADER
1581 Support for Hitachi-Powergrids SELI8 service unit card.
1582 SELI8 is a QorIQ LS1021a based service unit card used
1583 in XMC20 and FOX615 product families.
1585 config TARGET_PG_WCOM_EXPU1
1586 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1588 select ARCH_SUPPORT_PSCI
1589 select BOARD_EARLY_INIT_F
1590 select BOARD_LATE_INIT
1592 select CPU_V7_HAS_NONSEC
1593 select CPU_V7_HAS_VIRT
1595 select FSL_DDR_INTERACTIVE
1599 Support for Hitachi-Powergrids EXPU1 service unit card.
1600 EXPU1 is a QorIQ LS1021a based service unit card used
1601 in XMC20 and FOX615 product families.
1603 config TARGET_LS1021ATSN
1604 bool "Support ls1021atsn"
1606 select ARCH_SUPPORT_PSCI
1607 select BOARD_EARLY_INIT_F
1608 select BOARD_LATE_INIT
1610 select CPU_V7_HAS_NONSEC
1611 select CPU_V7_HAS_VIRT
1612 select LS1_DEEP_SLEEP
1614 select GPIO_EXTRA_HEADER
1617 config TARGET_LS1021AIOT
1618 bool "Support ls1021aiot"
1620 select ARCH_SUPPORT_PSCI
1621 select BOARD_LATE_INIT
1623 select CPU_V7_HAS_NONSEC
1624 select CPU_V7_HAS_VIRT
1626 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1627 select GPIO_EXTRA_HEADER
1630 Support for Freescale LS1021AIOT platform.
1631 The LS1021A Freescale board (IOT) is a high-performance
1632 development platform that supports the QorIQ LS1021A
1633 Layerscape Architecture processor.
1635 config TARGET_LS1043AQDS
1636 bool "Support ls1043aqds"
1639 select ARMV8_MULTIENTRY
1640 select ARCH_SUPPORT_TFABOOT
1641 select BOARD_EARLY_INIT_F
1642 select BOARD_LATE_INIT
1644 select FSL_DDR_INTERACTIVE if !SPL
1645 select FSL_DSPI if !SPL_NO_DSPI
1646 select DM_SPI_FLASH if FSL_DSPI
1647 select GPIO_EXTRA_HEADER
1651 Support for Freescale LS1043AQDS platform.
1653 config TARGET_LS1043ARDB
1654 bool "Support ls1043ardb"
1657 select ARMV8_MULTIENTRY
1658 select ARCH_SUPPORT_TFABOOT
1659 select BOARD_EARLY_INIT_F
1660 select BOARD_LATE_INIT
1662 select FSL_DSPI if !SPL_NO_DSPI
1663 select DM_SPI_FLASH if FSL_DSPI
1664 select GPIO_EXTRA_HEADER
1666 Support for Freescale LS1043ARDB platform.
1668 config TARGET_LS1046AQDS
1669 bool "Support ls1046aqds"
1672 select ARMV8_MULTIENTRY
1673 select ARCH_SUPPORT_TFABOOT
1674 select BOARD_EARLY_INIT_F
1675 select BOARD_LATE_INIT
1676 select DM_SPI_FLASH if DM_SPI
1678 select FSL_DDR_BIST if !SPL
1679 select FSL_DDR_INTERACTIVE if !SPL
1680 select FSL_DDR_INTERACTIVE if !SPL
1681 select GPIO_EXTRA_HEADER
1684 Support for Freescale LS1046AQDS platform.
1685 The LS1046A Development System (QDS) is a high-performance
1686 development platform that supports the QorIQ LS1046A
1687 Layerscape Architecture processor.
1689 config TARGET_LS1046ARDB
1690 bool "Support ls1046ardb"
1693 select ARMV8_MULTIENTRY
1694 select ARCH_SUPPORT_TFABOOT
1695 select BOARD_EARLY_INIT_F
1696 select BOARD_LATE_INIT
1697 select DM_SPI_FLASH if DM_SPI
1698 select POWER_MC34VR500
1701 select FSL_DDR_INTERACTIVE if !SPL
1702 select GPIO_EXTRA_HEADER
1705 Support for Freescale LS1046ARDB platform.
1706 The LS1046A Reference Design Board (RDB) is a high-performance
1707 development platform that supports the QorIQ LS1046A
1708 Layerscape Architecture processor.
1710 config TARGET_LS1046AFRWY
1711 bool "Support ls1046afrwy"
1714 select ARMV8_MULTIENTRY
1715 select ARCH_SUPPORT_TFABOOT
1716 select BOARD_EARLY_INIT_F
1717 select BOARD_LATE_INIT
1718 select DM_SPI_FLASH if DM_SPI
1719 select GPIO_EXTRA_HEADER
1722 Support for Freescale LS1046AFRWY platform.
1723 The LS1046A Freeway Board (FRWY) is a high-performance
1724 development platform that supports the QorIQ LS1046A
1725 Layerscape Architecture processor.
1731 select ARMV8_MULTIENTRY
1747 select GPIO_EXTRA_HEADER
1748 select SPL_DM if SPL
1749 select SPL_DM_SPI if SPL
1750 select SPL_DM_SPI_FLASH if SPL
1751 select SPL_DM_I2C if SPL
1752 select SPL_DM_MMC if SPL
1753 select SPL_DM_SERIAL if SPL
1755 Support for Kontron SMARC-sAL28 board.
1757 config TARGET_COLIBRI_PXA270
1758 bool "Support colibri_pxa270"
1760 select GPIO_EXTRA_HEADER
1762 config ARCH_UNIPHIER
1763 bool "Socionext UniPhier SoCs"
1764 select BOARD_LATE_INIT
1773 select OF_BOARD_SETUP
1777 select SPL_BOARD_INIT if SPL
1778 select SPL_DM if SPL
1779 select SPL_LIBCOMMON_SUPPORT if SPL
1780 select SPL_LIBGENERIC_SUPPORT if SPL
1781 select SPL_OF_CONTROL if SPL
1782 select SPL_PINCTRL if SPL
1785 imply DISTRO_DEFAULTS
1788 Support for UniPhier SoC family developed by Socionext Inc.
1789 (formerly, System LSI Business Division of Panasonic Corporation)
1791 config ARCH_SYNQUACER
1792 bool "Socionext SynQuacer SoCs"
1798 select SYSRESET_PSCI
1801 Support for SynQuacer SoC family developed by Socionext Inc.
1802 This SoC is used on 96boards EE DeveloperBox.
1805 bool "Support STMicroelectronics STM32 MCU with cortex M"
1809 select GPIO_EXTRA_HEADER
1813 bool "Support STMicrolectronics SoCs"
1822 Support for STMicroelectronics STiH407/10 SoC family.
1823 This SoC is used on Linaro 96Board STiH410-B2260
1826 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1827 select ARCH_MISC_INIT
1828 select ARCH_SUPPORT_TFABOOT
1829 select BOARD_LATE_INIT
1835 select GPIO_EXTRA_HEADER
1839 select OF_SYSTEM_SETUP
1845 select SYS_THUMB_BUILD
1849 imply OF_LIBFDT_OVERLAY
1850 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1853 Support for STM32MP SoC family developed by STMicroelectronics,
1854 MPUs based on ARM cortex A core
1855 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1856 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1858 SPL is the unsecure FSBL for the basic boot chain.
1860 config ARCH_ROCKCHIP
1861 bool "Support Rockchip SoCs"
1863 select BINMAN if SPL_OPTEE || (SPL && !ARM64)
1873 select ENABLE_ARM_SOC_BOOT0_HOOK
1876 select SPL_DM if SPL
1877 select SPL_DM_SPI if SPL
1878 select SPL_DM_SPI_FLASH if SPL
1880 select SYS_THUMB_BUILD if !ARM64
1883 imply DEBUG_UART_BOARD_INIT
1884 imply DISTRO_DEFAULTS
1886 imply SARADC_ROCKCHIP
1888 imply SPL_SYS_MALLOC_SIMPLE
1891 imply USB_FUNCTION_FASTBOOT
1893 config ARCH_OCTEONTX
1894 bool "Support OcteonTX SoCs"
1897 select GPIO_EXTRA_HEADER
1901 select BOARD_LATE_INIT
1902 select SYS_CACHE_SHIFT_7
1904 config ARCH_OCTEONTX2
1905 bool "Support OcteonTX2 SoCs"
1908 select GPIO_EXTRA_HEADER
1912 select BOARD_LATE_INIT
1913 select SYS_CACHE_SHIFT_7
1915 config TARGET_THUNDERX_88XX
1916 bool "Support ThunderX 88xx"
1918 select GPIO_EXTRA_HEADER
1921 select SYS_CACHE_SHIFT_7
1924 bool "Support Aspeed SoCs"
1929 config TARGET_DURIAN
1930 bool "Support Phytium Durian Platform"
1932 select GPIO_EXTRA_HEADER
1934 Support for durian platform.
1935 It has 2GB Sdram, uart and pcie.
1937 config TARGET_PRESIDIO_ASIC
1938 bool "Support Cortina Presidio ASIC Platform"
1942 config TARGET_XENGUEST_ARM64
1943 bool "Xen guest ARM64"
1947 select LINUX_KERNEL_IMAGE_HEADER
1952 config SUPPORT_PASSING_ATAGS
1953 bool "Support pre-devicetree ATAG-based booting"
1955 imply SETUP_MEMORY_TAGS
1957 Support for booting older Linux kernels, using ATAGs rather than
1958 passing a devicetree. This is option is rarely used, and the
1959 semantics are defined at
1960 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
1962 config SETUP_MEMORY_TAGS
1963 bool "Pass memory size information via ATAG"
1964 depends on SUPPORT_PASSING_ATAGS
1967 bool "Pass Linux kernel cmdline via ATAG"
1968 depends on SUPPORT_PASSING_ATAGS
1971 bool "Pass initrd starting point and size via ATAG"
1972 depends on SUPPORT_PASSING_ATAGS
1975 bool "Pass system revision via ATAG"
1976 depends on SUPPORT_PASSING_ATAGS
1979 bool "Pass system serial number via ATAG"
1980 depends on SUPPORT_PASSING_ATAGS
1982 config STATIC_MACH_TYPE
1983 bool "Statically define the Machine ID number"
1985 When booting via ATAGs, enable this option if we know the correct
1986 machine ID number to use at compile time. Some systems will be
1987 passed the number dynamically by whatever loads U-Boot.
1990 int "Machine ID number"
1991 depends on STATIC_MACH_TYPE
1993 When booting via ATAGs, the machine type must be passed as a number.
1994 For the full list see https://www.arm.linux.org.uk/developer/machines
1996 config ARCH_SUPPORT_TFABOOT
2000 bool "Support for booting from TF-A"
2001 depends on ARCH_SUPPORT_TFABOOT
2003 Some platforms support the setup of secure registers (for instance
2004 for CPU errata handling) or provide secure services like PSCI.
2005 Those services could also be provided by other firmware parts
2006 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2007 does not need to (and cannot) execute this code.
2008 Enabling this option will make a U-Boot binary that is relying
2009 on other firmware layers to provide secure functionality.
2011 config TI_SECURE_DEVICE
2012 bool "HS Device Type Support"
2013 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2015 If a high secure (HS) device type is being used, this config
2016 must be set. This option impacts various aspects of the
2017 build system (to create signed boot images that can be
2018 authenticated) and the code. See the doc/README.ti-secure
2019 file for further details.
2021 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
2022 config ISW_ENTRY_ADDR
2023 hex "Address in memory or XIP address of bootloader entry point"
2024 default 0x402F4000 if AM43XX
2025 default 0x402F0400 if AM33XX
2026 default 0x40301350 if OMAP54XX
2028 After any reset, the boot ROM searches the boot media for a valid
2029 boot image. For non-XIP devices, the ROM then copies the image into
2030 internal memory. For all boot modes, after the ROM processes the
2031 boot image it eventually computes the entry point address depending
2032 on the device type (secure/non-secure), boot media (xip/non-xip) and
2036 source "arch/arm/mach-aspeed/Kconfig"
2038 source "arch/arm/mach-at91/Kconfig"
2040 source "arch/arm/mach-bcm283x/Kconfig"
2042 source "arch/arm/mach-bcmstb/Kconfig"
2044 source "arch/arm/mach-davinci/Kconfig"
2046 source "arch/arm/mach-exynos/Kconfig"
2048 source "arch/arm/mach-highbank/Kconfig"
2050 source "arch/arm/mach-integrator/Kconfig"
2052 source "arch/arm/mach-ipq40xx/Kconfig"
2054 source "arch/arm/mach-k3/Kconfig"
2056 source "arch/arm/mach-keystone/Kconfig"
2058 source "arch/arm/mach-kirkwood/Kconfig"
2060 source "arch/arm/mach-lpc32xx/Kconfig"
2062 source "arch/arm/mach-mvebu/Kconfig"
2064 source "arch/arm/mach-octeontx/Kconfig"
2066 source "arch/arm/mach-octeontx2/Kconfig"
2068 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2070 source "arch/arm/mach-imx/mx2/Kconfig"
2072 source "arch/arm/mach-imx/mx3/Kconfig"
2074 source "arch/arm/mach-imx/mx5/Kconfig"
2076 source "arch/arm/mach-imx/mx6/Kconfig"
2078 source "arch/arm/mach-imx/mx7/Kconfig"
2080 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2082 source "arch/arm/mach-imx/imx8/Kconfig"
2084 source "arch/arm/mach-imx/imx8m/Kconfig"
2086 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2088 source "arch/arm/mach-imx/imxrt/Kconfig"
2090 source "arch/arm/mach-imx/mxs/Kconfig"
2092 source "arch/arm/mach-omap2/Kconfig"
2094 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2096 source "arch/arm/mach-orion5x/Kconfig"
2098 source "arch/arm/mach-owl/Kconfig"
2100 source "arch/arm/mach-rmobile/Kconfig"
2102 source "arch/arm/mach-meson/Kconfig"
2104 source "arch/arm/mach-mediatek/Kconfig"
2106 source "arch/arm/mach-qemu/Kconfig"
2108 source "arch/arm/mach-rockchip/Kconfig"
2110 source "arch/arm/mach-s5pc1xx/Kconfig"
2112 source "arch/arm/mach-snapdragon/Kconfig"
2114 source "arch/arm/mach-socfpga/Kconfig"
2116 source "arch/arm/mach-sti/Kconfig"
2118 source "arch/arm/mach-stm32/Kconfig"
2120 source "arch/arm/mach-stm32mp/Kconfig"
2122 source "arch/arm/mach-sunxi/Kconfig"
2124 source "arch/arm/mach-tegra/Kconfig"
2126 source "arch/arm/mach-u8500/Kconfig"
2128 source "arch/arm/mach-uniphier/Kconfig"
2130 source "arch/arm/cpu/armv7/vf610/Kconfig"
2132 source "arch/arm/mach-zynq/Kconfig"
2134 source "arch/arm/mach-zynqmp/Kconfig"
2136 source "arch/arm/mach-versal/Kconfig"
2138 source "arch/arm/mach-zynqmp-r5/Kconfig"
2140 source "arch/arm/cpu/armv7/Kconfig"
2142 source "arch/arm/cpu/armv8/Kconfig"
2144 source "arch/arm/mach-imx/Kconfig"
2146 source "arch/arm/mach-nexell/Kconfig"
2148 source "board/armltd/total_compute/Kconfig"
2150 source "board/bosch/shc/Kconfig"
2151 source "board/bosch/guardian/Kconfig"
2152 source "board/CarMediaLab/flea3/Kconfig"
2153 source "board/Marvell/aspenite/Kconfig"
2154 source "board/Marvell/octeontx/Kconfig"
2155 source "board/Marvell/octeontx2/Kconfig"
2156 source "board/armltd/vexpress/Kconfig"
2157 source "board/armltd/vexpress64/Kconfig"
2158 source "board/cortina/presidio-asic/Kconfig"
2159 source "board/broadcom/bcm963158/Kconfig"
2160 source "board/broadcom/bcm968360bg/Kconfig"
2161 source "board/broadcom/bcm968580xref/Kconfig"
2162 source "board/broadcom/bcmns3/Kconfig"
2163 source "board/cavium/thunderx/Kconfig"
2164 source "board/eets/pdu001/Kconfig"
2165 source "board/emulation/qemu-arm/Kconfig"
2166 source "board/freescale/ls2080aqds/Kconfig"
2167 source "board/freescale/ls2080ardb/Kconfig"
2168 source "board/freescale/ls1088a/Kconfig"
2169 source "board/freescale/ls1028a/Kconfig"
2170 source "board/freescale/ls1021aqds/Kconfig"
2171 source "board/freescale/ls1043aqds/Kconfig"
2172 source "board/freescale/ls1021atwr/Kconfig"
2173 source "board/freescale/ls1021atsn/Kconfig"
2174 source "board/freescale/ls1021aiot/Kconfig"
2175 source "board/freescale/ls1046aqds/Kconfig"
2176 source "board/freescale/ls1043ardb/Kconfig"
2177 source "board/freescale/ls1046ardb/Kconfig"
2178 source "board/freescale/ls1046afrwy/Kconfig"
2179 source "board/freescale/ls1012aqds/Kconfig"
2180 source "board/freescale/ls1012ardb/Kconfig"
2181 source "board/freescale/ls1012afrdm/Kconfig"
2182 source "board/freescale/lx2160a/Kconfig"
2183 source "board/grinn/chiliboard/Kconfig"
2184 source "board/hisilicon/hikey/Kconfig"
2185 source "board/hisilicon/hikey960/Kconfig"
2186 source "board/hisilicon/poplar/Kconfig"
2187 source "board/isee/igep003x/Kconfig"
2188 source "board/kontron/sl28/Kconfig"
2189 source "board/myir/mys_6ulx/Kconfig"
2190 source "board/seeed/npi_imx6ull/Kconfig"
2191 source "board/socionext/developerbox/Kconfig"
2192 source "board/st/stv0991/Kconfig"
2193 source "board/tcl/sl50/Kconfig"
2194 source "board/toradex/colibri_pxa270/Kconfig"
2195 source "board/variscite/dart_6ul/Kconfig"
2196 source "board/vscom/baltos/Kconfig"
2197 source "board/phytium/durian/Kconfig"
2198 source "board/xen/xenguest_arm64/Kconfig"
2199 source "board/keymile/Kconfig"
2201 source "arch/arm/Kconfig.debug"
2206 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
2207 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
2208 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64