5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
14 select HAVE_KPROBES if !XIP_KERNEL
15 select HAVE_KRETPROBES if (HAVE_KPROBES)
16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
24 select HAVE_KERNEL_LZMA
27 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API
30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_GENERIC_HARDIRQS
33 select GENERIC_IRQ_SHOW
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select GENERIC_PCI_IOMAP
36 select HAVE_BPF_JIT if NET
38 The ARM series is a line of low-power-consumption RISC chip designs
39 licensed by ARM Ltd and targeted at embedded applications and
40 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
41 manufactured, but legacy ARM-based PC hardware remains popular in
42 Europe. There is an ARM Linux project with a web page at
43 <http://www.arm.linux.org.uk/>.
45 config ARM_HAS_SG_CHAIN
54 config SYS_SUPPORTS_APM_EMULATION
60 config ARCH_USES_GETTIMEOFFSET
64 config GENERIC_CLOCKEVENTS
67 config GENERIC_CLOCKEVENTS_BROADCAST
69 depends on GENERIC_CLOCKEVENTS
78 select GENERIC_ALLOCATOR
89 The Extended Industry Standard Architecture (EISA) bus was
90 developed as an open alternative to the IBM MicroChannel bus.
92 The EISA bus provided some of the features of the IBM MicroChannel
93 bus while maintaining backward compatibility with cards made for
94 the older ISA bus. The EISA bus saw limited use between 1988 and
95 1995 when it was made obsolete by the PCI bus.
97 Say Y here if you are building a kernel for an EISA-based machine.
107 MicroChannel Architecture is found in some IBM PS/2 machines and
108 laptops. It is a bus system similar to PCI or ISA. See
109 <file:Documentation/mca.txt> (and especially the web page given
110 there) before attempting to build an MCA bus kernel.
112 config STACKTRACE_SUPPORT
116 config HAVE_LATENCYTOP_SUPPORT
121 config LOCKDEP_SUPPORT
125 config TRACE_IRQFLAGS_SUPPORT
129 config HARDIRQS_SW_RESEND
133 config GENERIC_IRQ_PROBE
137 config GENERIC_LOCKBREAK
140 depends on SMP && PREEMPT
142 config RWSEM_GENERIC_SPINLOCK
146 config RWSEM_XCHGADD_ALGORITHM
149 config ARCH_HAS_ILOG2_U32
152 config ARCH_HAS_ILOG2_U64
155 config ARCH_HAS_CPUFREQ
158 Internal node to signify that the ARCH has CPUFREQ support
159 and that the relevant menu configurations are displayed for
162 config ARCH_HAS_CPU_IDLE_WAIT
165 config GENERIC_HWEIGHT
169 config GENERIC_CALIBRATE_DELAY
173 config ARCH_MAY_HAVE_PC_FDC
179 config NEED_DMA_MAP_STATE
182 config GENERIC_ISA_DMA
188 config NEED_RET_TO_USER
196 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
197 default DRAM_BASE if REMAP_VECTORS_TO_RAM
200 The base address of exception vectors.
202 config ARM_PATCH_PHYS_VIRT
203 bool "Patch physical to virtual translations at runtime" if EMBEDDED
205 depends on !XIP_KERNEL && MMU
206 depends on !ARCH_REALVIEW || !SPARSEMEM
208 Patch phys-to-virt and virt-to-phys translation functions at
209 boot and module load time according to the position of the
210 kernel in system memory.
212 This can only be used with non-XIP MMU kernels where the base
213 of physical memory is at a 16MB boundary.
215 Only disable this option if you know that you do not require
216 this feature (eg, building a kernel for a single machine) and
217 you need to shrink the kernel to the minimal size.
219 config NEED_MACH_MEMORY_H
222 Select this when mach/memory.h is required to provide special
223 definitions for this platform. The need for mach/memory.h should
224 be avoided when possible.
227 hex "Physical address of main memory" if MMU
228 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
229 default DRAM_BASE if !MMU
231 Please provide the physical address corresponding to the
232 location of main memory in your system.
238 source "init/Kconfig"
240 source "kernel/Kconfig.freezer"
245 bool "MMU-based Paged Memory Management Support"
248 Select if you want MMU-based virtualised addressing space
249 support by paged memory management. If unsure, say 'Y'.
252 # The "ARM system type" choice list is ordered alphabetically by option
253 # text. Please add new entries in the option alphabetic order.
256 prompt "ARM system type"
257 default ARCH_VERSATILE
259 config ARCH_INTEGRATOR
260 bool "ARM Ltd. Integrator family"
262 select ARCH_HAS_CPUFREQ
264 select HAVE_MACH_CLKDEV
267 select GENERIC_CLOCKEVENTS
268 select PLAT_VERSATILE
269 select PLAT_VERSATILE_FPGA_IRQ
270 select NEED_MACH_MEMORY_H
273 Support for ARM's Integrator platform.
276 bool "ARM Ltd. RealView family"
279 select HAVE_MACH_CLKDEV
281 select GENERIC_CLOCKEVENTS
282 select ARCH_WANT_OPTIONAL_GPIOLIB
283 select PLAT_VERSATILE
284 select PLAT_VERSATILE_CLCD
285 select ARM_TIMER_SP804
286 select GPIO_PL061 if GPIOLIB
287 select NEED_MACH_MEMORY_H
289 This enables support for ARM Ltd RealView boards.
291 config ARCH_VERSATILE
292 bool "ARM Ltd. Versatile family"
296 select HAVE_MACH_CLKDEV
298 select GENERIC_CLOCKEVENTS
299 select ARCH_WANT_OPTIONAL_GPIOLIB
300 select PLAT_VERSATILE
301 select PLAT_VERSATILE_CLCD
302 select PLAT_VERSATILE_FPGA_IRQ
303 select ARM_TIMER_SP804
305 This enables support for ARM Ltd Versatile board.
308 bool "ARM Ltd. Versatile Express family"
309 select ARCH_WANT_OPTIONAL_GPIOLIB
311 select ARM_TIMER_SP804
313 select HAVE_MACH_CLKDEV
314 select GENERIC_CLOCKEVENTS
316 select HAVE_PATA_PLATFORM
319 select PLAT_VERSATILE
320 select PLAT_VERSATILE_CLCD
322 This enables support for the ARM Ltd Versatile Express boards.
326 select ARCH_REQUIRE_GPIOLIB
331 This enables support for systems based on the Atmel AT91RM9200,
335 bool "Broadcom BCMRING"
339 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select ARCH_WANT_OPTIONAL_GPIOLIB
344 Support for Broadcom's BCMRing platform.
347 bool "Calxeda Highbank-based"
348 select ARCH_WANT_OPTIONAL_GPIOLIB
351 select ARM_TIMER_SP804
355 select GENERIC_CLOCKEVENTS
361 Support for the Calxeda Highbank SoC based boards.
364 bool "Cirrus Logic CLPS711x/EP721x-based"
366 select ARCH_USES_GETTIMEOFFSET
367 select NEED_MACH_MEMORY_H
369 Support for Cirrus Logic 711x/721x based boards.
372 bool "Cavium Networks CNS3XXX family"
374 select GENERIC_CLOCKEVENTS
376 select MIGHT_HAVE_CACHE_L2X0
377 select MIGHT_HAVE_PCI
378 select PCI_DOMAINS if PCI
380 Support for Cavium Networks CNS3XXX platform.
383 bool "Cortina Systems Gemini"
385 select ARCH_REQUIRE_GPIOLIB
386 select ARCH_USES_GETTIMEOFFSET
388 Support for the Cortina Systems Gemini family SoCs
391 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
394 select GENERIC_CLOCKEVENTS
396 select GENERIC_IRQ_CHIP
397 select MIGHT_HAVE_CACHE_L2X0
401 Support for CSR SiRFSoC ARM Cortex A9 Platform
408 select ARCH_USES_GETTIMEOFFSET
409 select NEED_MACH_MEMORY_H
411 This is an evaluation board for the StrongARM processor available
412 from Digital. It has limited hardware on-board, including an
413 Ethernet interface, two PCMCIA sockets, two serial ports and a
422 select ARCH_REQUIRE_GPIOLIB
423 select ARCH_HAS_HOLES_MEMORYMODEL
424 select ARCH_USES_GETTIMEOFFSET
425 select NEED_MACH_MEMORY_H
427 This enables support for the Cirrus EP93xx series of CPUs.
429 config ARCH_FOOTBRIDGE
433 select GENERIC_CLOCKEVENTS
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Freescale MXC/iMX-based"
442 select GENERIC_CLOCKEVENTS
443 select ARCH_REQUIRE_GPIOLIB
446 select GENERIC_IRQ_CHIP
447 select MULTI_IRQ_HANDLER
449 Support for Freescale MXC/iMX-based family of processors
452 bool "Freescale MXS-based"
453 select GENERIC_CLOCKEVENTS
454 select ARCH_REQUIRE_GPIOLIB
457 select HAVE_CLK_PREPARE
459 Support for Freescale MXS-based family of processors
462 bool "Hilscher NetX based"
466 select GENERIC_CLOCKEVENTS
468 This enables support for systems based on the Hilscher NetX Soc
471 bool "Hynix HMS720x-based"
474 select ARCH_USES_GETTIMEOFFSET
476 This enables support for systems based on the Hynix HMS720x
484 select ARCH_SUPPORTS_MSI
486 select NEED_MACH_MEMORY_H
487 select NEED_RET_TO_USER
489 Support for Intel's IOP13XX (XScale) family of processors.
495 select NEED_RET_TO_USER
498 select ARCH_REQUIRE_GPIOLIB
500 Support for Intel's 80219 and IOP32X (XScale) family of
507 select NEED_RET_TO_USER
510 select ARCH_REQUIRE_GPIOLIB
512 Support for Intel's IOP33X (XScale) family of processors.
519 select ARCH_USES_GETTIMEOFFSET
520 select NEED_MACH_MEMORY_H
522 Support for Intel's IXP23xx (XScale) family of processors.
525 bool "IXP2400/2800-based"
529 select ARCH_USES_GETTIMEOFFSET
530 select NEED_MACH_MEMORY_H
532 Support for Intel's IXP2400/2800 (XScale) family of processors.
540 select GENERIC_CLOCKEVENTS
541 select MIGHT_HAVE_PCI
542 select DMABOUNCE if PCI
544 Support for Intel's IXP4XX (XScale) family of processors.
550 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_CLOCKEVENTS
554 Support for the Marvell Dove SoC 88AP510
557 bool "Marvell Kirkwood"
560 select ARCH_REQUIRE_GPIOLIB
561 select GENERIC_CLOCKEVENTS
564 Support for the following Marvell Kirkwood series SoCs:
565 88F6180, 88F6192 and 88F6281.
571 select ARCH_REQUIRE_GPIOLIB
574 select USB_ARCH_HAS_OHCI
576 select GENERIC_CLOCKEVENTS
578 Support for the NXP LPC32XX family of processors
581 bool "Marvell MV78xx0"
584 select ARCH_REQUIRE_GPIOLIB
585 select GENERIC_CLOCKEVENTS
588 Support for the following Marvell MV78xx0 series SoCs:
596 select ARCH_REQUIRE_GPIOLIB
597 select GENERIC_CLOCKEVENTS
600 Support for the following Marvell Orion 5x series SoCs:
601 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
602 Orion-2 (5281), Orion-1-90 (6183).
605 bool "Marvell PXA168/910/MMP2"
607 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
614 select GENERIC_ALLOCATOR
616 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
619 bool "Micrel/Kendin KS8695"
621 select ARCH_REQUIRE_GPIOLIB
622 select ARCH_USES_GETTIMEOFFSET
623 select NEED_MACH_MEMORY_H
625 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
626 System-on-Chip devices.
629 bool "Nuvoton W90X900 CPU"
631 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
636 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
637 At present, the w90x900 has been renamed nuc900, regarding
638 the ARM series product line, you can login the following
639 link address to know more.
641 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
642 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
648 select GENERIC_CLOCKEVENTS
652 select MIGHT_HAVE_CACHE_L2X0
653 select ARCH_HAS_CPUFREQ
655 This enables support for NVIDIA Tegra based systems (Tegra APX,
656 Tegra 6xx and Tegra 2 series).
658 config ARCH_PICOXCELL
659 bool "Picochip picoXcell"
660 select ARCH_REQUIRE_GPIOLIB
661 select ARM_PATCH_PHYS_VIRT
665 select GENERIC_CLOCKEVENTS
672 This enables support for systems based on the Picochip picoXcell
673 family of Femtocell devices. The picoxcell support requires device tree
677 bool "Philips Nexperia PNX4008 Mobile"
680 select ARCH_USES_GETTIMEOFFSET
682 This enables support for Philips PNX4008 mobile platform.
685 bool "PXA2xx/PXA3xx-based"
688 select ARCH_HAS_CPUFREQ
691 select ARCH_REQUIRE_GPIOLIB
692 select GENERIC_CLOCKEVENTS
698 select MULTI_IRQ_HANDLER
699 select ARM_CPU_SUSPEND if PM
702 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
707 select GENERIC_CLOCKEVENTS
708 select ARCH_REQUIRE_GPIOLIB
711 Support for Qualcomm MSM/QSD based systems. This runs on the
712 apps processor of the MSM/QSD and depends on a shared memory
713 interface to the modem processor which runs the baseband
714 stack and controls some vital subsystems
715 (clock and power control, etc).
718 bool "Renesas SH-Mobile / R-Mobile"
721 select HAVE_MACH_CLKDEV
723 select GENERIC_CLOCKEVENTS
724 select MIGHT_HAVE_CACHE_L2X0
727 select MULTI_IRQ_HANDLER
728 select PM_GENERIC_DOMAINS if PM
729 select NEED_MACH_MEMORY_H
731 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
737 select ARCH_MAY_HAVE_PC_FDC
738 select HAVE_PATA_PLATFORM
741 select ARCH_SPARSEMEM_ENABLE
742 select ARCH_USES_GETTIMEOFFSET
744 select NEED_MACH_MEMORY_H
746 On the Acorn Risc-PC, Linux can support the internal IDE disk and
747 CD-ROM interface, serial and parallel port, and the floppy drive.
754 select ARCH_SPARSEMEM_ENABLE
756 select ARCH_HAS_CPUFREQ
758 select GENERIC_CLOCKEVENTS
761 select ARCH_REQUIRE_GPIOLIB
763 select NEED_MACH_MEMORY_H
766 Support for StrongARM 11x0 based boards.
769 bool "Samsung S3C24XX SoCs"
771 select ARCH_HAS_CPUFREQ
774 select ARCH_USES_GETTIMEOFFSET
775 select HAVE_S3C2410_I2C if I2C
776 select HAVE_S3C_RTC if RTC_CLASS
777 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
780 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
781 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
782 Samsung SMDK2410 development board (and derivatives).
785 bool "Samsung S3C64XX"
793 select ARCH_USES_GETTIMEOFFSET
794 select ARCH_HAS_CPUFREQ
795 select ARCH_REQUIRE_GPIOLIB
796 select SAMSUNG_CLKSRC
797 select SAMSUNG_IRQ_VIC_TIMER
798 select S3C_GPIO_TRACK
800 select USB_ARCH_HAS_OHCI
801 select SAMSUNG_GPIOLIB_4BIT
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 Samsung S3C64XX series based systems
808 bool "Samsung S5P6440 S5P6450"
814 select HAVE_S3C2410_WATCHDOG if WATCHDOG
815 select GENERIC_CLOCKEVENTS
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C_RTC if RTC_CLASS
819 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
823 bool "Samsung S5PC100"
828 select ARCH_USES_GETTIMEOFFSET
829 select HAVE_S3C2410_I2C if I2C
830 select HAVE_S3C_RTC if RTC_CLASS
831 select HAVE_S3C2410_WATCHDOG if WATCHDOG
833 Samsung S5PC100 series based systems
836 bool "Samsung S5PV210/S5PC110"
838 select ARCH_SPARSEMEM_ENABLE
839 select ARCH_HAS_HOLES_MEMORYMODEL
844 select ARCH_HAS_CPUFREQ
845 select GENERIC_CLOCKEVENTS
846 select HAVE_S3C2410_I2C if I2C
847 select HAVE_S3C_RTC if RTC_CLASS
848 select HAVE_S3C2410_WATCHDOG if WATCHDOG
849 select NEED_MACH_MEMORY_H
851 Samsung S5PV210/S5PC110 series based systems
854 bool "SAMSUNG EXYNOS"
856 select ARCH_SPARSEMEM_ENABLE
857 select ARCH_HAS_HOLES_MEMORYMODEL
861 select ARCH_HAS_CPUFREQ
862 select GENERIC_CLOCKEVENTS
863 select HAVE_S3C_RTC if RTC_CLASS
864 select HAVE_S3C2410_I2C if I2C
865 select HAVE_S3C2410_WATCHDOG if WATCHDOG
866 select NEED_MACH_MEMORY_H
868 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
877 select ARCH_USES_GETTIMEOFFSET
878 select NEED_MACH_MEMORY_H
880 Support for the StrongARM based Digital DNARD machine, also known
881 as "Shark" (<http://www.shark-linux.de/shark.html>).
884 bool "ST-Ericsson U300 Series"
890 select ARM_PATCH_PHYS_VIRT
892 select GENERIC_CLOCKEVENTS
894 select HAVE_MACH_CLKDEV
896 select ARCH_REQUIRE_GPIOLIB
898 Support for ST-Ericsson U300 series mobile platforms.
901 bool "ST-Ericsson U8500 Series"
905 select GENERIC_CLOCKEVENTS
907 select ARCH_REQUIRE_GPIOLIB
908 select ARCH_HAS_CPUFREQ
910 select MIGHT_HAVE_CACHE_L2X0
912 Support for ST-Ericsson's Ux500 architecture
915 bool "STMicroelectronics Nomadik"
920 select GENERIC_CLOCKEVENTS
921 select MIGHT_HAVE_CACHE_L2X0
922 select ARCH_REQUIRE_GPIOLIB
924 Support for the Nomadik platform by ST-Ericsson
928 select GENERIC_CLOCKEVENTS
929 select ARCH_REQUIRE_GPIOLIB
933 select GENERIC_ALLOCATOR
934 select GENERIC_IRQ_CHIP
935 select ARCH_HAS_HOLES_MEMORYMODEL
937 Support for TI's DaVinci platform.
942 select ARCH_REQUIRE_GPIOLIB
943 select ARCH_HAS_CPUFREQ
945 select GENERIC_CLOCKEVENTS
946 select ARCH_HAS_HOLES_MEMORYMODEL
948 Support for TI's OMAP platform (OMAP1/2/3/4).
953 select ARCH_REQUIRE_GPIOLIB
956 select GENERIC_CLOCKEVENTS
959 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
962 bool "VIA/WonderMedia 85xx"
965 select ARCH_HAS_CPUFREQ
966 select GENERIC_CLOCKEVENTS
967 select ARCH_REQUIRE_GPIOLIB
970 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
973 bool "Xilinx Zynq ARM Cortex A9 Platform"
975 select GENERIC_CLOCKEVENTS
980 select MIGHT_HAVE_CACHE_L2X0
983 Support for Xilinx Zynq ARM Cortex A9 Platform
987 # This is sorted alphabetically by mach-* pathname. However, plat-*
988 # Kconfigs may be included either alphabetically (according to the
989 # plat- suffix) or along side the corresponding mach-* source.
991 source "arch/arm/mach-at91/Kconfig"
993 source "arch/arm/mach-bcmring/Kconfig"
995 source "arch/arm/mach-clps711x/Kconfig"
997 source "arch/arm/mach-cns3xxx/Kconfig"
999 source "arch/arm/mach-davinci/Kconfig"
1001 source "arch/arm/mach-dove/Kconfig"
1003 source "arch/arm/mach-ep93xx/Kconfig"
1005 source "arch/arm/mach-footbridge/Kconfig"
1007 source "arch/arm/mach-gemini/Kconfig"
1009 source "arch/arm/mach-h720x/Kconfig"
1011 source "arch/arm/mach-integrator/Kconfig"
1013 source "arch/arm/mach-iop32x/Kconfig"
1015 source "arch/arm/mach-iop33x/Kconfig"
1017 source "arch/arm/mach-iop13xx/Kconfig"
1019 source "arch/arm/mach-ixp4xx/Kconfig"
1021 source "arch/arm/mach-ixp2000/Kconfig"
1023 source "arch/arm/mach-ixp23xx/Kconfig"
1025 source "arch/arm/mach-kirkwood/Kconfig"
1027 source "arch/arm/mach-ks8695/Kconfig"
1029 source "arch/arm/mach-lpc32xx/Kconfig"
1031 source "arch/arm/mach-msm/Kconfig"
1033 source "arch/arm/mach-mv78xx0/Kconfig"
1035 source "arch/arm/plat-mxc/Kconfig"
1037 source "arch/arm/mach-mxs/Kconfig"
1039 source "arch/arm/mach-netx/Kconfig"
1041 source "arch/arm/mach-nomadik/Kconfig"
1042 source "arch/arm/plat-nomadik/Kconfig"
1044 source "arch/arm/plat-omap/Kconfig"
1046 source "arch/arm/mach-omap1/Kconfig"
1048 source "arch/arm/mach-omap2/Kconfig"
1050 source "arch/arm/mach-orion5x/Kconfig"
1052 source "arch/arm/mach-pxa/Kconfig"
1053 source "arch/arm/plat-pxa/Kconfig"
1055 source "arch/arm/mach-mmp/Kconfig"
1057 source "arch/arm/mach-realview/Kconfig"
1059 source "arch/arm/mach-sa1100/Kconfig"
1061 source "arch/arm/plat-samsung/Kconfig"
1062 source "arch/arm/plat-s3c24xx/Kconfig"
1063 source "arch/arm/plat-s5p/Kconfig"
1065 source "arch/arm/plat-spear/Kconfig"
1067 source "arch/arm/mach-s3c24xx/Kconfig"
1069 source "arch/arm/mach-s3c2412/Kconfig"
1070 source "arch/arm/mach-s3c2440/Kconfig"
1074 source "arch/arm/mach-s3c64xx/Kconfig"
1077 source "arch/arm/mach-s5p64x0/Kconfig"
1079 source "arch/arm/mach-s5pc100/Kconfig"
1081 source "arch/arm/mach-s5pv210/Kconfig"
1083 source "arch/arm/mach-exynos/Kconfig"
1085 source "arch/arm/mach-shmobile/Kconfig"
1087 source "arch/arm/mach-tegra/Kconfig"
1089 source "arch/arm/mach-u300/Kconfig"
1091 source "arch/arm/mach-ux500/Kconfig"
1093 source "arch/arm/mach-versatile/Kconfig"
1095 source "arch/arm/mach-vexpress/Kconfig"
1096 source "arch/arm/plat-versatile/Kconfig"
1098 source "arch/arm/mach-vt8500/Kconfig"
1100 source "arch/arm/mach-w90x900/Kconfig"
1102 # Definitions to make life easier
1108 select GENERIC_CLOCKEVENTS
1113 select GENERIC_IRQ_CHIP
1118 config PLAT_VERSATILE
1121 config ARM_TIMER_SP804
1124 select HAVE_SCHED_CLOCK
1126 source arch/arm/mm/Kconfig
1130 default 16 if ARCH_EP93XX
1134 bool "Enable iWMMXt support"
1135 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1136 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1138 Enable support for iWMMXt context switching at run time if
1139 running on a CPU that supports it.
1143 depends on CPU_XSCALE
1147 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1148 (!ARCH_OMAP3 || OMAP3_EMU)
1152 config MULTI_IRQ_HANDLER
1155 Allow each machine to specify it's own IRQ handler at run time.
1158 source "arch/arm/Kconfig-nommu"
1161 config ARM_ERRATA_411920
1162 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1163 depends on CPU_V6 || CPU_V6K
1165 Invalidation of the Instruction Cache operation can
1166 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1167 It does not affect the MPCore. This option enables the ARM Ltd.
1168 recommended workaround.
1170 config ARM_ERRATA_430973
1171 bool "ARM errata: Stale prediction on replaced interworking branch"
1174 This option enables the workaround for the 430973 Cortex-A8
1175 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1176 interworking branch is replaced with another code sequence at the
1177 same virtual address, whether due to self-modifying code or virtual
1178 to physical address re-mapping, Cortex-A8 does not recover from the
1179 stale interworking branch prediction. This results in Cortex-A8
1180 executing the new code sequence in the incorrect ARM or Thumb state.
1181 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1182 and also flushes the branch target cache at every context switch.
1183 Note that setting specific bits in the ACTLR register may not be
1184 available in non-secure mode.
1186 config ARM_ERRATA_458693
1187 bool "ARM errata: Processor deadlock when a false hazard is created"
1190 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1191 erratum. For very specific sequences of memory operations, it is
1192 possible for a hazard condition intended for a cache line to instead
1193 be incorrectly associated with a different cache line. This false
1194 hazard might then cause a processor deadlock. The workaround enables
1195 the L1 caching of the NEON accesses and disables the PLD instruction
1196 in the ACTLR register. Note that setting specific bits in the ACTLR
1197 register may not be available in non-secure mode.
1199 config ARM_ERRATA_460075
1200 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1203 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1204 erratum. Any asynchronous access to the L2 cache may encounter a
1205 situation in which recent store transactions to the L2 cache are lost
1206 and overwritten with stale memory contents from external memory. The
1207 workaround disables the write-allocate mode for the L2 cache via the
1208 ACTLR register. Note that setting specific bits in the ACTLR register
1209 may not be available in non-secure mode.
1211 config ARM_ERRATA_742230
1212 bool "ARM errata: DMB operation may be faulty"
1213 depends on CPU_V7 && SMP
1215 This option enables the workaround for the 742230 Cortex-A9
1216 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1217 between two write operations may not ensure the correct visibility
1218 ordering of the two writes. This workaround sets a specific bit in
1219 the diagnostic register of the Cortex-A9 which causes the DMB
1220 instruction to behave as a DSB, ensuring the correct behaviour of
1223 config ARM_ERRATA_742231
1224 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1225 depends on CPU_V7 && SMP
1227 This option enables the workaround for the 742231 Cortex-A9
1228 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1229 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1230 accessing some data located in the same cache line, may get corrupted
1231 data due to bad handling of the address hazard when the line gets
1232 replaced from one of the CPUs at the same time as another CPU is
1233 accessing it. This workaround sets specific bits in the diagnostic
1234 register of the Cortex-A9 which reduces the linefill issuing
1235 capabilities of the processor.
1237 config PL310_ERRATA_588369
1238 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1239 depends on CACHE_L2X0
1241 The PL310 L2 cache controller implements three types of Clean &
1242 Invalidate maintenance operations: by Physical Address
1243 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1244 They are architecturally defined to behave as the execution of a
1245 clean operation followed immediately by an invalidate operation,
1246 both performing to the same memory location. This functionality
1247 is not correctly implemented in PL310 as clean lines are not
1248 invalidated as a result of these operations.
1250 config ARM_ERRATA_720789
1251 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1254 This option enables the workaround for the 720789 Cortex-A9 (prior to
1255 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1256 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1257 As a consequence of this erratum, some TLB entries which should be
1258 invalidated are not, resulting in an incoherency in the system page
1259 tables. The workaround changes the TLB flushing routines to invalidate
1260 entries regardless of the ASID.
1262 config PL310_ERRATA_727915
1263 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1264 depends on CACHE_L2X0
1266 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1267 operation (offset 0x7FC). This operation runs in background so that
1268 PL310 can handle normal accesses while it is in progress. Under very
1269 rare circumstances, due to this erratum, write data can be lost when
1270 PL310 treats a cacheable write transaction during a Clean &
1271 Invalidate by Way operation.
1273 config ARM_ERRATA_743622
1274 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1277 This option enables the workaround for the 743622 Cortex-A9
1278 (r2p*) erratum. Under very rare conditions, a faulty
1279 optimisation in the Cortex-A9 Store Buffer may lead to data
1280 corruption. This workaround sets a specific bit in the diagnostic
1281 register of the Cortex-A9 which disables the Store Buffer
1282 optimisation, preventing the defect from occurring. This has no
1283 visible impact on the overall performance or power consumption of the
1286 config ARM_ERRATA_751472
1287 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1290 This option enables the workaround for the 751472 Cortex-A9 (prior
1291 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1292 completion of a following broadcasted operation if the second
1293 operation is received by a CPU before the ICIALLUIS has completed,
1294 potentially leading to corrupted entries in the cache or TLB.
1296 config PL310_ERRATA_753970
1297 bool "PL310 errata: cache sync operation may be faulty"
1298 depends on CACHE_PL310
1300 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1302 Under some condition the effect of cache sync operation on
1303 the store buffer still remains when the operation completes.
1304 This means that the store buffer is always asked to drain and
1305 this prevents it from merging any further writes. The workaround
1306 is to replace the normal offset of cache sync operation (0x730)
1307 by another offset targeting an unmapped PL310 register 0x740.
1308 This has the same effect as the cache sync operation: store buffer
1309 drain and waiting for all buffers empty.
1311 config ARM_ERRATA_754322
1312 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1315 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1316 r3p*) erratum. A speculative memory access may cause a page table walk
1317 which starts prior to an ASID switch but completes afterwards. This
1318 can populate the micro-TLB with a stale entry which may be hit with
1319 the new ASID. This workaround places two dsb instructions in the mm
1320 switching code so that no page table walks can cross the ASID switch.
1322 config ARM_ERRATA_754327
1323 bool "ARM errata: no automatic Store Buffer drain"
1324 depends on CPU_V7 && SMP
1326 This option enables the workaround for the 754327 Cortex-A9 (prior to
1327 r2p0) erratum. The Store Buffer does not have any automatic draining
1328 mechanism and therefore a livelock may occur if an external agent
1329 continuously polls a memory location waiting to observe an update.
1330 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1331 written polling loops from denying visibility of updates to memory.
1333 config ARM_ERRATA_364296
1334 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1335 depends on CPU_V6 && !SMP
1337 This options enables the workaround for the 364296 ARM1136
1338 r0p2 erratum (possible cache data corruption with
1339 hit-under-miss enabled). It sets the undocumented bit 31 in
1340 the auxiliary control register and the FI bit in the control
1341 register, thus disabling hit-under-miss without putting the
1342 processor into full low interrupt latency mode. ARM11MPCore
1345 config ARM_ERRATA_764369
1346 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1347 depends on CPU_V7 && SMP
1349 This option enables the workaround for erratum 764369
1350 affecting Cortex-A9 MPCore with two or more processors (all
1351 current revisions). Under certain timing circumstances, a data
1352 cache line maintenance operation by MVA targeting an Inner
1353 Shareable memory region may fail to proceed up to either the
1354 Point of Coherency or to the Point of Unification of the
1355 system. This workaround adds a DSB instruction before the
1356 relevant cache maintenance functions and sets a specific bit
1357 in the diagnostic control register of the SCU.
1359 config PL310_ERRATA_769419
1360 bool "PL310 errata: no automatic Store Buffer drain"
1361 depends on CACHE_L2X0
1363 On revisions of the PL310 prior to r3p2, the Store Buffer does
1364 not automatically drain. This can cause normal, non-cacheable
1365 writes to be retained when the memory system is idle, leading
1366 to suboptimal I/O performance for drivers using coherent DMA.
1367 This option adds a write barrier to the cpu_idle loop so that,
1368 on systems with an outer cache, the store buffer is drained
1373 source "arch/arm/common/Kconfig"
1383 Find out whether you have ISA slots on your motherboard. ISA is the
1384 name of a bus system, i.e. the way the CPU talks to the other stuff
1385 inside your box. Other bus systems are PCI, EISA, MicroChannel
1386 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1387 newer boards don't support it. If you have ISA, say Y, otherwise N.
1389 # Select ISA DMA controller support
1394 # Select ISA DMA interface
1399 bool "PCI support" if MIGHT_HAVE_PCI
1401 Find out whether you have a PCI motherboard. PCI is the name of a
1402 bus system, i.e. the way the CPU talks to the other stuff inside
1403 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1404 VESA. If you have PCI, say Y, otherwise N.
1410 config PCI_NANOENGINE
1411 bool "BSE nanoEngine PCI support"
1412 depends on SA1100_NANOENGINE
1414 Enable PCI on the BSE nanoEngine board.
1419 # Select the host bridge type
1420 config PCI_HOST_VIA82C505
1422 depends on PCI && ARCH_SHARK
1425 config PCI_HOST_ITE8152
1427 depends on PCI && MACH_ARMCORE
1431 source "drivers/pci/Kconfig"
1433 source "drivers/pcmcia/Kconfig"
1437 menu "Kernel Features"
1439 source "kernel/time/Kconfig"
1444 This option should be selected by machines which have an SMP-
1447 The only effect of this option is to make the SMP-related
1448 options available to the user for configuration.
1451 bool "Symmetric Multi-Processing"
1452 depends on CPU_V6K || CPU_V7
1453 depends on GENERIC_CLOCKEVENTS
1456 select USE_GENERIC_SMP_HELPERS
1457 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1459 This enables support for systems with more than one CPU. If you have
1460 a system with only one CPU, like most personal computers, say N. If
1461 you have a system with more than one CPU, say Y.
1463 If you say N here, the kernel will run on single and multiprocessor
1464 machines, but will use only one CPU of a multiprocessor machine. If
1465 you say Y here, the kernel will run on many, but not all, single
1466 processor machines. On a single processor machine, the kernel will
1467 run faster if you say N here.
1469 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1470 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1471 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1473 If you don't know what to do here, say N.
1476 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1477 depends on EXPERIMENTAL
1478 depends on SMP && !XIP_KERNEL
1481 SMP kernels contain instructions which fail on non-SMP processors.
1482 Enabling this option allows the kernel to modify itself to make
1483 these instructions safe. Disabling it allows about 1K of space
1486 If you don't know what to do here, say Y.
1488 config ARM_CPU_TOPOLOGY
1489 bool "Support cpu topology definition"
1490 depends on SMP && CPU_V7
1493 Support ARM cpu topology definition. The MPIDR register defines
1494 affinity between processors which is then used to describe the cpu
1495 topology of an ARM System.
1498 bool "Multi-core scheduler support"
1499 depends on ARM_CPU_TOPOLOGY
1501 Multi-core scheduler support improves the CPU scheduler's decision
1502 making when dealing with multi-core CPU chips at a cost of slightly
1503 increased overhead in some places. If unsure say N here.
1506 bool "SMT scheduler support"
1507 depends on ARM_CPU_TOPOLOGY
1509 Improves the CPU scheduler's decision making when dealing with
1510 MultiThreading at a cost of slightly increased overhead in some
1511 places. If unsure say N here.
1516 This option enables support for the ARM system coherency unit
1523 This options enables support for the ARM timer and watchdog unit
1526 prompt "Memory split"
1529 Select the desired split between kernel and user memory.
1531 If you are not absolutely sure what you are doing, leave this
1535 bool "3G/1G user/kernel split"
1537 bool "2G/2G user/kernel split"
1539 bool "1G/3G user/kernel split"
1544 default 0x40000000 if VMSPLIT_1G
1545 default 0x80000000 if VMSPLIT_2G
1549 int "Maximum number of CPUs (2-32)"
1555 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1556 depends on SMP && HOTPLUG && EXPERIMENTAL
1558 Say Y here to experiment with turning CPUs off and on. CPUs
1559 can be controlled through /sys/devices/system/cpu.
1562 bool "Use local timer interrupts"
1565 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1567 Enable support for local timers on SMP platforms, rather then the
1568 legacy IPI broadcast method. Local timers allows the system
1569 accounting to be spread across the timer interval, preventing a
1570 "thundering herd" at every timer tick.
1574 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1575 default 355 if ARCH_U8500
1576 default 264 if MACH_H4700
1579 Maximum number of GPIOs in the system.
1581 If unsure, leave the default value.
1583 source kernel/Kconfig.preempt
1587 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1588 ARCH_S5PV210 || ARCH_EXYNOS4
1589 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1590 default AT91_TIMER_HZ if ARCH_AT91
1591 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1594 config THUMB2_KERNEL
1595 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1596 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1598 select ARM_ASM_UNIFIED
1601 By enabling this option, the kernel will be compiled in
1602 Thumb-2 mode. A compiler/assembler that understand the unified
1603 ARM-Thumb syntax is needed.
1607 config THUMB2_AVOID_R_ARM_THM_JUMP11
1608 bool "Work around buggy Thumb-2 short branch relocations in gas"
1609 depends on THUMB2_KERNEL && MODULES
1612 Various binutils versions can resolve Thumb-2 branches to
1613 locally-defined, preemptible global symbols as short-range "b.n"
1614 branch instructions.
1616 This is a problem, because there's no guarantee the final
1617 destination of the symbol, or any candidate locations for a
1618 trampoline, are within range of the branch. For this reason, the
1619 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1620 relocation in modules at all, and it makes little sense to add
1623 The symptom is that the kernel fails with an "unsupported
1624 relocation" error when loading some modules.
1626 Until fixed tools are available, passing
1627 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1628 code which hits this problem, at the cost of a bit of extra runtime
1629 stack usage in some cases.
1631 The problem is described in more detail at:
1632 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1634 Only Thumb-2 kernels are affected.
1636 Unless you are sure your tools don't have this problem, say Y.
1638 config ARM_ASM_UNIFIED
1642 bool "Use the ARM EABI to compile the kernel"
1644 This option allows for the kernel to be compiled using the latest
1645 ARM ABI (aka EABI). This is only useful if you are using a user
1646 space environment that is also compiled with EABI.
1648 Since there are major incompatibilities between the legacy ABI and
1649 EABI, especially with regard to structure member alignment, this
1650 option also changes the kernel syscall calling convention to
1651 disambiguate both ABIs and allow for backward compatibility support
1652 (selected with CONFIG_OABI_COMPAT).
1654 To use this you need GCC version 4.0.0 or later.
1657 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1658 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1661 This option preserves the old syscall interface along with the
1662 new (ARM EABI) one. It also provides a compatibility layer to
1663 intercept syscalls that have structure arguments which layout
1664 in memory differs between the legacy ABI and the new ARM EABI
1665 (only for non "thumb" binaries). This option adds a tiny
1666 overhead to all syscalls and produces a slightly larger kernel.
1667 If you know you'll be using only pure EABI user space then you
1668 can say N here. If this option is not selected and you attempt
1669 to execute a legacy ABI binary then the result will be
1670 UNPREDICTABLE (in fact it can be predicted that it won't work
1671 at all). If in doubt say Y.
1673 config ARCH_HAS_HOLES_MEMORYMODEL
1676 config ARCH_SPARSEMEM_ENABLE
1679 config ARCH_SPARSEMEM_DEFAULT
1680 def_bool ARCH_SPARSEMEM_ENABLE
1682 config ARCH_SELECT_MEMORY_MODEL
1683 def_bool ARCH_SPARSEMEM_ENABLE
1685 config HAVE_ARCH_PFN_VALID
1686 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1689 bool "High Memory Support"
1692 The address space of ARM processors is only 4 Gigabytes large
1693 and it has to accommodate user address space, kernel address
1694 space as well as some memory mapped IO. That means that, if you
1695 have a large amount of physical memory and/or IO, not all of the
1696 memory can be "permanently mapped" by the kernel. The physical
1697 memory that is not permanently mapped is called "high memory".
1699 Depending on the selected kernel/user memory split, minimum
1700 vmalloc space and actual amount of RAM, you may not need this
1701 option which should result in a slightly faster kernel.
1706 bool "Allocate 2nd-level pagetables from highmem"
1709 config HW_PERF_EVENTS
1710 bool "Enable hardware performance counter support for perf events"
1711 depends on PERF_EVENTS && CPU_HAS_PMU
1714 Enable hardware performance counter support for perf events. If
1715 disabled, perf events will use software events only.
1719 config FORCE_MAX_ZONEORDER
1720 int "Maximum zone order" if ARCH_SHMOBILE
1721 range 11 64 if ARCH_SHMOBILE
1722 default "9" if SA1111
1725 The kernel memory allocator divides physically contiguous memory
1726 blocks into "zones", where each zone is a power of two number of
1727 pages. This option selects the largest power of two that the kernel
1728 keeps in the memory allocator. If you need to allocate very large
1729 blocks of physically contiguous memory, then you may need to
1730 increase this value.
1732 This config option is actually maximum order plus one. For example,
1733 a value of 11 means that the largest free memory block is 2^10 pages.
1736 bool "Timer and CPU usage LEDs"
1737 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1738 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1739 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1740 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1741 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1742 ARCH_AT91 || ARCH_DAVINCI || \
1743 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1745 If you say Y here, the LEDs on your machine will be used
1746 to provide useful information about your current system status.
1748 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1749 be able to select which LEDs are active using the options below. If
1750 you are compiling a kernel for the EBSA-110 or the LART however, the
1751 red LED will simply flash regularly to indicate that the system is
1752 still functional. It is safe to say Y here if you have a CATS
1753 system, but the driver will do nothing.
1756 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1757 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1758 || MACH_OMAP_PERSEUS2
1760 depends on !GENERIC_CLOCKEVENTS
1761 default y if ARCH_EBSA110
1763 If you say Y here, one of the system LEDs (the green one on the
1764 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1765 will flash regularly to indicate that the system is still
1766 operational. This is mainly useful to kernel hackers who are
1767 debugging unstable kernels.
1769 The LART uses the same LED for both Timer LED and CPU usage LED
1770 functions. You may choose to use both, but the Timer LED function
1771 will overrule the CPU usage LED.
1774 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1776 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1777 || MACH_OMAP_PERSEUS2
1780 If you say Y here, the red LED will be used to give a good real
1781 time indication of CPU usage, by lighting whenever the idle task
1782 is not currently executing.
1784 The LART uses the same LED for both Timer LED and CPU usage LED
1785 functions. You may choose to use both, but the Timer LED function
1786 will overrule the CPU usage LED.
1788 config ALIGNMENT_TRAP
1790 depends on CPU_CP15_MMU
1791 default y if !ARCH_EBSA110
1792 select HAVE_PROC_CPU if PROC_FS
1794 ARM processors cannot fetch/store information which is not
1795 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1796 address divisible by 4. On 32-bit ARM processors, these non-aligned
1797 fetch/store instructions will be emulated in software if you say
1798 here, which has a severe performance impact. This is necessary for
1799 correct operation of some network protocols. With an IP-only
1800 configuration it is safe to say N, otherwise say Y.
1802 config UACCESS_WITH_MEMCPY
1803 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1804 depends on MMU && EXPERIMENTAL
1805 default y if CPU_FEROCEON
1807 Implement faster copy_to_user and clear_user methods for CPU
1808 cores where a 8-word STM instruction give significantly higher
1809 memory write throughput than a sequence of individual 32bit stores.
1811 A possible side effect is a slight increase in scheduling latency
1812 between threads sharing the same address space if they invoke
1813 such copy operations with large buffers.
1815 However, if the CPU data cache is using a write-allocate mode,
1816 this option is unlikely to provide any performance gain.
1820 prompt "Enable seccomp to safely compute untrusted bytecode"
1822 This kernel feature is useful for number crunching applications
1823 that may need to compute untrusted bytecode during their
1824 execution. By using pipes or other transports made available to
1825 the process as file descriptors supporting the read/write
1826 syscalls, it's possible to isolate those applications in
1827 their own address space using seccomp. Once seccomp is
1828 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1829 and the task is only allowed to execute a few safe syscalls
1830 defined by each seccomp mode.
1832 config CC_STACKPROTECTOR
1833 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1834 depends on EXPERIMENTAL
1836 This option turns on the -fstack-protector GCC feature. This
1837 feature puts, at the beginning of functions, a canary value on
1838 the stack just before the return address, and validates
1839 the value just before actually returning. Stack based buffer
1840 overflows (that need to overwrite this return address) now also
1841 overwrite the canary, which gets detected and the attack is then
1842 neutralized via a kernel panic.
1843 This feature requires gcc version 4.2 or above.
1845 config DEPRECATED_PARAM_STRUCT
1846 bool "Provide old way to pass kernel parameters"
1848 This was deprecated in 2001 and announced to live on for 5 years.
1849 Some old boot loaders still use this way.
1856 bool "Flattened Device Tree support"
1858 select OF_EARLY_FLATTREE
1861 Include support for flattened device tree machine descriptions.
1863 # Compressed boot loader in ROM. Yes, we really want to ask about
1864 # TEXT and BSS so we preserve their values in the config files.
1865 config ZBOOT_ROM_TEXT
1866 hex "Compressed ROM boot loader base address"
1869 The physical address at which the ROM-able zImage is to be
1870 placed in the target. Platforms which normally make use of
1871 ROM-able zImage formats normally set this to a suitable
1872 value in their defconfig file.
1874 If ZBOOT_ROM is not enabled, this has no effect.
1876 config ZBOOT_ROM_BSS
1877 hex "Compressed ROM boot loader BSS address"
1880 The base address of an area of read/write memory in the target
1881 for the ROM-able zImage which must be available while the
1882 decompressor is running. It must be large enough to hold the
1883 entire decompressed kernel plus an additional 128 KiB.
1884 Platforms which normally make use of ROM-able zImage formats
1885 normally set this to a suitable value in their defconfig file.
1887 If ZBOOT_ROM is not enabled, this has no effect.
1890 bool "Compressed boot loader in ROM/flash"
1891 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1893 Say Y here if you intend to execute your compressed kernel image
1894 (zImage) directly from ROM or flash. If unsure, say N.
1897 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1898 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1899 default ZBOOT_ROM_NONE
1901 Include experimental SD/MMC loading code in the ROM-able zImage.
1902 With this enabled it is possible to write the the ROM-able zImage
1903 kernel image to an MMC or SD card and boot the kernel straight
1904 from the reset vector. At reset the processor Mask ROM will load
1905 the first part of the the ROM-able zImage which in turn loads the
1906 rest the kernel image to RAM.
1908 config ZBOOT_ROM_NONE
1909 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1911 Do not load image from SD or MMC
1913 config ZBOOT_ROM_MMCIF
1914 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1916 Load image from MMCIF hardware block.
1918 config ZBOOT_ROM_SH_MOBILE_SDHI
1919 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1921 Load image from SDHI hardware block
1925 config ARM_APPENDED_DTB
1926 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1927 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1929 With this option, the boot code will look for a device tree binary
1930 (DTB) appended to zImage
1931 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1933 This is meant as a backward compatibility convenience for those
1934 systems with a bootloader that can't be upgraded to accommodate
1935 the documented boot protocol using a device tree.
1937 Beware that there is very little in terms of protection against
1938 this option being confused by leftover garbage in memory that might
1939 look like a DTB header after a reboot if no actual DTB is appended
1940 to zImage. Do not leave this option active in a production kernel
1941 if you don't intend to always append a DTB. Proper passing of the
1942 location into r2 of a bootloader provided DTB is always preferable
1945 config ARM_ATAG_DTB_COMPAT
1946 bool "Supplement the appended DTB with traditional ATAG information"
1947 depends on ARM_APPENDED_DTB
1949 Some old bootloaders can't be updated to a DTB capable one, yet
1950 they provide ATAGs with memory configuration, the ramdisk address,
1951 the kernel cmdline string, etc. Such information is dynamically
1952 provided by the bootloader and can't always be stored in a static
1953 DTB. To allow a device tree enabled kernel to be used with such
1954 bootloaders, this option allows zImage to extract the information
1955 from the ATAG list and store it at run time into the appended DTB.
1958 string "Default kernel command string"
1961 On some architectures (EBSA110 and CATS), there is currently no way
1962 for the boot loader to pass arguments to the kernel. For these
1963 architectures, you should supply some command-line options at build
1964 time by entering them here. As a minimum, you should specify the
1965 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1968 prompt "Kernel command line type" if CMDLINE != ""
1969 default CMDLINE_FROM_BOOTLOADER
1971 config CMDLINE_FROM_BOOTLOADER
1972 bool "Use bootloader kernel arguments if available"
1974 Uses the command-line options passed by the boot loader. If
1975 the boot loader doesn't provide any, the default kernel command
1976 string provided in CMDLINE will be used.
1978 config CMDLINE_EXTEND
1979 bool "Extend bootloader kernel arguments"
1981 The command-line arguments provided by the boot loader will be
1982 appended to the default kernel command string.
1984 config CMDLINE_FORCE
1985 bool "Always use the default kernel command string"
1987 Always use the default kernel command string, even if the boot
1988 loader passes other arguments to the kernel.
1989 This is useful if you cannot or don't want to change the
1990 command-line options your boot loader passes to the kernel.
1994 bool "Kernel Execute-In-Place from ROM"
1995 depends on !ZBOOT_ROM && !ARM_LPAE
1997 Execute-In-Place allows the kernel to run from non-volatile storage
1998 directly addressable by the CPU, such as NOR flash. This saves RAM
1999 space since the text section of the kernel is not loaded from flash
2000 to RAM. Read-write sections, such as the data section and stack,
2001 are still copied to RAM. The XIP kernel is not compressed since
2002 it has to run directly from flash, so it will take more space to
2003 store it. The flash address used to link the kernel object files,
2004 and for storing it, is configuration dependent. Therefore, if you
2005 say Y here, you must know the proper physical address where to
2006 store the kernel image depending on your own flash memory usage.
2008 Also note that the make target becomes "make xipImage" rather than
2009 "make zImage" or "make Image". The final kernel binary to put in
2010 ROM memory will be arch/arm/boot/xipImage.
2014 config XIP_PHYS_ADDR
2015 hex "XIP Kernel Physical Location"
2016 depends on XIP_KERNEL
2017 default "0x00080000"
2019 This is the physical address in your flash memory the kernel will
2020 be linked for and stored to. This address is dependent on your
2024 bool "Kexec system call (EXPERIMENTAL)"
2025 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2027 kexec is a system call that implements the ability to shutdown your
2028 current kernel, and to start another kernel. It is like a reboot
2029 but it is independent of the system firmware. And like a reboot
2030 you can start any kernel with it, not just Linux.
2032 It is an ongoing process to be certain the hardware in a machine
2033 is properly shutdown, so do not be surprised if this code does not
2034 initially work for you. It may help to enable device hotplugging
2038 bool "Export atags in procfs"
2042 Should the atags used to boot the kernel be exported in an "atags"
2043 file in procfs. Useful with kexec.
2046 bool "Build kdump crash kernel (EXPERIMENTAL)"
2047 depends on EXPERIMENTAL
2049 Generate crash dump after being started by kexec. This should
2050 be normally only set in special crash dump kernels which are
2051 loaded in the main kernel with kexec-tools into a specially
2052 reserved region and then later executed after a crash by
2053 kdump/kexec. The crash dump kernel must be compiled to a
2054 memory address not used by the main kernel
2056 For more details see Documentation/kdump/kdump.txt
2058 config AUTO_ZRELADDR
2059 bool "Auto calculation of the decompressed kernel image address"
2060 depends on !ZBOOT_ROM && !ARCH_U300
2062 ZRELADDR is the physical address where the decompressed kernel
2063 image will be placed. If AUTO_ZRELADDR is selected, the address
2064 will be determined at run-time by masking the current IP with
2065 0xf8000000. This assumes the zImage being placed in the first 128MB
2066 from start of memory.
2070 menu "CPU Power Management"
2074 source "drivers/cpufreq/Kconfig"
2077 tristate "CPUfreq driver for i.MX CPUs"
2078 depends on ARCH_MXC && CPU_FREQ
2080 This enables the CPUfreq driver for i.MX CPUs.
2082 config CPU_FREQ_SA1100
2085 config CPU_FREQ_SA1110
2088 config CPU_FREQ_INTEGRATOR
2089 tristate "CPUfreq driver for ARM Integrator CPUs"
2090 depends on ARCH_INTEGRATOR && CPU_FREQ
2093 This enables the CPUfreq driver for ARM Integrator CPUs.
2095 For details, take a look at <file:Documentation/cpu-freq>.
2101 depends on CPU_FREQ && ARCH_PXA && PXA25x
2103 select CPU_FREQ_TABLE
2104 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2109 Internal configuration node for common cpufreq on Samsung SoC
2111 config CPU_FREQ_S3C24XX
2112 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2113 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2116 This enables the CPUfreq driver for the Samsung S3C24XX family
2119 For details, take a look at <file:Documentation/cpu-freq>.
2123 config CPU_FREQ_S3C24XX_PLL
2124 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2125 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2127 Compile in support for changing the PLL frequency from the
2128 S3C24XX series CPUfreq driver. The PLL takes time to settle
2129 after a frequency change, so by default it is not enabled.
2131 This also means that the PLL tables for the selected CPU(s) will
2132 be built which may increase the size of the kernel image.
2134 config CPU_FREQ_S3C24XX_DEBUG
2135 bool "Debug CPUfreq Samsung driver core"
2136 depends on CPU_FREQ_S3C24XX
2138 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2140 config CPU_FREQ_S3C24XX_IODEBUG
2141 bool "Debug CPUfreq Samsung driver IO timing"
2142 depends on CPU_FREQ_S3C24XX
2144 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2146 config CPU_FREQ_S3C24XX_DEBUGFS
2147 bool "Export debugfs for CPUFreq"
2148 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2150 Export status information via debugfs.
2154 source "drivers/cpuidle/Kconfig"
2158 menu "Floating point emulation"
2160 comment "At least one emulation must be selected"
2163 bool "NWFPE math emulation"
2164 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2166 Say Y to include the NWFPE floating point emulator in the kernel.
2167 This is necessary to run most binaries. Linux does not currently
2168 support floating point hardware so you need to say Y here even if
2169 your machine has an FPA or floating point co-processor podule.
2171 You may say N here if you are going to load the Acorn FPEmulator
2172 early in the bootup.
2175 bool "Support extended precision"
2176 depends on FPE_NWFPE
2178 Say Y to include 80-bit support in the kernel floating-point
2179 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2180 Note that gcc does not generate 80-bit operations by default,
2181 so in most cases this option only enlarges the size of the
2182 floating point emulator without any good reason.
2184 You almost surely want to say N here.
2187 bool "FastFPE math emulation (EXPERIMENTAL)"
2188 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2190 Say Y here to include the FAST floating point emulator in the kernel.
2191 This is an experimental much faster emulator which now also has full
2192 precision for the mantissa. It does not support any exceptions.
2193 It is very simple, and approximately 3-6 times faster than NWFPE.
2195 It should be sufficient for most programs. It may be not suitable
2196 for scientific calculations, but you have to check this for yourself.
2197 If you do not feel you need a faster FP emulation you should better
2201 bool "VFP-format floating point maths"
2202 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2204 Say Y to include VFP support code in the kernel. This is needed
2205 if your hardware includes a VFP unit.
2207 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2208 release notes and additional status information.
2210 Say N if your target does not have VFP hardware.
2218 bool "Advanced SIMD (NEON) Extension support"
2219 depends on VFPv3 && CPU_V7
2221 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2226 menu "Userspace binary formats"
2228 source "fs/Kconfig.binfmt"
2231 tristate "RISC OS personality"
2234 Say Y here to include the kernel code necessary if you want to run
2235 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2236 experimental; if this sounds frightening, say N and sleep in peace.
2237 You can also say M here to compile this support as a module (which
2238 will be called arthur).
2242 menu "Power management options"
2244 source "kernel/power/Kconfig"
2246 config ARCH_SUSPEND_POSSIBLE
2247 depends on !ARCH_S5PC100
2248 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2249 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2252 config ARM_CPU_SUSPEND
2257 source "net/Kconfig"
2259 source "drivers/Kconfig"
2263 source "arch/arm/Kconfig.debug"
2265 source "security/Kconfig"
2267 source "crypto/Kconfig"
2269 source "lib/Kconfig"