1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
17 be loaded to and run from that address. This option lifts that
18 restriction, thus allowing the code to be loaded to and executed from
19 almost any 4K aligned address. This logic relies on the relocation
20 information that is embedded in the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
23 config INIT_SP_RELATIVE
24 bool "Specify the early stack pointer relative to the .bss section"
25 default n if ARCH_QEMU
26 default y if POSITION_INDEPENDENT
28 U-Boot typically uses a hard-coded value for the stack pointer
29 before relocation. Enable this option to instead calculate the
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that it can be loaded and executed at arbitrary
32 addresses and thus avoid using arbitrary addresses at runtime.
34 If this option is enabled, the early stack pointer is set to
35 &_bss_start with a offset value added. The offset is specified by
36 SYS_INIT_SP_BSS_OFFSET.
38 config SYS_INIT_SP_BSS_OFFSET
39 int "Early stack offset from the .bss base address"
40 depends on INIT_SP_RELATIVE
43 This option's value is the offset added to &_bss_start in order to
44 calculate the stack pointer. This offset should be large enough so
45 that the early malloc region, global data (gd), and early stack usage
46 do not overlap any appended DTB.
48 config LINUX_KERNEL_IMAGE_HEADER
51 Place a Linux kernel image header at the start of the U-Boot binary.
52 The format of the header is described in the Linux kernel source at
53 Documentation/arm64/booting.txt. This feature is useful since the
54 image header reports the amount of memory (BSS and similar) that
55 U-Boot needs to use, but which isn't part of the binary.
57 if LINUX_KERNEL_IMAGE_HEADER
58 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
61 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
62 TEXT_OFFSET value written to the Linux kernel image header.
71 ARM GICV3 Interrupt translation service (ITS).
72 Basic support for programming locality specific peripheral
73 interrupts (LPI) configuration tables and enable LPI tables.
74 LPI configuration table can be used by u-boot or Linux.
75 ARM GICV3 has limitation, once the LPI table is enabled, LPI
76 configuration table can not be re-programmed, unless GICV3 reset.
82 config DMA_ADDR_T_64BIT
92 # Used for compatibility with asm files copied from the kernel
93 config ARM_ASM_UNIFIED
97 # Used for compatibility with asm files copied from the kernel
101 config SYS_ICACHE_OFF
102 bool "Do not enable icache"
105 Do not enable instruction cache in U-Boot.
107 config SPL_SYS_ICACHE_OFF
108 bool "Do not enable icache in SPL"
110 default SYS_ICACHE_OFF
112 Do not enable instruction cache in SPL.
114 config SYS_DCACHE_OFF
115 bool "Do not enable dcache"
118 Do not enable data cache in U-Boot.
120 config SPL_SYS_DCACHE_OFF
121 bool "Do not enable dcache in SPL"
123 default SYS_DCACHE_OFF
125 Do not enable data cache in SPL.
127 config SYS_ARM_CACHE_CP15
128 bool "CP15 based cache enabling support"
130 Select this if your processor suports enabling caches by using
134 bool "MMU-based Paged Memory Management Support"
135 select SYS_ARM_CACHE_CP15
137 Select if you want MMU-based virtualised addressing space
138 support via paged memory management.
141 bool 'Use the ARM v7 PMSA Compliant MPU'
143 Some ARM systems without an MMU have instead a Memory Protection
144 Unit (MPU) that defines the type and permissions for regions of
146 If your CPU has an MPU then you should choose 'y' here unless you
147 know that you do not want to use the MPU.
149 # If set, the workarounds for these ARM errata are applied early during U-Boot
150 # startup. Note that in general these options force the workarounds to be
151 # applied; no CPU-type/version detection exists, unlike the similar options in
152 # the Linux kernel. Do not set these options unless they apply! Also note that
153 # the following can be machine-specific errata. These do have ability to
154 # provide rudimentary version and machine-specific checks, but expect no
156 # CONFIG_ARM_ERRATA_430973
157 # CONFIG_ARM_ERRATA_454179
158 # CONFIG_ARM_ERRATA_621766
159 # CONFIG_ARM_ERRATA_798870
160 # CONFIG_ARM_ERRATA_801819
161 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
162 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
164 config ARM_ERRATA_430973
167 config ARM_ERRATA_454179
170 config ARM_ERRATA_621766
173 config ARM_ERRATA_716044
176 config ARM_ERRATA_725233
179 config ARM_ERRATA_742230
182 config ARM_ERRATA_743622
185 config ARM_ERRATA_751472
188 config ARM_ERRATA_761320
191 config ARM_ERRATA_773022
194 config ARM_ERRATA_774769
197 config ARM_ERRATA_794072
200 config ARM_ERRATA_798870
203 config ARM_ERRATA_801819
206 config ARM_ERRATA_826974
209 config ARM_ERRATA_828024
212 config ARM_ERRATA_829520
215 config ARM_ERRATA_833069
218 config ARM_ERRATA_833471
221 config ARM_ERRATA_845369
224 config ARM_ERRATA_852421
227 config ARM_ERRATA_852423
230 config ARM_ERRATA_855873
233 config ARM_CORTEX_A8_CVE_2017_5715
236 config ARM_CORTEX_A15_CVE_2017_5715
241 select SYS_CACHE_SHIFT_5
246 select SYS_CACHE_SHIFT_5
251 select SYS_CACHE_SHIFT_5
256 select SYS_CACHE_SHIFT_5
261 select SYS_CACHE_SHIFT_5
267 select SYS_CACHE_SHIFT_5
274 select SYS_CACHE_SHIFT_6
281 select SYS_CACHE_SHIFT_5
282 select SYS_THUMB_BUILD
288 select SYS_ARM_CACHE_CP15
290 select SYS_CACHE_SHIFT_6
294 select SYS_CACHE_SHIFT_5
299 select SYS_CACHE_SHIFT_5
303 default "arm720t" if CPU_ARM720T
304 default "arm920t" if CPU_ARM920T
305 default "arm926ejs" if CPU_ARM926EJS
306 default "arm946es" if CPU_ARM946ES
307 default "arm1136" if CPU_ARM1136
308 default "arm1176" if CPU_ARM1176
309 default "armv7" if CPU_V7A
310 default "armv7" if CPU_V7R
311 default "armv7m" if CPU_V7M
312 default "pxa" if CPU_PXA
313 default "sa1100" if CPU_SA1100
314 default "armv8" if ARM64
318 default 4 if CPU_ARM720T
319 default 4 if CPU_ARM920T
320 default 5 if CPU_ARM926EJS
321 default 5 if CPU_ARM946ES
322 default 6 if CPU_ARM1136
323 default 6 if CPU_ARM1176
328 default 4 if CPU_SA1100
331 config SYS_CACHE_SHIFT_5
334 config SYS_CACHE_SHIFT_6
337 config SYS_CACHE_SHIFT_7
340 config SYS_CACHELINE_SIZE
342 default 128 if SYS_CACHE_SHIFT_7
343 default 64 if SYS_CACHE_SHIFT_6
344 default 32 if SYS_CACHE_SHIFT_5
347 prompt "Select the ARM data write cache policy"
348 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
349 TARGET_BCMNSP || CPU_PXA || RZA1
350 default SYS_ARM_CACHE_WRITEBACK
352 config SYS_ARM_CACHE_WRITEBACK
353 bool "Write-back (WB)"
355 A write updates the cache only and marks the cache line as dirty.
356 External memory is updated only when the line is evicted or explicitly
359 config SYS_ARM_CACHE_WRITETHROUGH
360 bool "Write-through (WT)"
362 A write updates both the cache and the external memory system.
363 This does not mark the cache line as dirty.
365 config SYS_ARM_CACHE_WRITEALLOC
366 bool "Write allocation (WA)"
368 A cache line is allocated on a write miss. This means that executing a
369 store instruction on the processor might cause a burst read to occur.
370 There is a linefill to obtain the data for the cache line, before the
375 bool "Enable ARCH_CPU_INIT"
377 Some architectures require a call to arch_cpu_init().
378 Say Y here to enable it
380 config SYS_ARCH_TIMER
381 bool "ARM Generic Timer support"
382 depends on CPU_V7A || ARM64
385 The ARM Generic Timer (aka arch-timer) provides an architected
386 interface to a timer source on an SoC.
387 It is mandatory for ARMv8 implementation and widely available
391 bool "Support for ARM SMC Calling Convention (SMCCC)"
392 depends on CPU_V7A || ARM64
395 Say Y here if you want to enable ARM SMC Calling Convention.
396 This should be enabled if U-Boot needs to communicate with system
397 firmware (for example, PSCI) according to SMCCC.
400 bool "support boot from semihosting"
402 In emulated environments, semihosting is a way for
403 the hosted environment to call out to the emulator to
404 retrieve files from the host machine.
406 config SYS_THUMB_BUILD
407 bool "Build U-Boot using the Thumb instruction set"
410 Use this flag to build U-Boot using the Thumb instruction set for
411 ARM architectures. Thumb instruction set provides better code
412 density. For ARM architectures that support Thumb2 this flag will
413 result in Thumb2 code generated by GCC.
415 config SPL_SYS_THUMB_BUILD
416 bool "Build SPL using the Thumb instruction set"
417 default y if SYS_THUMB_BUILD
418 depends on !ARM64 && SPL
420 Use this flag to build SPL using the Thumb instruction set for
421 ARM architectures. Thumb instruction set provides better code
422 density. For ARM architectures that support Thumb2 this flag will
423 result in Thumb2 code generated by GCC.
425 config TPL_SYS_THUMB_BUILD
426 bool "Build TPL using the Thumb instruction set"
427 default y if SYS_THUMB_BUILD
428 depends on TPL && !ARM64
430 Use this flag to build TPL using the Thumb instruction set for
431 ARM architectures. Thumb instruction set provides better code
432 density. For ARM architectures that support Thumb2 this flag will
433 result in Thumb2 code generated by GCC.
436 config SYS_L2CACHE_OFF
439 If SoC does not support L2CACHE or one does not want to enable
440 L2CACHE, choose this option.
442 config ENABLE_ARM_SOC_BOOT0_HOOK
443 bool "prepare BOOT0 header"
445 If the SoC's BOOT0 requires a header area filled with (magic)
446 values, then choose this option, and create a file included as
447 <asm/arch/boot0.h> which contains the required assembler code.
449 config ARM_CORTEX_CPU_IS_UP
453 config USE_ARCH_MEMCPY
454 bool "Use an assembly optimized implementation of memcpy"
458 Enable the generation of an optimized version of memcpy.
459 Such an implementation may be faster under some conditions
460 but may increase the binary size.
462 config SPL_USE_ARCH_MEMCPY
463 bool "Use an assembly optimized implementation of memcpy for SPL"
464 default y if USE_ARCH_MEMCPY
465 depends on !ARM64 && SPL
467 Enable the generation of an optimized version of memcpy.
468 Such an implementation may be faster under some conditions
469 but may increase the binary size.
471 config TPL_USE_ARCH_MEMCPY
472 bool "Use an assembly optimized implementation of memcpy for TPL"
473 default y if USE_ARCH_MEMCPY
474 depends on !ARM64 && TPL
476 Enable the generation of an optimized version of memcpy.
477 Such an implementation may be faster under some conditions
478 but may increase the binary size.
480 config USE_ARCH_MEMSET
481 bool "Use an assembly optimized implementation of memset"
485 Enable the generation of an optimized version of memset.
486 Such an implementation may be faster under some conditions
487 but may increase the binary size.
489 config SPL_USE_ARCH_MEMSET
490 bool "Use an assembly optimized implementation of memset for SPL"
491 default y if USE_ARCH_MEMSET
492 depends on !ARM64 && SPL
494 Enable the generation of an optimized version of memset.
495 Such an implementation may be faster under some conditions
496 but may increase the binary size.
498 config TPL_USE_ARCH_MEMSET
499 bool "Use an assembly optimized implementation of memset for TPL"
500 default y if USE_ARCH_MEMSET
501 depends on !ARM64 && TPL
503 Enable the generation of an optimized version of memset.
504 Such an implementation may be faster under some conditions
505 but may increase the binary size.
507 config ARM64_SUPPORT_AARCH32
508 bool "ARM64 system support AArch32 execution state"
510 default y if !TARGET_THUNDERX_88XX
512 This ARM64 system supports AArch32 execution state.
515 prompt "Target select"
520 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
521 select SPL_SEPARATE_BSS if SPL
523 config TARGET_EDB93XX
524 bool "Support edb93xx"
528 config TARGET_ASPENITE
529 bool "Support aspenite"
533 bool "Support gplugd"
539 select SPL_DM_SPI if SPL
542 Support for TI's DaVinci platform.
545 bool "Marvell Kirkwood"
546 select ARCH_MISC_INIT
547 select BOARD_EARLY_INIT_F
551 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
557 select SPL_DM_SPI if SPL
558 select SPL_DM_SPI_FLASH if SPL
568 config TARGET_SPEAR300
569 bool "Support spear300"
570 select BOARD_EARLY_INIT_F
575 config TARGET_SPEAR310
576 bool "Support spear310"
577 select BOARD_EARLY_INIT_F
582 config TARGET_SPEAR320
583 bool "Support spear320"
584 select BOARD_EARLY_INIT_F
589 config TARGET_SPEAR600
590 bool "Support spear600"
591 select BOARD_EARLY_INIT_F
596 config TARGET_STV0991
597 bool "Support stv0991"
610 select BOARD_LATE_INIT
620 bool "Broadcom BCM283X family"
626 select SERIAL_SEARCH_ALL
631 bool "Broadcom BCM63158 family"
637 bool "Broadcom BCM68360 family"
643 bool "Broadcom BCM6858 family"
649 bool "Broadcom BCM7XXX family"
653 select OF_PRIOR_STAGE
656 This enables support for Broadcom ARM-based set-top box
657 chipsets, including the 7445 family of chips.
659 config TARGET_BCM23550_W1D
660 bool "Support bcm23550_w1d"
665 config TARGET_BCMCYGNUS
666 bool "Support bcmcygnus"
669 imply BCM_SF2_ETH_GMAC
677 bool "Support bcmnsp"
681 bool "Support Broadcom Northstar2"
684 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
685 ARMv8 Cortex-A57 processors targeting a broad range of networking
689 bool "Support Broadcom NS3"
691 select BOARD_LATE_INIT
693 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
694 ARMv8 Cortex-A72 processors targeting a broad range of networking
698 bool "Samsung EXYNOS"
707 imply SYS_THUMB_BUILD
712 bool "Samsung S5PC1XX"
721 bool "Calxeda Highbank"
725 config ARCH_INTEGRATOR
726 bool "ARM Ltd. Integrator family"
733 bool "Qualcomm IPQ40xx SoCs"
751 select SYS_ARCH_TIMER
752 select SYS_THUMB_BUILD
758 bool "Texas Instruments' K3 Architecture"
763 config ARCH_OMAP2PLUS
766 select SPL_BOARD_INIT if SPL
767 select SPL_STACK_R if SPL
769 imply TI_SYSC if DM && OF_CONTROL
774 imply DISTRO_DEFAULTS
777 Support for the Meson SoC family developed by Amlogic Inc.,
778 targeted at media players and tablet computers. We currently
779 support the S905 (GXBaby) 64-bit SoC.
786 select SPL_LIBCOMMON_SUPPORT if SPL
787 select SPL_LIBGENERIC_SUPPORT if SPL
788 select SPL_OF_CONTROL if SPL
791 Support for the MediaTek SoCs family developed by MediaTek Inc.
792 Please refer to doc/README.mediatek for more information.
795 bool "NXP LPC32xx platform"
805 bool "NXP i.MX8 platform"
809 select ENABLE_ARM_SOC_BOOT0_HOOK
812 bool "NXP i.MX8M platform"
814 select SYS_FSL_HAS_SEC if IMX_HAB
815 select SYS_FSL_SEC_COMPAT_4
816 select SYS_FSL_SEC_LE
822 bool "NXP i.MXRT platform"
830 bool "NXP i.MX23 family"
841 bool "NXP i.MX28 family"
847 bool "NXP i.MX31 family"
853 select SYS_FSL_HAS_SEC if IMX_HAB
854 select SYS_FSL_SEC_COMPAT_4
855 select SYS_FSL_SEC_LE
856 select ROM_UNIFIED_SECTIONS
858 imply SYS_THUMB_BUILD
862 select ARCH_MISC_INIT
864 select SYS_FSL_HAS_SEC if IMX_HAB
865 select SYS_FSL_SEC_COMPAT_4
866 select SYS_FSL_SEC_LE
867 imply BOARD_EARLY_INIT_F
869 imply SYS_THUMB_BUILD
874 select SYS_FSL_HAS_SEC
875 select SYS_FSL_SEC_COMPAT_4
876 select SYS_FSL_SEC_LE
878 imply SYS_THUMB_BUILD
882 default "arch/arm/mach-omap2/u-boot-spl.lds"
887 select BOARD_EARLY_INIT_F
892 bool "Nexell S5P4418/S5P6818 SoC"
893 select ENABLE_ARM_SOC_BOOT0_HOOK
897 bool "Actions Semi OWL SoCs"
905 select SYS_RELOC_GD_ENV_ADDR
909 bool "QEMU Virtual Platform"
920 bool "Renesas ARM SoCs"
923 imply BOARD_EARLY_INIT_F
926 imply SYS_THUMB_BUILD
927 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
929 config ARCH_SNAPDRAGON
930 bool "Qualcomm Snapdragon SoCs"
943 bool "Altera SOCFPGA family"
944 select ARCH_EARLY_INIT_R
945 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
946 select ARM64 if TARGET_SOCFPGA_SOC64
947 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
950 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
952 select SPL_DM_RESET if DM_RESET
954 select SPL_LIBCOMMON_SUPPORT
955 select SPL_LIBGENERIC_SUPPORT
956 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
957 select SPL_OF_CONTROL
958 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
959 select SPL_SERIAL_SUPPORT
961 select SPL_WATCHDOG_SUPPORT
964 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
966 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
967 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
977 imply SPL_DM_SPI_FLASH
978 imply SPL_LIBDISK_SUPPORT
979 imply SPL_MMC_SUPPORT
980 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
981 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
982 imply SPL_SPI_FLASH_SUPPORT
983 imply SPL_SPI_SUPPORT
987 bool "Support sunxi (Allwinner) SoCs"
990 select CMD_MMC if MMC
991 select CMD_USB if DISTRO_DEFAULTS
998 select DM_SCSI if SCSI
1000 select DM_USB if DISTRO_DEFAULTS
1001 select OF_BOARD_SETUP
1004 select SPECIFY_CONSOLE_INDEX
1005 select SPL_STACK_R if SPL
1006 select SPL_SYS_MALLOC_SIMPLE if SPL
1007 select SPL_SYS_THUMB_BUILD if !ARM64
1010 select SYS_THUMB_BUILD if !ARM64
1011 select USB if DISTRO_DEFAULTS
1012 select USB_KEYBOARD if DISTRO_DEFAULTS
1013 select USB_STORAGE if DISTRO_DEFAULTS
1014 select SPL_USE_TINY_PRINTF
1016 select SYS_RELOC_GD_ENV_ADDR
1017 imply BOARD_LATE_INIT
1020 imply CMD_UBI if MTD_RAW_NAND
1021 imply DISTRO_DEFAULTS
1024 imply OF_LIBFDT_OVERLAY
1025 imply PRE_CONSOLE_BUFFER
1026 imply SPL_GPIO_SUPPORT
1027 imply SPL_LIBCOMMON_SUPPORT
1028 imply SPL_LIBGENERIC_SUPPORT
1029 imply SPL_MMC_SUPPORT if MMC
1030 imply SPL_POWER_SUPPORT
1031 imply SPL_SERIAL_SUPPORT
1035 bool "ST-Ericsson U8500 Series"
1039 select DM_MMC if MMC
1041 select DM_USB if USB
1045 imply ARM_PL180_MMCI
1047 imply NOMADIK_MTU_TIMER
1050 imply SYSRESET_SYSCON
1053 bool "Support Xilinx Versal Platform"
1057 select DM_ETH if NET
1058 select DM_MMC if MMC
1061 imply BOARD_LATE_INIT
1062 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1065 bool "Freescale Vybrid"
1067 select SYS_FSL_ERRATUM_ESDHC111
1072 bool "Xilinx Zynq based platform"
1077 select DM_ETH if NET
1078 select DM_MMC if MMC
1082 select DM_USB if USB
1085 select SPL_BOARD_INIT if SPL
1086 select SPL_CLK if SPL
1087 select SPL_DM if SPL
1088 select SPL_DM_SPI if SPL
1089 select SPL_DM_SPI_FLASH if SPL
1090 select SPL_OF_CONTROL if SPL
1091 select SPL_SEPARATE_BSS if SPL
1093 imply ARCH_EARLY_INIT_R
1094 imply BOARD_LATE_INIT
1098 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1101 config ARCH_ZYNQMP_R5
1102 bool "Xilinx ZynqMP R5 based platform"
1106 select DM_ETH if NET
1107 select DM_MMC if MMC
1114 bool "Xilinx ZynqMP based platform"
1118 select DM_ETH if NET
1120 select DM_MMC if MMC
1122 select DM_SPI if SPI
1123 select DM_SPI_FLASH if DM_SPI
1124 select DM_USB if USB
1127 select SPL_BOARD_INIT if SPL
1128 select SPL_CLK if SPL
1129 select SPL_DM if SPL
1130 select SPL_DM_SPI if SPI && SPL_DM
1131 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1132 select SPL_DM_MAILBOX if SPL
1133 select SPL_FIRMWARE if SPL
1134 select SPL_SEPARATE_BSS if SPL
1137 imply BOARD_LATE_INIT
1139 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1146 imply DISTRO_DEFAULTS
1149 config TARGET_VEXPRESS64_AEMV8A
1150 bool "Support vexpress_aemv8a"
1154 config TARGET_VEXPRESS64_BASE_FVP
1155 bool "Support Versatile Express ARMv8a FVP BASE model"
1160 config TARGET_VEXPRESS64_JUNO
1161 bool "Support Versatile Express Juno Development Platform"
1176 config TARGET_TOTAL_COMPUTE
1177 bool "Support Total Compute Platform"
1185 config TARGET_LS2080A_EMU
1186 bool "Support ls2080a_emu"
1189 select ARMV8_MULTIENTRY
1190 select FSL_DDR_SYNC_REFRESH
1192 Support for Freescale LS2080A_EMU platform.
1193 The LS2080A Development System (EMULATOR) is a pre-silicon
1194 development platform that supports the QorIQ LS2080A
1195 Layerscape Architecture processor.
1197 config TARGET_LS1088AQDS
1198 bool "Support ls1088aqds"
1201 select ARMV8_MULTIENTRY
1202 select ARCH_SUPPORT_TFABOOT
1203 select BOARD_LATE_INIT
1205 select FSL_DDR_INTERACTIVE if !SD_BOOT
1207 Support for NXP LS1088AQDS platform.
1208 The LS1088A Development System (QDS) is a high-performance
1209 development platform that supports the QorIQ LS1088A
1210 Layerscape Architecture processor.
1212 config TARGET_LS2080AQDS
1213 bool "Support ls2080aqds"
1216 select ARMV8_MULTIENTRY
1217 select ARCH_SUPPORT_TFABOOT
1218 select BOARD_LATE_INIT
1223 select FSL_DDR_INTERACTIVE if !SPL
1225 Support for Freescale LS2080AQDS platform.
1226 The LS2080A Development System (QDS) is a high-performance
1227 development platform that supports the QorIQ LS2080A
1228 Layerscape Architecture processor.
1230 config TARGET_LS2080ARDB
1231 bool "Support ls2080ardb"
1234 select ARMV8_MULTIENTRY
1235 select ARCH_SUPPORT_TFABOOT
1236 select BOARD_LATE_INIT
1239 select FSL_DDR_INTERACTIVE if !SPL
1243 Support for Freescale LS2080ARDB platform.
1244 The LS2080A Reference design board (RDB) is a high-performance
1245 development platform that supports the QorIQ LS2080A
1246 Layerscape Architecture processor.
1248 config TARGET_LS2081ARDB
1249 bool "Support ls2081ardb"
1252 select ARMV8_MULTIENTRY
1253 select BOARD_LATE_INIT
1256 Support for Freescale LS2081ARDB platform.
1257 The LS2081A Reference design board (RDB) is a high-performance
1258 development platform that supports the QorIQ LS2081A/LS2041A
1259 Layerscape Architecture processor.
1261 config TARGET_LX2160ARDB
1262 bool "Support lx2160ardb"
1265 select ARMV8_MULTIENTRY
1266 select ARCH_SUPPORT_TFABOOT
1267 select BOARD_LATE_INIT
1269 Support for NXP LX2160ARDB platform.
1270 The lx2160ardb (LX2160A Reference design board (RDB)
1271 is a high-performance development platform that supports the
1272 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1274 config TARGET_LX2160AQDS
1275 bool "Support lx2160aqds"
1278 select ARMV8_MULTIENTRY
1279 select ARCH_SUPPORT_TFABOOT
1280 select BOARD_LATE_INIT
1282 Support for NXP LX2160AQDS platform.
1283 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1284 is a high-performance development platform that supports the
1285 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1287 config TARGET_LX2162AQDS
1288 bool "Support lx2162aqds"
1290 select ARCH_MISC_INIT
1292 select ARMV8_MULTIENTRY
1293 select ARCH_SUPPORT_TFABOOT
1294 select BOARD_LATE_INIT
1296 Support for NXP LX2162AQDS platform.
1297 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1300 bool "Support HiKey 96boards Consumer Edition Platform"
1307 select SPECIFY_CONSOLE_INDEX
1310 Support for HiKey 96boards platform. It features a HI6220
1311 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1313 config TARGET_HIKEY960
1314 bool "Support HiKey960 96boards Consumer Edition Platform"
1322 Support for HiKey960 96boards platform. It features a HI3660
1323 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1325 config TARGET_POPLAR
1326 bool "Support Poplar 96boards Enterprise Edition Platform"
1335 Support for Poplar 96boards EE platform. It features a HI3798cv200
1336 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1337 making it capable of running any commercial set-top solution based on
1340 config TARGET_LS1012AQDS
1341 bool "Support ls1012aqds"
1344 select ARCH_SUPPORT_TFABOOT
1345 select BOARD_LATE_INIT
1347 Support for Freescale LS1012AQDS platform.
1348 The LS1012A Development System (QDS) is a high-performance
1349 development platform that supports the QorIQ LS1012A
1350 Layerscape Architecture processor.
1352 config TARGET_LS1012ARDB
1353 bool "Support ls1012ardb"
1356 select ARCH_SUPPORT_TFABOOT
1357 select BOARD_LATE_INIT
1361 Support for Freescale LS1012ARDB platform.
1362 The LS1012A Reference design board (RDB) is a high-performance
1363 development platform that supports the QorIQ LS1012A
1364 Layerscape Architecture processor.
1366 config TARGET_LS1012A2G5RDB
1367 bool "Support ls1012a2g5rdb"
1370 select ARCH_SUPPORT_TFABOOT
1371 select BOARD_LATE_INIT
1374 Support for Freescale LS1012A2G5RDB platform.
1375 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1376 development platform that supports the QorIQ LS1012A
1377 Layerscape Architecture processor.
1379 config TARGET_LS1012AFRWY
1380 bool "Support ls1012afrwy"
1383 select ARCH_SUPPORT_TFABOOT
1384 select BOARD_LATE_INIT
1388 Support for Freescale LS1012AFRWY platform.
1389 The LS1012A FRWY board (FRWY) is a high-performance
1390 development platform that supports the QorIQ LS1012A
1391 Layerscape Architecture processor.
1393 config TARGET_LS1012AFRDM
1394 bool "Support ls1012afrdm"
1397 select ARCH_SUPPORT_TFABOOT
1399 Support for Freescale LS1012AFRDM platform.
1400 The LS1012A Freedom board (FRDM) is a high-performance
1401 development platform that supports the QorIQ LS1012A
1402 Layerscape Architecture processor.
1404 config TARGET_LS1028AQDS
1405 bool "Support ls1028aqds"
1408 select ARMV8_MULTIENTRY
1409 select ARCH_SUPPORT_TFABOOT
1410 select BOARD_LATE_INIT
1412 Support for Freescale LS1028AQDS platform
1413 The LS1028A Development System (QDS) is a high-performance
1414 development platform that supports the QorIQ LS1028A
1415 Layerscape Architecture processor.
1417 config TARGET_LS1028ARDB
1418 bool "Support ls1028ardb"
1421 select ARMV8_MULTIENTRY
1422 select ARCH_SUPPORT_TFABOOT
1423 select BOARD_LATE_INIT
1425 Support for Freescale LS1028ARDB platform
1426 The LS1028A Development System (RDB) is a high-performance
1427 development platform that supports the QorIQ LS1028A
1428 Layerscape Architecture processor.
1430 config TARGET_LS1088ARDB
1431 bool "Support ls1088ardb"
1434 select ARMV8_MULTIENTRY
1435 select ARCH_SUPPORT_TFABOOT
1436 select BOARD_LATE_INIT
1438 select FSL_DDR_INTERACTIVE if !SD_BOOT
1440 Support for NXP LS1088ARDB platform.
1441 The LS1088A Reference design board (RDB) is a high-performance
1442 development platform that supports the QorIQ LS1088A
1443 Layerscape Architecture processor.
1445 config TARGET_LS1021AQDS
1446 bool "Support ls1021aqds"
1448 select ARCH_SUPPORT_PSCI
1449 select BOARD_EARLY_INIT_F
1450 select BOARD_LATE_INIT
1452 select CPU_V7_HAS_NONSEC
1453 select CPU_V7_HAS_VIRT
1454 select LS1_DEEP_SLEEP
1457 select FSL_DDR_INTERACTIVE
1458 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1459 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1462 config TARGET_LS1021ATWR
1463 bool "Support ls1021atwr"
1465 select ARCH_SUPPORT_PSCI
1466 select BOARD_EARLY_INIT_F
1467 select BOARD_LATE_INIT
1469 select CPU_V7_HAS_NONSEC
1470 select CPU_V7_HAS_VIRT
1471 select LS1_DEEP_SLEEP
1473 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1476 config TARGET_LS1021ATSN
1477 bool "Support ls1021atsn"
1479 select ARCH_SUPPORT_PSCI
1480 select BOARD_EARLY_INIT_F
1481 select BOARD_LATE_INIT
1483 select CPU_V7_HAS_NONSEC
1484 select CPU_V7_HAS_VIRT
1485 select LS1_DEEP_SLEEP
1489 config TARGET_LS1021AIOT
1490 bool "Support ls1021aiot"
1492 select ARCH_SUPPORT_PSCI
1493 select BOARD_LATE_INIT
1495 select CPU_V7_HAS_NONSEC
1496 select CPU_V7_HAS_VIRT
1498 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1501 Support for Freescale LS1021AIOT platform.
1502 The LS1021A Freescale board (IOT) is a high-performance
1503 development platform that supports the QorIQ LS1021A
1504 Layerscape Architecture processor.
1506 config TARGET_LS1043AQDS
1507 bool "Support ls1043aqds"
1510 select ARMV8_MULTIENTRY
1511 select ARCH_SUPPORT_TFABOOT
1512 select BOARD_EARLY_INIT_F
1513 select BOARD_LATE_INIT
1515 select FSL_DDR_INTERACTIVE if !SPL
1516 select FSL_DSPI if !SPL_NO_DSPI
1517 select DM_SPI_FLASH if FSL_DSPI
1521 Support for Freescale LS1043AQDS platform.
1523 config TARGET_LS1043ARDB
1524 bool "Support ls1043ardb"
1527 select ARMV8_MULTIENTRY
1528 select ARCH_SUPPORT_TFABOOT
1529 select BOARD_EARLY_INIT_F
1530 select BOARD_LATE_INIT
1532 select FSL_DSPI if !SPL_NO_DSPI
1533 select DM_SPI_FLASH if FSL_DSPI
1535 Support for Freescale LS1043ARDB platform.
1537 config TARGET_LS1046AQDS
1538 bool "Support ls1046aqds"
1541 select ARMV8_MULTIENTRY
1542 select ARCH_SUPPORT_TFABOOT
1543 select BOARD_EARLY_INIT_F
1544 select BOARD_LATE_INIT
1545 select DM_SPI_FLASH if DM_SPI
1547 select FSL_DDR_BIST if !SPL
1548 select FSL_DDR_INTERACTIVE if !SPL
1549 select FSL_DDR_INTERACTIVE if !SPL
1552 Support for Freescale LS1046AQDS platform.
1553 The LS1046A Development System (QDS) is a high-performance
1554 development platform that supports the QorIQ LS1046A
1555 Layerscape Architecture processor.
1557 config TARGET_LS1046ARDB
1558 bool "Support ls1046ardb"
1561 select ARMV8_MULTIENTRY
1562 select ARCH_SUPPORT_TFABOOT
1563 select BOARD_EARLY_INIT_F
1564 select BOARD_LATE_INIT
1565 select DM_SPI_FLASH if DM_SPI
1566 select POWER_MC34VR500
1569 select FSL_DDR_INTERACTIVE if !SPL
1572 Support for Freescale LS1046ARDB platform.
1573 The LS1046A Reference Design Board (RDB) is a high-performance
1574 development platform that supports the QorIQ LS1046A
1575 Layerscape Architecture processor.
1577 config TARGET_LS1046AFRWY
1578 bool "Support ls1046afrwy"
1581 select ARMV8_MULTIENTRY
1582 select ARCH_SUPPORT_TFABOOT
1583 select BOARD_EARLY_INIT_F
1584 select BOARD_LATE_INIT
1585 select DM_SPI_FLASH if DM_SPI
1588 Support for Freescale LS1046AFRWY platform.
1589 The LS1046A Freeway Board (FRWY) is a high-performance
1590 development platform that supports the QorIQ LS1046A
1591 Layerscape Architecture processor.
1597 select ARMV8_MULTIENTRY
1601 Support for Kontron SMARC-sAL28 board.
1603 config TARGET_COLIBRI_PXA270
1604 bool "Support colibri_pxa270"
1607 config ARCH_UNIPHIER
1608 bool "Socionext UniPhier SoCs"
1609 select BOARD_LATE_INIT
1619 select OF_BOARD_SETUP
1623 select SPL_BOARD_INIT if SPL
1624 select SPL_DM if SPL
1625 select SPL_LIBCOMMON_SUPPORT if SPL
1626 select SPL_LIBGENERIC_SUPPORT if SPL
1627 select SPL_OF_CONTROL if SPL
1628 select SPL_PINCTRL if SPL
1631 imply DISTRO_DEFAULTS
1634 Support for UniPhier SoC family developed by Socionext Inc.
1635 (formerly, System LSI Business Division of Panasonic Corporation)
1638 bool "Support STMicroelectronics STM32 MCU with cortex M"
1645 bool "Support STMicrolectronics SoCs"
1654 Support for STMicroelectronics STiH407/10 SoC family.
1655 This SoC is used on Linaro 96Board STiH410-B2260
1658 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1659 select ARCH_MISC_INIT
1660 select ARCH_SUPPORT_TFABOOT
1661 select BOARD_LATE_INIT
1670 select OF_SYSTEM_SETUP
1676 select SYS_THUMB_BUILD
1680 imply OF_LIBFDT_OVERLAY
1681 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1684 Support for STM32MP SoC family developed by STMicroelectronics,
1685 MPUs based on ARM cortex A core
1686 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1687 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1689 SPL is the unsecure FSBL for the basic boot chain.
1691 config ARCH_ROCKCHIP
1692 bool "Support Rockchip SoCs"
1694 select BINMAN if SPL_OPTEE
1704 select DM_USB if USB
1705 select ENABLE_ARM_SOC_BOOT0_HOOK
1708 select SPL_DM if SPL
1709 select SPL_DM_SPI if SPL
1710 select SPL_DM_SPI_FLASH if SPL
1712 select SYS_THUMB_BUILD if !ARM64
1715 imply DEBUG_UART_BOARD_INIT
1716 imply DISTRO_DEFAULTS
1718 imply SARADC_ROCKCHIP
1720 imply SPL_SYS_MALLOC_SIMPLE
1723 imply USB_FUNCTION_FASTBOOT
1725 config ARCH_OCTEONTX
1726 bool "Support OcteonTX SoCs"
1732 select BOARD_LATE_INIT
1733 select SYS_CACHE_SHIFT_7
1735 config ARCH_OCTEONTX2
1736 bool "Support OcteonTX2 SoCs"
1742 select BOARD_LATE_INIT
1743 select SYS_CACHE_SHIFT_7
1745 config TARGET_THUNDERX_88XX
1746 bool "Support ThunderX 88xx"
1750 select SYS_CACHE_SHIFT_7
1753 bool "Support Aspeed SoCs"
1758 config TARGET_DURIAN
1759 bool "Support Phytium Durian Platform"
1762 Support for durian platform.
1763 It has 2GB Sdram, uart and pcie.
1765 config TARGET_PRESIDIO_ASIC
1766 bool "Support Cortina Presidio ASIC Platform"
1769 config TARGET_XENGUEST_ARM64
1770 bool "Xen guest ARM64"
1774 select LINUX_KERNEL_IMAGE_HEADER
1779 config ARCH_SUPPORT_TFABOOT
1783 bool "Support for booting from TF-A"
1784 depends on ARCH_SUPPORT_TFABOOT
1787 Some platforms support the setup of secure registers (for instance
1788 for CPU errata handling) or provide secure services like PSCI.
1789 Those services could also be provided by other firmware parts
1790 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
1791 does not need to (and cannot) execute this code.
1792 Enabling this option will make a U-Boot binary that is relying
1793 on other firmware layers to provide secure functionality.
1795 config TI_SECURE_DEVICE
1796 bool "HS Device Type Support"
1797 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1799 If a high secure (HS) device type is being used, this config
1800 must be set. This option impacts various aspects of the
1801 build system (to create signed boot images that can be
1802 authenticated) and the code. See the doc/README.ti-secure
1803 file for further details.
1805 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1806 config ISW_ENTRY_ADDR
1807 hex "Address in memory or XIP address of bootloader entry point"
1808 default 0x402F4000 if AM43XX
1809 default 0x402F0400 if AM33XX
1810 default 0x40301350 if OMAP54XX
1812 After any reset, the boot ROM searches the boot media for a valid
1813 boot image. For non-XIP devices, the ROM then copies the image into
1814 internal memory. For all boot modes, after the ROM processes the
1815 boot image it eventually computes the entry point address depending
1816 on the device type (secure/non-secure), boot media (xip/non-xip) and
1820 source "arch/arm/mach-aspeed/Kconfig"
1822 source "arch/arm/mach-at91/Kconfig"
1824 source "arch/arm/mach-bcm283x/Kconfig"
1826 source "arch/arm/mach-bcmstb/Kconfig"
1828 source "arch/arm/mach-davinci/Kconfig"
1830 source "arch/arm/mach-exynos/Kconfig"
1832 source "arch/arm/mach-highbank/Kconfig"
1834 source "arch/arm/mach-integrator/Kconfig"
1836 source "arch/arm/mach-ipq40xx/Kconfig"
1838 source "arch/arm/mach-k3/Kconfig"
1840 source "arch/arm/mach-keystone/Kconfig"
1842 source "arch/arm/mach-kirkwood/Kconfig"
1844 source "arch/arm/mach-lpc32xx/Kconfig"
1846 source "arch/arm/mach-mvebu/Kconfig"
1848 source "arch/arm/mach-octeontx/Kconfig"
1850 source "arch/arm/mach-octeontx2/Kconfig"
1852 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1854 source "arch/arm/mach-imx/mx2/Kconfig"
1856 source "arch/arm/mach-imx/mx3/Kconfig"
1858 source "arch/arm/mach-imx/mx5/Kconfig"
1860 source "arch/arm/mach-imx/mx6/Kconfig"
1862 source "arch/arm/mach-imx/mx7/Kconfig"
1864 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1866 source "arch/arm/mach-imx/imx8/Kconfig"
1868 source "arch/arm/mach-imx/imx8m/Kconfig"
1870 source "arch/arm/mach-imx/imxrt/Kconfig"
1872 source "arch/arm/mach-imx/mxs/Kconfig"
1874 source "arch/arm/mach-omap2/Kconfig"
1876 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1878 source "arch/arm/mach-orion5x/Kconfig"
1880 source "arch/arm/mach-owl/Kconfig"
1882 source "arch/arm/mach-rmobile/Kconfig"
1884 source "arch/arm/mach-meson/Kconfig"
1886 source "arch/arm/mach-mediatek/Kconfig"
1888 source "arch/arm/mach-qemu/Kconfig"
1890 source "arch/arm/mach-rockchip/Kconfig"
1892 source "arch/arm/mach-s5pc1xx/Kconfig"
1894 source "arch/arm/mach-snapdragon/Kconfig"
1896 source "arch/arm/mach-socfpga/Kconfig"
1898 source "arch/arm/mach-sti/Kconfig"
1900 source "arch/arm/mach-stm32/Kconfig"
1902 source "arch/arm/mach-stm32mp/Kconfig"
1904 source "arch/arm/mach-sunxi/Kconfig"
1906 source "arch/arm/mach-tegra/Kconfig"
1908 source "arch/arm/mach-u8500/Kconfig"
1910 source "arch/arm/mach-uniphier/Kconfig"
1912 source "arch/arm/cpu/armv7/vf610/Kconfig"
1914 source "arch/arm/mach-zynq/Kconfig"
1916 source "arch/arm/mach-zynqmp/Kconfig"
1918 source "arch/arm/mach-versal/Kconfig"
1920 source "arch/arm/mach-zynqmp-r5/Kconfig"
1922 source "arch/arm/cpu/armv7/Kconfig"
1924 source "arch/arm/cpu/armv8/Kconfig"
1926 source "arch/arm/mach-imx/Kconfig"
1928 source "arch/arm/mach-nexell/Kconfig"
1930 source "board/armltd/total_compute/Kconfig"
1932 source "board/bosch/shc/Kconfig"
1933 source "board/bosch/guardian/Kconfig"
1934 source "board/CarMediaLab/flea3/Kconfig"
1935 source "board/Marvell/aspenite/Kconfig"
1936 source "board/Marvell/gplugd/Kconfig"
1937 source "board/Marvell/octeontx/Kconfig"
1938 source "board/Marvell/octeontx2/Kconfig"
1939 source "board/armltd/vexpress64/Kconfig"
1940 source "board/cortina/presidio-asic/Kconfig"
1941 source "board/broadcom/bcm23550_w1d/Kconfig"
1942 source "board/broadcom/bcm963158/Kconfig"
1943 source "board/broadcom/bcm968360bg/Kconfig"
1944 source "board/broadcom/bcm968580xref/Kconfig"
1945 source "board/broadcom/bcmcygnus/Kconfig"
1946 source "board/broadcom/bcmnsp/Kconfig"
1947 source "board/broadcom/bcmns3/Kconfig"
1948 source "board/cavium/thunderx/Kconfig"
1949 source "board/cirrus/edb93xx/Kconfig"
1950 source "board/eets/pdu001/Kconfig"
1951 source "board/emulation/qemu-arm/Kconfig"
1952 source "board/freescale/ls2080aqds/Kconfig"
1953 source "board/freescale/ls2080ardb/Kconfig"
1954 source "board/freescale/ls1088a/Kconfig"
1955 source "board/freescale/ls1028a/Kconfig"
1956 source "board/freescale/ls1021aqds/Kconfig"
1957 source "board/freescale/ls1043aqds/Kconfig"
1958 source "board/freescale/ls1021atwr/Kconfig"
1959 source "board/freescale/ls1021atsn/Kconfig"
1960 source "board/freescale/ls1021aiot/Kconfig"
1961 source "board/freescale/ls1046aqds/Kconfig"
1962 source "board/freescale/ls1043ardb/Kconfig"
1963 source "board/freescale/ls1046ardb/Kconfig"
1964 source "board/freescale/ls1046afrwy/Kconfig"
1965 source "board/freescale/ls1012aqds/Kconfig"
1966 source "board/freescale/ls1012ardb/Kconfig"
1967 source "board/freescale/ls1012afrdm/Kconfig"
1968 source "board/freescale/lx2160a/Kconfig"
1969 source "board/grinn/chiliboard/Kconfig"
1970 source "board/hisilicon/hikey/Kconfig"
1971 source "board/hisilicon/hikey960/Kconfig"
1972 source "board/hisilicon/poplar/Kconfig"
1973 source "board/isee/igep003x/Kconfig"
1974 source "board/kontron/sl28/Kconfig"
1975 source "board/myir/mys_6ulx/Kconfig"
1976 source "board/spear/spear300/Kconfig"
1977 source "board/spear/spear310/Kconfig"
1978 source "board/spear/spear320/Kconfig"
1979 source "board/spear/spear600/Kconfig"
1980 source "board/spear/x600/Kconfig"
1981 source "board/st/stv0991/Kconfig"
1982 source "board/tcl/sl50/Kconfig"
1983 source "board/toradex/colibri_pxa270/Kconfig"
1984 source "board/variscite/dart_6ul/Kconfig"
1985 source "board/vscom/baltos/Kconfig"
1986 source "board/phytium/durian/Kconfig"
1987 source "board/xen/xenguest_arm64/Kconfig"
1989 source "arch/arm/Kconfig.debug"
1994 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
1995 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
1996 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64