1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
17 be loaded to and run from that address. This option lifts that
18 restriction, thus allowing the code to be loaded to and executed from
19 almost any 4K aligned address. This logic relies on the relocation
20 information that is embedded in the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
23 config INIT_SP_RELATIVE
24 bool "Specify the early stack pointer relative to the .bss section"
25 default n if ARCH_QEMU
26 default y if POSITION_INDEPENDENT
28 U-Boot typically uses a hard-coded value for the stack pointer
29 before relocation. Enable this option to instead calculate the
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that it can be loaded and executed at arbitrary
32 addresses and thus avoid using arbitrary addresses at runtime.
34 If this option is enabled, the early stack pointer is set to
35 &_bss_start with a offset value added. The offset is specified by
36 SYS_INIT_SP_BSS_OFFSET.
38 config SYS_INIT_SP_BSS_OFFSET
39 int "Early stack offset from the .bss base address"
40 depends on INIT_SP_RELATIVE
43 This option's value is the offset added to &_bss_start in order to
44 calculate the stack pointer. This offset should be large enough so
45 that the early malloc region, global data (gd), and early stack usage
46 do not overlap any appended DTB.
48 config LINUX_KERNEL_IMAGE_HEADER
51 Place a Linux kernel image header at the start of the U-Boot binary.
52 The format of the header is described in the Linux kernel source at
53 Documentation/arm64/booting.txt. This feature is useful since the
54 image header reports the amount of memory (BSS and similar) that
55 U-Boot needs to use, but which isn't part of the binary.
57 if LINUX_KERNEL_IMAGE_HEADER
58 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
61 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
62 TEXT_OFFSET value written to the Linux kernel image header.
72 ARM GICV3 Interrupt translation service (ITS).
73 Basic support for programming locality specific peripheral
74 interrupts (LPI) configuration tables and enable LPI tables.
75 LPI configuration table can be used by u-boot or Linux.
76 ARM GICV3 has limitation, once the LPI table is enabled, LPI
77 configuration table can not be re-programmed, unless GICV3 reset.
83 config DMA_ADDR_T_64BIT
93 config GPIO_EXTRA_HEADER
96 # Used for compatibility with asm files copied from the kernel
97 config ARM_ASM_UNIFIED
101 # Used for compatibility with asm files copied from the kernel
105 config SYS_ICACHE_OFF
106 bool "Do not enable icache"
109 Do not enable instruction cache in U-Boot.
111 config SPL_SYS_ICACHE_OFF
112 bool "Do not enable icache in SPL"
114 default SYS_ICACHE_OFF
116 Do not enable instruction cache in SPL.
118 config SYS_DCACHE_OFF
119 bool "Do not enable dcache"
122 Do not enable data cache in U-Boot.
124 config SPL_SYS_DCACHE_OFF
125 bool "Do not enable dcache in SPL"
127 default SYS_DCACHE_OFF
129 Do not enable data cache in SPL.
131 config SYS_ARM_CACHE_CP15
132 bool "CP15 based cache enabling support"
134 Select this if your processor suports enabling caches by using
138 bool "MMU-based Paged Memory Management Support"
139 select SYS_ARM_CACHE_CP15
141 Select if you want MMU-based virtualised addressing space
142 support via paged memory management.
145 bool 'Use the ARM v7 PMSA Compliant MPU'
147 Some ARM systems without an MMU have instead a Memory Protection
148 Unit (MPU) that defines the type and permissions for regions of
150 If your CPU has an MPU then you should choose 'y' here unless you
151 know that you do not want to use the MPU.
153 # If set, the workarounds for these ARM errata are applied early during U-Boot
154 # startup. Note that in general these options force the workarounds to be
155 # applied; no CPU-type/version detection exists, unlike the similar options in
156 # the Linux kernel. Do not set these options unless they apply! Also note that
157 # the following can be machine-specific errata. These do have ability to
158 # provide rudimentary version and machine-specific checks, but expect no
160 # CONFIG_ARM_ERRATA_430973
161 # CONFIG_ARM_ERRATA_454179
162 # CONFIG_ARM_ERRATA_621766
163 # CONFIG_ARM_ERRATA_798870
164 # CONFIG_ARM_ERRATA_801819
165 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
166 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
168 config ARM_ERRATA_430973
171 config ARM_ERRATA_454179
174 config ARM_ERRATA_621766
177 config ARM_ERRATA_716044
180 config ARM_ERRATA_725233
183 config ARM_ERRATA_742230
186 config ARM_ERRATA_743622
189 config ARM_ERRATA_751472
192 config ARM_ERRATA_761320
195 config ARM_ERRATA_773022
198 config ARM_ERRATA_774769
201 config ARM_ERRATA_794072
204 config ARM_ERRATA_798870
207 config ARM_ERRATA_801819
210 config ARM_ERRATA_826974
213 config ARM_ERRATA_828024
216 config ARM_ERRATA_829520
219 config ARM_ERRATA_833069
222 config ARM_ERRATA_833471
225 config ARM_ERRATA_845369
228 config ARM_ERRATA_852421
231 config ARM_ERRATA_852423
234 config ARM_ERRATA_855873
237 config ARM_CORTEX_A8_CVE_2017_5715
240 config ARM_CORTEX_A15_CVE_2017_5715
245 select SYS_CACHE_SHIFT_5
250 select SYS_CACHE_SHIFT_5
255 select SYS_CACHE_SHIFT_5
260 select SYS_CACHE_SHIFT_5
265 select SYS_CACHE_SHIFT_5
271 select SYS_CACHE_SHIFT_5
278 select SYS_CACHE_SHIFT_6
285 select SYS_CACHE_SHIFT_5
286 select SYS_THUMB_BUILD
292 select SYS_ARM_CACHE_CP15
294 select SYS_CACHE_SHIFT_6
298 select SYS_CACHE_SHIFT_5
303 select SYS_CACHE_SHIFT_5
307 default "arm720t" if CPU_ARM720T
308 default "arm920t" if CPU_ARM920T
309 default "arm926ejs" if CPU_ARM926EJS
310 default "arm946es" if CPU_ARM946ES
311 default "arm1136" if CPU_ARM1136
312 default "arm1176" if CPU_ARM1176
313 default "armv7" if CPU_V7A
314 default "armv7" if CPU_V7R
315 default "armv7m" if CPU_V7M
316 default "pxa" if CPU_PXA
317 default "sa1100" if CPU_SA1100
318 default "armv8" if ARM64
322 default 4 if CPU_ARM720T
323 default 4 if CPU_ARM920T
324 default 5 if CPU_ARM926EJS
325 default 5 if CPU_ARM946ES
326 default 6 if CPU_ARM1136
327 default 6 if CPU_ARM1176
332 default 4 if CPU_SA1100
335 config SYS_CACHE_SHIFT_5
338 config SYS_CACHE_SHIFT_6
341 config SYS_CACHE_SHIFT_7
344 config SYS_CACHELINE_SIZE
346 default 128 if SYS_CACHE_SHIFT_7
347 default 64 if SYS_CACHE_SHIFT_6
348 default 32 if SYS_CACHE_SHIFT_5
351 prompt "Select the ARM data write cache policy"
352 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
354 default SYS_ARM_CACHE_WRITEBACK
356 config SYS_ARM_CACHE_WRITEBACK
357 bool "Write-back (WB)"
359 A write updates the cache only and marks the cache line as dirty.
360 External memory is updated only when the line is evicted or explicitly
363 config SYS_ARM_CACHE_WRITETHROUGH
364 bool "Write-through (WT)"
366 A write updates both the cache and the external memory system.
367 This does not mark the cache line as dirty.
369 config SYS_ARM_CACHE_WRITEALLOC
370 bool "Write allocation (WA)"
372 A cache line is allocated on a write miss. This means that executing a
373 store instruction on the processor might cause a burst read to occur.
374 There is a linefill to obtain the data for the cache line, before the
379 bool "Enable ARCH_CPU_INIT"
381 Some architectures require a call to arch_cpu_init().
382 Say Y here to enable it
384 config SYS_ARCH_TIMER
385 bool "ARM Generic Timer support"
386 depends on CPU_V7A || ARM64
389 The ARM Generic Timer (aka arch-timer) provides an architected
390 interface to a timer source on an SoC.
391 It is mandatory for ARMv8 implementation and widely available
395 bool "Support for ARM SMC Calling Convention (SMCCC)"
396 depends on CPU_V7A || ARM64
399 Say Y here if you want to enable ARM SMC Calling Convention.
400 This should be enabled if U-Boot needs to communicate with system
401 firmware (for example, PSCI) according to SMCCC.
404 bool "support boot from semihosting"
406 In emulated environments, semihosting is a way for
407 the hosted environment to call out to the emulator to
408 retrieve files from the host machine.
410 config SYS_THUMB_BUILD
411 bool "Build U-Boot using the Thumb instruction set"
414 Use this flag to build U-Boot using the Thumb instruction set for
415 ARM architectures. Thumb instruction set provides better code
416 density. For ARM architectures that support Thumb2 this flag will
417 result in Thumb2 code generated by GCC.
419 config SPL_SYS_THUMB_BUILD
420 bool "Build SPL using the Thumb instruction set"
421 default y if SYS_THUMB_BUILD
422 depends on !ARM64 && SPL
424 Use this flag to build SPL using the Thumb instruction set for
425 ARM architectures. Thumb instruction set provides better code
426 density. For ARM architectures that support Thumb2 this flag will
427 result in Thumb2 code generated by GCC.
429 config TPL_SYS_THUMB_BUILD
430 bool "Build TPL using the Thumb instruction set"
431 default y if SYS_THUMB_BUILD
432 depends on TPL && !ARM64
434 Use this flag to build TPL using the Thumb instruction set for
435 ARM architectures. Thumb instruction set provides better code
436 density. For ARM architectures that support Thumb2 this flag will
437 result in Thumb2 code generated by GCC.
440 config SYS_L2CACHE_OFF
443 If SoC does not support L2CACHE or one does not want to enable
444 L2CACHE, choose this option.
446 config ENABLE_ARM_SOC_BOOT0_HOOK
447 bool "prepare BOOT0 header"
449 If the SoC's BOOT0 requires a header area filled with (magic)
450 values, then choose this option, and create a file included as
451 <asm/arch/boot0.h> which contains the required assembler code.
453 config ARM_CORTEX_CPU_IS_UP
457 config USE_ARCH_MEMCPY
458 bool "Use an assembly optimized implementation of memcpy"
462 Enable the generation of an optimized version of memcpy.
463 Such an implementation may be faster under some conditions
464 but may increase the binary size.
466 config SPL_USE_ARCH_MEMCPY
467 bool "Use an assembly optimized implementation of memcpy for SPL"
468 default y if USE_ARCH_MEMCPY
469 depends on !ARM64 && SPL
471 Enable the generation of an optimized version of memcpy.
472 Such an implementation may be faster under some conditions
473 but may increase the binary size.
475 config TPL_USE_ARCH_MEMCPY
476 bool "Use an assembly optimized implementation of memcpy for TPL"
477 default y if USE_ARCH_MEMCPY
478 depends on !ARM64 && TPL
480 Enable the generation of an optimized version of memcpy.
481 Such an implementation may be faster under some conditions
482 but may increase the binary size.
484 config USE_ARCH_MEMSET
485 bool "Use an assembly optimized implementation of memset"
489 Enable the generation of an optimized version of memset.
490 Such an implementation may be faster under some conditions
491 but may increase the binary size.
493 config SPL_USE_ARCH_MEMSET
494 bool "Use an assembly optimized implementation of memset for SPL"
495 default y if USE_ARCH_MEMSET
496 depends on !ARM64 && SPL
498 Enable the generation of an optimized version of memset.
499 Such an implementation may be faster under some conditions
500 but may increase the binary size.
502 config TPL_USE_ARCH_MEMSET
503 bool "Use an assembly optimized implementation of memset for TPL"
504 default y if USE_ARCH_MEMSET
505 depends on !ARM64 && TPL
507 Enable the generation of an optimized version of memset.
508 Such an implementation may be faster under some conditions
509 but may increase the binary size.
511 config ARM64_SUPPORT_AARCH32
512 bool "ARM64 system support AArch32 execution state"
514 default y if !TARGET_THUNDERX_88XX
516 This ARM64 system supports AArch32 execution state.
519 prompt "Target select"
524 select GPIO_EXTRA_HEADER
525 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
526 select SPL_SEPARATE_BSS if SPL
528 config TARGET_ASPENITE
529 bool "Support aspenite"
531 select GPIO_EXTRA_HEADER
536 select GPIO_EXTRA_HEADER
537 select SPL_DM_SPI if SPL
540 Support for TI's DaVinci platform.
543 bool "Marvell Kirkwood"
544 select ARCH_MISC_INIT
545 select BOARD_EARLY_INIT_F
547 select GPIO_EXTRA_HEADER
550 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
556 select GPIO_EXTRA_HEADER
557 select SPL_DM_SPI if SPL
558 select SPL_DM_SPI_FLASH if SPL
567 select GPIO_EXTRA_HEADER
569 config TARGET_SPEAR310
570 bool "Support spear310"
571 select BOARD_EARLY_INIT_F
573 select GPIO_EXTRA_HEADER
577 config TARGET_SPEAR320
578 bool "Support spear320"
579 select BOARD_EARLY_INIT_F
581 select GPIO_EXTRA_HEADER
585 config TARGET_SPEAR600
586 bool "Support spear600"
587 select BOARD_EARLY_INIT_F
589 select GPIO_EXTRA_HEADER
593 config TARGET_STV0991
594 bool "Support stv0991"
600 select GPIO_EXTRA_HEADER
608 select BOARD_LATE_INIT
610 select GPIO_EXTRA_HEADER
617 select GPIO_EXTRA_HEADER
620 bool "Broadcom BCM283X family"
624 select GPIO_EXTRA_HEADER
627 select SERIAL_SEARCH_ALL
632 bool "Broadcom BCM63158 family"
638 bool "Broadcom BCM68360 family"
644 bool "Broadcom BCM6858 family"
650 bool "Broadcom BCM7XXX family"
653 select GPIO_EXTRA_HEADER
655 select OF_PRIOR_STAGE
658 This enables support for Broadcom ARM-based set-top box
659 chipsets, including the 7445 family of chips.
661 config TARGET_BCMCYGNUS
662 bool "Support bcmcygnus"
664 select GPIO_EXTRA_HEADER
666 imply BCM_SF2_ETH_GMAC
674 bool "Support Broadcom Northstar2"
676 select GPIO_EXTRA_HEADER
678 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
679 ARMv8 Cortex-A57 processors targeting a broad range of networking
683 bool "Support Broadcom NS3"
685 select BOARD_LATE_INIT
687 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
688 ARMv8 Cortex-A72 processors targeting a broad range of networking
692 bool "Samsung EXYNOS"
701 select GPIO_EXTRA_HEADER
702 imply SYS_THUMB_BUILD
707 bool "Samsung S5PC1XX"
713 select GPIO_EXTRA_HEADER
717 bool "Calxeda Highbank"
730 config ARCH_INTEGRATOR
731 bool "ARM Ltd. Integrator family"
734 select GPIO_EXTRA_HEADER
739 bool "Qualcomm IPQ40xx SoCs"
745 select GPIO_EXTRA_HEADER
757 select GPIO_EXTRA_HEADER
759 select SYS_ARCH_TIMER
760 select SYS_THUMB_BUILD
766 bool "Texas Instruments' K3 Architecture"
771 config ARCH_OMAP2PLUS
774 select GPIO_EXTRA_HEADER
775 select SPL_BOARD_INIT if SPL
776 select SPL_STACK_R if SPL
778 imply TI_SYSC if DM && OF_CONTROL
783 select GPIO_EXTRA_HEADER
784 imply DISTRO_DEFAULTS
787 Support for the Meson SoC family developed by Amlogic Inc.,
788 targeted at media players and tablet computers. We currently
789 support the S905 (GXBaby) 64-bit SoC.
794 select GPIO_EXTRA_HEADER
797 select SPL_LIBCOMMON_SUPPORT if SPL
798 select SPL_LIBGENERIC_SUPPORT if SPL
799 select SPL_OF_CONTROL if SPL
802 Support for the MediaTek SoCs family developed by MediaTek Inc.
803 Please refer to doc/README.mediatek for more information.
806 bool "NXP LPC32xx platform"
811 select GPIO_EXTRA_HEADER
817 bool "NXP i.MX8 platform"
820 select GPIO_EXTRA_HEADER
822 select ENABLE_ARM_SOC_BOOT0_HOOK
825 bool "NXP i.MX8M platform"
827 select GPIO_EXTRA_HEADER
828 select SYS_FSL_HAS_SEC if IMX_HAB
829 select SYS_FSL_SEC_COMPAT_4
830 select SYS_FSL_SEC_LE
836 bool "NXP i.MXRT platform"
840 select GPIO_EXTRA_HEADER
845 bool "NXP i.MX23 family"
847 select GPIO_EXTRA_HEADER
854 select GPIO_EXTRA_HEADER
858 bool "NXP i.MX28 family"
860 select GPIO_EXTRA_HEADER
865 bool "NXP i.MX31 family"
867 select GPIO_EXTRA_HEADER
872 select GPIO_EXTRA_HEADER
873 select SYS_FSL_HAS_SEC if IMX_HAB
874 select SYS_FSL_SEC_COMPAT_4
875 select SYS_FSL_SEC_LE
876 select ROM_UNIFIED_SECTIONS
878 imply SYS_THUMB_BUILD
882 select ARCH_MISC_INIT
884 select GPIO_EXTRA_HEADER
885 select SYS_FSL_HAS_SEC if IMX_HAB
886 select SYS_FSL_SEC_COMPAT_4
887 select SYS_FSL_SEC_LE
888 imply BOARD_EARLY_INIT_F
890 imply SYS_THUMB_BUILD
895 select GPIO_EXTRA_HEADER
896 select SYS_FSL_HAS_SEC
897 select SYS_FSL_SEC_COMPAT_4
898 select SYS_FSL_SEC_LE
900 imply SYS_THUMB_BUILD
904 default "arch/arm/mach-omap2/u-boot-spl.lds"
909 select BOARD_EARLY_INIT_F
911 select GPIO_EXTRA_HEADER
915 bool "Nexell S5P4418/S5P6818 SoC"
916 select ENABLE_ARM_SOC_BOOT0_HOOK
918 select GPIO_EXTRA_HEADER
921 bool "Actions Semi OWL SoCs"
925 select GPIO_EXTRA_HEADER
930 select SYS_RELOC_GD_ENV_ADDR
934 bool "QEMU Virtual Platform"
945 bool "Renesas ARM SoCs"
948 select GPIO_EXTRA_HEADER
949 imply BOARD_EARLY_INIT_F
952 imply SYS_THUMB_BUILD
953 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
955 config ARCH_SNAPDRAGON
956 bool "Qualcomm Snapdragon SoCs"
961 select GPIO_EXTRA_HEADER
970 bool "Altera SOCFPGA family"
971 select ARCH_EARLY_INIT_R
972 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
973 select ARM64 if TARGET_SOCFPGA_SOC64
974 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
977 select GPIO_EXTRA_HEADER
978 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
980 select SPL_DM_RESET if DM_RESET
982 select SPL_LIBCOMMON_SUPPORT
983 select SPL_LIBGENERIC_SUPPORT
984 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
985 select SPL_OF_CONTROL
986 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
987 select SPL_SERIAL_SUPPORT
989 select SPL_WATCHDOG_SUPPORT
992 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
994 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
995 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1005 imply SPL_DM_SPI_FLASH
1006 imply SPL_LIBDISK_SUPPORT
1007 imply SPL_MMC_SUPPORT
1008 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1009 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1010 imply SPL_SPI_FLASH_SUPPORT
1011 imply SPL_SPI_SUPPORT
1015 bool "Support sunxi (Allwinner) SoCs"
1018 select CMD_MMC if MMC
1019 select CMD_USB if DISTRO_DEFAULTS
1025 select DM_MMC if MMC
1026 select DM_SCSI if SCSI
1028 select DM_USB if DISTRO_DEFAULTS
1029 select GPIO_EXTRA_HEADER
1030 select OF_BOARD_SETUP
1033 select SPECIFY_CONSOLE_INDEX
1034 select SPL_STACK_R if SPL
1035 select SPL_SYS_MALLOC_SIMPLE if SPL
1036 select SPL_SYS_THUMB_BUILD if !ARM64
1039 select SYS_THUMB_BUILD if !ARM64
1040 select USB if DISTRO_DEFAULTS
1041 select USB_KEYBOARD if DISTRO_DEFAULTS
1042 select USB_STORAGE if DISTRO_DEFAULTS
1043 select SPL_USE_TINY_PRINTF
1045 select SYS_RELOC_GD_ENV_ADDR
1046 imply BOARD_LATE_INIT
1049 imply CMD_UBI if MTD_RAW_NAND
1050 imply DISTRO_DEFAULTS
1053 imply OF_LIBFDT_OVERLAY
1054 imply PRE_CONSOLE_BUFFER
1055 imply SPL_GPIO_SUPPORT
1056 imply SPL_LIBCOMMON_SUPPORT
1057 imply SPL_LIBGENERIC_SUPPORT
1058 imply SPL_MMC_SUPPORT if MMC
1059 imply SPL_POWER_SUPPORT
1060 imply SPL_SERIAL_SUPPORT
1064 bool "ST-Ericsson U8500 Series"
1068 select DM_MMC if MMC
1070 select DM_USB if USB
1074 imply ARM_PL180_MMCI
1076 imply NOMADIK_MTU_TIMER
1079 imply SYSRESET_SYSCON
1082 bool "Support Xilinx Versal Platform"
1086 select DM_ETH if NET
1087 select DM_MMC if MMC
1089 select GPIO_EXTRA_HEADER
1091 imply BOARD_LATE_INIT
1092 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1095 bool "Freescale Vybrid"
1097 select GPIO_EXTRA_HEADER
1098 select SYS_FSL_ERRATUM_ESDHC111
1103 bool "Xilinx Zynq based platform"
1108 select DM_ETH if NET
1109 select DM_MMC if MMC
1113 select DM_USB if USB
1114 select GPIO_EXTRA_HEADER
1117 select SPL_BOARD_INIT if SPL
1118 select SPL_CLK if SPL
1119 select SPL_DM if SPL
1120 select SPL_DM_SPI if SPL
1121 select SPL_DM_SPI_FLASH if SPL
1122 select SPL_OF_CONTROL if SPL
1123 select SPL_SEPARATE_BSS if SPL
1125 imply ARCH_EARLY_INIT_R
1126 imply BOARD_LATE_INIT
1130 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1133 config ARCH_ZYNQMP_R5
1134 bool "Xilinx ZynqMP R5 based platform"
1138 select DM_ETH if NET
1139 select DM_MMC if MMC
1141 select GPIO_EXTRA_HEADER
1147 bool "Xilinx ZynqMP based platform"
1151 select DM_ETH if NET
1153 select DM_MMC if MMC
1155 select DM_SPI if SPI
1156 select DM_SPI_FLASH if DM_SPI
1157 select DM_USB if USB
1159 select GPIO_EXTRA_HEADER
1161 select SPL_BOARD_INIT if SPL
1162 select SPL_CLK if SPL
1163 select SPL_DM if SPL
1164 select SPL_DM_SPI if SPI && SPL_DM
1165 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1166 select SPL_DM_MAILBOX if SPL
1167 select SPL_FIRMWARE if SPL
1168 select SPL_SEPARATE_BSS if SPL
1171 imply BOARD_LATE_INIT
1173 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1180 select GPIO_EXTRA_HEADER
1181 imply DISTRO_DEFAULTS
1184 config TARGET_VEXPRESS64_AEMV8A
1185 bool "Support vexpress_aemv8a"
1187 select GPIO_EXTRA_HEADER
1190 config TARGET_VEXPRESS64_BASE_FVP
1191 bool "Support Versatile Express ARMv8a FVP BASE model"
1193 select GPIO_EXTRA_HEADER
1197 config TARGET_VEXPRESS64_JUNO
1198 bool "Support Versatile Express Juno Development Platform"
1200 select GPIO_EXTRA_HEADER
1214 config TARGET_TOTAL_COMPUTE
1215 bool "Support Total Compute Platform"
1223 config TARGET_LS2080A_EMU
1224 bool "Support ls2080a_emu"
1227 select ARMV8_MULTIENTRY
1228 select FSL_DDR_SYNC_REFRESH
1229 select GPIO_EXTRA_HEADER
1231 Support for Freescale LS2080A_EMU platform.
1232 The LS2080A Development System (EMULATOR) is a pre-silicon
1233 development platform that supports the QorIQ LS2080A
1234 Layerscape Architecture processor.
1236 config TARGET_LS1088AQDS
1237 bool "Support ls1088aqds"
1240 select ARMV8_MULTIENTRY
1241 select ARCH_SUPPORT_TFABOOT
1242 select BOARD_LATE_INIT
1243 select GPIO_EXTRA_HEADER
1245 select FSL_DDR_INTERACTIVE if !SD_BOOT
1247 Support for NXP LS1088AQDS platform.
1248 The LS1088A Development System (QDS) is a high-performance
1249 development platform that supports the QorIQ LS1088A
1250 Layerscape Architecture processor.
1252 config TARGET_LS2080AQDS
1253 bool "Support ls2080aqds"
1256 select ARMV8_MULTIENTRY
1257 select ARCH_SUPPORT_TFABOOT
1258 select BOARD_LATE_INIT
1259 select GPIO_EXTRA_HEADER
1264 select FSL_DDR_INTERACTIVE if !SPL
1266 Support for Freescale LS2080AQDS platform.
1267 The LS2080A Development System (QDS) is a high-performance
1268 development platform that supports the QorIQ LS2080A
1269 Layerscape Architecture processor.
1271 config TARGET_LS2080ARDB
1272 bool "Support ls2080ardb"
1275 select ARMV8_MULTIENTRY
1276 select ARCH_SUPPORT_TFABOOT
1277 select BOARD_LATE_INIT
1280 select FSL_DDR_INTERACTIVE if !SPL
1281 select GPIO_EXTRA_HEADER
1285 Support for Freescale LS2080ARDB platform.
1286 The LS2080A Reference design board (RDB) is a high-performance
1287 development platform that supports the QorIQ LS2080A
1288 Layerscape Architecture processor.
1290 config TARGET_LS2081ARDB
1291 bool "Support ls2081ardb"
1294 select ARMV8_MULTIENTRY
1295 select BOARD_LATE_INIT
1296 select GPIO_EXTRA_HEADER
1299 Support for Freescale LS2081ARDB platform.
1300 The LS2081A Reference design board (RDB) is a high-performance
1301 development platform that supports the QorIQ LS2081A/LS2041A
1302 Layerscape Architecture processor.
1304 config TARGET_LX2160ARDB
1305 bool "Support lx2160ardb"
1308 select ARMV8_MULTIENTRY
1309 select ARCH_SUPPORT_TFABOOT
1310 select BOARD_LATE_INIT
1311 select GPIO_EXTRA_HEADER
1313 Support for NXP LX2160ARDB platform.
1314 The lx2160ardb (LX2160A Reference design board (RDB)
1315 is a high-performance development platform that supports the
1316 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1318 config TARGET_LX2160AQDS
1319 bool "Support lx2160aqds"
1322 select ARMV8_MULTIENTRY
1323 select ARCH_SUPPORT_TFABOOT
1324 select BOARD_LATE_INIT
1325 select GPIO_EXTRA_HEADER
1327 Support for NXP LX2160AQDS platform.
1328 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1329 is a high-performance development platform that supports the
1330 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1332 config TARGET_LX2162AQDS
1333 bool "Support lx2162aqds"
1335 select ARCH_MISC_INIT
1337 select ARMV8_MULTIENTRY
1338 select ARCH_SUPPORT_TFABOOT
1339 select BOARD_LATE_INIT
1340 select GPIO_EXTRA_HEADER
1342 Support for NXP LX2162AQDS platform.
1343 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1346 bool "Support HiKey 96boards Consumer Edition Platform"
1351 select GPIO_EXTRA_HEADER
1354 select SPECIFY_CONSOLE_INDEX
1357 Support for HiKey 96boards platform. It features a HI6220
1358 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1360 config TARGET_HIKEY960
1361 bool "Support HiKey960 96boards Consumer Edition Platform"
1365 select GPIO_EXTRA_HEADER
1370 Support for HiKey960 96boards platform. It features a HI3660
1371 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1373 config TARGET_POPLAR
1374 bool "Support Poplar 96boards Enterprise Edition Platform"
1379 select GPIO_EXTRA_HEADER
1384 Support for Poplar 96boards EE platform. It features a HI3798cv200
1385 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1386 making it capable of running any commercial set-top solution based on
1389 config TARGET_LS1012AQDS
1390 bool "Support ls1012aqds"
1393 select ARCH_SUPPORT_TFABOOT
1394 select BOARD_LATE_INIT
1395 select GPIO_EXTRA_HEADER
1397 Support for Freescale LS1012AQDS platform.
1398 The LS1012A Development System (QDS) is a high-performance
1399 development platform that supports the QorIQ LS1012A
1400 Layerscape Architecture processor.
1402 config TARGET_LS1012ARDB
1403 bool "Support ls1012ardb"
1406 select ARCH_SUPPORT_TFABOOT
1407 select BOARD_LATE_INIT
1408 select GPIO_EXTRA_HEADER
1412 Support for Freescale LS1012ARDB platform.
1413 The LS1012A Reference design board (RDB) is a high-performance
1414 development platform that supports the QorIQ LS1012A
1415 Layerscape Architecture processor.
1417 config TARGET_LS1012A2G5RDB
1418 bool "Support ls1012a2g5rdb"
1421 select ARCH_SUPPORT_TFABOOT
1422 select BOARD_LATE_INIT
1423 select GPIO_EXTRA_HEADER
1426 Support for Freescale LS1012A2G5RDB platform.
1427 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1428 development platform that supports the QorIQ LS1012A
1429 Layerscape Architecture processor.
1431 config TARGET_LS1012AFRWY
1432 bool "Support ls1012afrwy"
1435 select ARCH_SUPPORT_TFABOOT
1436 select BOARD_LATE_INIT
1437 select GPIO_EXTRA_HEADER
1441 Support for Freescale LS1012AFRWY platform.
1442 The LS1012A FRWY board (FRWY) is a high-performance
1443 development platform that supports the QorIQ LS1012A
1444 Layerscape Architecture processor.
1446 config TARGET_LS1012AFRDM
1447 bool "Support ls1012afrdm"
1450 select ARCH_SUPPORT_TFABOOT
1451 select GPIO_EXTRA_HEADER
1453 Support for Freescale LS1012AFRDM platform.
1454 The LS1012A Freedom board (FRDM) is a high-performance
1455 development platform that supports the QorIQ LS1012A
1456 Layerscape Architecture processor.
1458 config TARGET_LS1028AQDS
1459 bool "Support ls1028aqds"
1462 select ARMV8_MULTIENTRY
1463 select ARCH_SUPPORT_TFABOOT
1464 select BOARD_LATE_INIT
1465 select GPIO_EXTRA_HEADER
1467 Support for Freescale LS1028AQDS platform
1468 The LS1028A Development System (QDS) is a high-performance
1469 development platform that supports the QorIQ LS1028A
1470 Layerscape Architecture processor.
1472 config TARGET_LS1028ARDB
1473 bool "Support ls1028ardb"
1476 select ARMV8_MULTIENTRY
1477 select ARCH_SUPPORT_TFABOOT
1478 select BOARD_LATE_INIT
1479 select GPIO_EXTRA_HEADER
1481 Support for Freescale LS1028ARDB platform
1482 The LS1028A Development System (RDB) is a high-performance
1483 development platform that supports the QorIQ LS1028A
1484 Layerscape Architecture processor.
1486 config TARGET_LS1088ARDB
1487 bool "Support ls1088ardb"
1490 select ARMV8_MULTIENTRY
1491 select ARCH_SUPPORT_TFABOOT
1492 select BOARD_LATE_INIT
1494 select FSL_DDR_INTERACTIVE if !SD_BOOT
1495 select GPIO_EXTRA_HEADER
1497 Support for NXP LS1088ARDB platform.
1498 The LS1088A Reference design board (RDB) is a high-performance
1499 development platform that supports the QorIQ LS1088A
1500 Layerscape Architecture processor.
1502 config TARGET_LS1021AQDS
1503 bool "Support ls1021aqds"
1505 select ARCH_SUPPORT_PSCI
1506 select BOARD_EARLY_INIT_F
1507 select BOARD_LATE_INIT
1509 select CPU_V7_HAS_NONSEC
1510 select CPU_V7_HAS_VIRT
1511 select LS1_DEEP_SLEEP
1514 select FSL_DDR_INTERACTIVE
1515 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1516 select GPIO_EXTRA_HEADER
1517 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1520 config TARGET_LS1021ATWR
1521 bool "Support ls1021atwr"
1523 select ARCH_SUPPORT_PSCI
1524 select BOARD_EARLY_INIT_F
1525 select BOARD_LATE_INIT
1527 select CPU_V7_HAS_NONSEC
1528 select CPU_V7_HAS_VIRT
1529 select LS1_DEEP_SLEEP
1531 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1532 select GPIO_EXTRA_HEADER
1535 config TARGET_PG_WCOM_SELI8
1536 bool "Support Hitachi-Powergrids SELI8 service unit card"
1538 select ARCH_SUPPORT_PSCI
1539 select BOARD_EARLY_INIT_F
1540 select BOARD_LATE_INIT
1542 select CPU_V7_HAS_NONSEC
1543 select CPU_V7_HAS_VIRT
1545 select FSL_DDR_INTERACTIVE
1546 select GPIO_EXTRA_HEADER
1550 Support for Hitachi-Powergrids SELI8 service unit card.
1551 SELI8 is a QorIQ LS1021a based service unit card used
1552 in XMC20 and FOX615 product families.
1554 config TARGET_PG_WCOM_EXPU1
1555 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1557 select ARCH_SUPPORT_PSCI
1558 select BOARD_EARLY_INIT_F
1559 select BOARD_LATE_INIT
1561 select CPU_V7_HAS_NONSEC
1562 select CPU_V7_HAS_VIRT
1564 select FSL_DDR_INTERACTIVE
1568 Support for Hitachi-Powergrids EXPU1 service unit card.
1569 EXPU1 is a QorIQ LS1021a based service unit card used
1570 in XMC20 and FOX615 product families.
1572 config TARGET_LS1021ATSN
1573 bool "Support ls1021atsn"
1575 select ARCH_SUPPORT_PSCI
1576 select BOARD_EARLY_INIT_F
1577 select BOARD_LATE_INIT
1579 select CPU_V7_HAS_NONSEC
1580 select CPU_V7_HAS_VIRT
1581 select LS1_DEEP_SLEEP
1583 select GPIO_EXTRA_HEADER
1586 config TARGET_LS1021AIOT
1587 bool "Support ls1021aiot"
1589 select ARCH_SUPPORT_PSCI
1590 select BOARD_LATE_INIT
1592 select CPU_V7_HAS_NONSEC
1593 select CPU_V7_HAS_VIRT
1595 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1596 select GPIO_EXTRA_HEADER
1599 Support for Freescale LS1021AIOT platform.
1600 The LS1021A Freescale board (IOT) is a high-performance
1601 development platform that supports the QorIQ LS1021A
1602 Layerscape Architecture processor.
1604 config TARGET_LS1043AQDS
1605 bool "Support ls1043aqds"
1608 select ARMV8_MULTIENTRY
1609 select ARCH_SUPPORT_TFABOOT
1610 select BOARD_EARLY_INIT_F
1611 select BOARD_LATE_INIT
1613 select FSL_DDR_INTERACTIVE if !SPL
1614 select FSL_DSPI if !SPL_NO_DSPI
1615 select DM_SPI_FLASH if FSL_DSPI
1616 select GPIO_EXTRA_HEADER
1620 Support for Freescale LS1043AQDS platform.
1622 config TARGET_LS1043ARDB
1623 bool "Support ls1043ardb"
1626 select ARMV8_MULTIENTRY
1627 select ARCH_SUPPORT_TFABOOT
1628 select BOARD_EARLY_INIT_F
1629 select BOARD_LATE_INIT
1631 select FSL_DSPI if !SPL_NO_DSPI
1632 select DM_SPI_FLASH if FSL_DSPI
1633 select GPIO_EXTRA_HEADER
1635 Support for Freescale LS1043ARDB platform.
1637 config TARGET_LS1046AQDS
1638 bool "Support ls1046aqds"
1641 select ARMV8_MULTIENTRY
1642 select ARCH_SUPPORT_TFABOOT
1643 select BOARD_EARLY_INIT_F
1644 select BOARD_LATE_INIT
1645 select DM_SPI_FLASH if DM_SPI
1647 select FSL_DDR_BIST if !SPL
1648 select FSL_DDR_INTERACTIVE if !SPL
1649 select FSL_DDR_INTERACTIVE if !SPL
1650 select GPIO_EXTRA_HEADER
1653 Support for Freescale LS1046AQDS platform.
1654 The LS1046A Development System (QDS) is a high-performance
1655 development platform that supports the QorIQ LS1046A
1656 Layerscape Architecture processor.
1658 config TARGET_LS1046ARDB
1659 bool "Support ls1046ardb"
1662 select ARMV8_MULTIENTRY
1663 select ARCH_SUPPORT_TFABOOT
1664 select BOARD_EARLY_INIT_F
1665 select BOARD_LATE_INIT
1666 select DM_SPI_FLASH if DM_SPI
1667 select POWER_MC34VR500
1670 select FSL_DDR_INTERACTIVE if !SPL
1671 select GPIO_EXTRA_HEADER
1674 Support for Freescale LS1046ARDB platform.
1675 The LS1046A Reference Design Board (RDB) is a high-performance
1676 development platform that supports the QorIQ LS1046A
1677 Layerscape Architecture processor.
1679 config TARGET_LS1046AFRWY
1680 bool "Support ls1046afrwy"
1683 select ARMV8_MULTIENTRY
1684 select ARCH_SUPPORT_TFABOOT
1685 select BOARD_EARLY_INIT_F
1686 select BOARD_LATE_INIT
1687 select DM_SPI_FLASH if DM_SPI
1688 select GPIO_EXTRA_HEADER
1691 Support for Freescale LS1046AFRWY platform.
1692 The LS1046A Freeway Board (FRWY) is a high-performance
1693 development platform that supports the QorIQ LS1046A
1694 Layerscape Architecture processor.
1700 select ARMV8_MULTIENTRY
1717 select GPIO_EXTRA_HEADER
1718 select SPL_DM if SPL
1719 select SPL_DM_SPI if SPL
1720 select SPL_DM_SPI_FLASH if SPL
1721 select SPL_DM_I2C if SPL
1722 select SPL_DM_MMC if SPL
1723 select SPL_DM_SERIAL if SPL
1725 Support for Kontron SMARC-sAL28 board.
1727 config TARGET_COLIBRI_PXA270
1728 bool "Support colibri_pxa270"
1730 select GPIO_EXTRA_HEADER
1732 config ARCH_UNIPHIER
1733 bool "Socionext UniPhier SoCs"
1734 select BOARD_LATE_INIT
1744 select OF_BOARD_SETUP
1748 select SPL_BOARD_INIT if SPL
1749 select SPL_DM if SPL
1750 select SPL_LIBCOMMON_SUPPORT if SPL
1751 select SPL_LIBGENERIC_SUPPORT if SPL
1752 select SPL_OF_CONTROL if SPL
1753 select SPL_PINCTRL if SPL
1756 imply DISTRO_DEFAULTS
1759 Support for UniPhier SoC family developed by Socionext Inc.
1760 (formerly, System LSI Business Division of Panasonic Corporation)
1762 config ARCH_SYNQUACER
1763 bool "Socionext SynQuacer SoCs"
1769 select SYSRESET_PSCI
1772 Support for SynQuacer SoC family developed by Socionext Inc.
1773 This SoC is used on 96boards EE DeveloperBox.
1776 bool "Support STMicroelectronics STM32 MCU with cortex M"
1780 select GPIO_EXTRA_HEADER
1784 bool "Support STMicrolectronics SoCs"
1793 Support for STMicroelectronics STiH407/10 SoC family.
1794 This SoC is used on Linaro 96Board STiH410-B2260
1797 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1798 select ARCH_MISC_INIT
1799 select ARCH_SUPPORT_TFABOOT
1800 select BOARD_LATE_INIT
1806 select GPIO_EXTRA_HEADER
1810 select OF_SYSTEM_SETUP
1816 select SYS_THUMB_BUILD
1820 imply OF_LIBFDT_OVERLAY
1821 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1824 Support for STM32MP SoC family developed by STMicroelectronics,
1825 MPUs based on ARM cortex A core
1826 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1827 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1829 SPL is the unsecure FSBL for the basic boot chain.
1831 config ARCH_ROCKCHIP
1832 bool "Support Rockchip SoCs"
1834 select BINMAN if SPL_OPTEE
1844 select DM_USB if USB
1845 select ENABLE_ARM_SOC_BOOT0_HOOK
1848 select SPL_DM if SPL
1849 select SPL_DM_SPI if SPL
1850 select SPL_DM_SPI_FLASH if SPL
1852 select SYS_THUMB_BUILD if !ARM64
1855 imply DEBUG_UART_BOARD_INIT
1856 imply DISTRO_DEFAULTS
1858 imply SARADC_ROCKCHIP
1860 imply SPL_SYS_MALLOC_SIMPLE
1863 imply USB_FUNCTION_FASTBOOT
1865 config ARCH_OCTEONTX
1866 bool "Support OcteonTX SoCs"
1869 select GPIO_EXTRA_HEADER
1873 select BOARD_LATE_INIT
1874 select SYS_CACHE_SHIFT_7
1876 config ARCH_OCTEONTX2
1877 bool "Support OcteonTX2 SoCs"
1880 select GPIO_EXTRA_HEADER
1884 select BOARD_LATE_INIT
1885 select SYS_CACHE_SHIFT_7
1887 config TARGET_THUNDERX_88XX
1888 bool "Support ThunderX 88xx"
1890 select GPIO_EXTRA_HEADER
1893 select SYS_CACHE_SHIFT_7
1896 bool "Support Aspeed SoCs"
1901 config TARGET_DURIAN
1902 bool "Support Phytium Durian Platform"
1904 select GPIO_EXTRA_HEADER
1906 Support for durian platform.
1907 It has 2GB Sdram, uart and pcie.
1909 config TARGET_PRESIDIO_ASIC
1910 bool "Support Cortina Presidio ASIC Platform"
1913 config TARGET_XENGUEST_ARM64
1914 bool "Xen guest ARM64"
1918 select LINUX_KERNEL_IMAGE_HEADER
1923 config ARCH_SUPPORT_TFABOOT
1927 bool "Support for booting from TF-A"
1928 depends on ARCH_SUPPORT_TFABOOT
1931 Some platforms support the setup of secure registers (for instance
1932 for CPU errata handling) or provide secure services like PSCI.
1933 Those services could also be provided by other firmware parts
1934 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
1935 does not need to (and cannot) execute this code.
1936 Enabling this option will make a U-Boot binary that is relying
1937 on other firmware layers to provide secure functionality.
1939 config TI_SECURE_DEVICE
1940 bool "HS Device Type Support"
1941 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1943 If a high secure (HS) device type is being used, this config
1944 must be set. This option impacts various aspects of the
1945 build system (to create signed boot images that can be
1946 authenticated) and the code. See the doc/README.ti-secure
1947 file for further details.
1949 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1950 config ISW_ENTRY_ADDR
1951 hex "Address in memory or XIP address of bootloader entry point"
1952 default 0x402F4000 if AM43XX
1953 default 0x402F0400 if AM33XX
1954 default 0x40301350 if OMAP54XX
1956 After any reset, the boot ROM searches the boot media for a valid
1957 boot image. For non-XIP devices, the ROM then copies the image into
1958 internal memory. For all boot modes, after the ROM processes the
1959 boot image it eventually computes the entry point address depending
1960 on the device type (secure/non-secure), boot media (xip/non-xip) and
1964 source "arch/arm/mach-aspeed/Kconfig"
1966 source "arch/arm/mach-at91/Kconfig"
1968 source "arch/arm/mach-bcm283x/Kconfig"
1970 source "arch/arm/mach-bcmstb/Kconfig"
1972 source "arch/arm/mach-davinci/Kconfig"
1974 source "arch/arm/mach-exynos/Kconfig"
1976 source "arch/arm/mach-highbank/Kconfig"
1978 source "arch/arm/mach-integrator/Kconfig"
1980 source "arch/arm/mach-ipq40xx/Kconfig"
1982 source "arch/arm/mach-k3/Kconfig"
1984 source "arch/arm/mach-keystone/Kconfig"
1986 source "arch/arm/mach-kirkwood/Kconfig"
1988 source "arch/arm/mach-lpc32xx/Kconfig"
1990 source "arch/arm/mach-mvebu/Kconfig"
1992 source "arch/arm/mach-octeontx/Kconfig"
1994 source "arch/arm/mach-octeontx2/Kconfig"
1996 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1998 source "arch/arm/mach-imx/mx2/Kconfig"
2000 source "arch/arm/mach-imx/mx3/Kconfig"
2002 source "arch/arm/mach-imx/mx5/Kconfig"
2004 source "arch/arm/mach-imx/mx6/Kconfig"
2006 source "arch/arm/mach-imx/mx7/Kconfig"
2008 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2010 source "arch/arm/mach-imx/imx8/Kconfig"
2012 source "arch/arm/mach-imx/imx8m/Kconfig"
2014 source "arch/arm/mach-imx/imxrt/Kconfig"
2016 source "arch/arm/mach-imx/mxs/Kconfig"
2018 source "arch/arm/mach-omap2/Kconfig"
2020 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2022 source "arch/arm/mach-orion5x/Kconfig"
2024 source "arch/arm/mach-owl/Kconfig"
2026 source "arch/arm/mach-rmobile/Kconfig"
2028 source "arch/arm/mach-meson/Kconfig"
2030 source "arch/arm/mach-mediatek/Kconfig"
2032 source "arch/arm/mach-qemu/Kconfig"
2034 source "arch/arm/mach-rockchip/Kconfig"
2036 source "arch/arm/mach-s5pc1xx/Kconfig"
2038 source "arch/arm/mach-snapdragon/Kconfig"
2040 source "arch/arm/mach-socfpga/Kconfig"
2042 source "arch/arm/mach-sti/Kconfig"
2044 source "arch/arm/mach-stm32/Kconfig"
2046 source "arch/arm/mach-stm32mp/Kconfig"
2048 source "arch/arm/mach-sunxi/Kconfig"
2050 source "arch/arm/mach-tegra/Kconfig"
2052 source "arch/arm/mach-u8500/Kconfig"
2054 source "arch/arm/mach-uniphier/Kconfig"
2056 source "arch/arm/cpu/armv7/vf610/Kconfig"
2058 source "arch/arm/mach-zynq/Kconfig"
2060 source "arch/arm/mach-zynqmp/Kconfig"
2062 source "arch/arm/mach-versal/Kconfig"
2064 source "arch/arm/mach-zynqmp-r5/Kconfig"
2066 source "arch/arm/cpu/armv7/Kconfig"
2068 source "arch/arm/cpu/armv8/Kconfig"
2070 source "arch/arm/mach-imx/Kconfig"
2072 source "arch/arm/mach-nexell/Kconfig"
2074 source "board/armltd/total_compute/Kconfig"
2076 source "board/bosch/shc/Kconfig"
2077 source "board/bosch/guardian/Kconfig"
2078 source "board/CarMediaLab/flea3/Kconfig"
2079 source "board/Marvell/aspenite/Kconfig"
2080 source "board/Marvell/octeontx/Kconfig"
2081 source "board/Marvell/octeontx2/Kconfig"
2082 source "board/armltd/vexpress64/Kconfig"
2083 source "board/cortina/presidio-asic/Kconfig"
2084 source "board/broadcom/bcm963158/Kconfig"
2085 source "board/broadcom/bcm968360bg/Kconfig"
2086 source "board/broadcom/bcm968580xref/Kconfig"
2087 source "board/broadcom/bcmns3/Kconfig"
2088 source "board/cavium/thunderx/Kconfig"
2089 source "board/eets/pdu001/Kconfig"
2090 source "board/emulation/qemu-arm/Kconfig"
2091 source "board/freescale/ls2080aqds/Kconfig"
2092 source "board/freescale/ls2080ardb/Kconfig"
2093 source "board/freescale/ls1088a/Kconfig"
2094 source "board/freescale/ls1028a/Kconfig"
2095 source "board/freescale/ls1021aqds/Kconfig"
2096 source "board/freescale/ls1043aqds/Kconfig"
2097 source "board/freescale/ls1021atwr/Kconfig"
2098 source "board/freescale/ls1021atsn/Kconfig"
2099 source "board/freescale/ls1021aiot/Kconfig"
2100 source "board/freescale/ls1046aqds/Kconfig"
2101 source "board/freescale/ls1043ardb/Kconfig"
2102 source "board/freescale/ls1046ardb/Kconfig"
2103 source "board/freescale/ls1046afrwy/Kconfig"
2104 source "board/freescale/ls1012aqds/Kconfig"
2105 source "board/freescale/ls1012ardb/Kconfig"
2106 source "board/freescale/ls1012afrdm/Kconfig"
2107 source "board/freescale/lx2160a/Kconfig"
2108 source "board/grinn/chiliboard/Kconfig"
2109 source "board/hisilicon/hikey/Kconfig"
2110 source "board/hisilicon/hikey960/Kconfig"
2111 source "board/hisilicon/poplar/Kconfig"
2112 source "board/isee/igep003x/Kconfig"
2113 source "board/kontron/sl28/Kconfig"
2114 source "board/myir/mys_6ulx/Kconfig"
2115 source "board/seeed/npi_imx6ull/Kconfig"
2116 source "board/socionext/developerbox/Kconfig"
2117 source "board/spear/spear310/Kconfig"
2118 source "board/spear/spear320/Kconfig"
2119 source "board/spear/spear600/Kconfig"
2120 source "board/spear/x600/Kconfig"
2121 source "board/st/stv0991/Kconfig"
2122 source "board/tcl/sl50/Kconfig"
2123 source "board/toradex/colibri_pxa270/Kconfig"
2124 source "board/variscite/dart_6ul/Kconfig"
2125 source "board/vscom/baltos/Kconfig"
2126 source "board/phytium/durian/Kconfig"
2127 source "board/xen/xenguest_arm64/Kconfig"
2128 source "board/keymile/Kconfig"
2130 source "arch/arm/Kconfig.debug"
2135 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
2136 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
2137 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64