4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_WANT_IPC_PARSE_VERSION
8 select BUILDTIME_EXTABLE_SORT if MMU
9 select CPU_PM if (SUSPEND || CPU_IDLE)
10 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
13 select GENERIC_IRQ_PROBE
14 select GENERIC_IRQ_SHOW
15 select GENERIC_PCI_IOMAP
16 select GENERIC_SMP_IDLE_THREAD
17 select GENERIC_STRNCPY_FROM_USER
18 select GENERIC_STRNLEN_USER
19 select HARDIRQS_SW_RESEND
21 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
23 select HAVE_ARCH_SECCOMP_FILTER
24 select HAVE_ARCH_TRACEHOOK
26 select HAVE_C_RECORDMCOUNT
27 select HAVE_DEBUG_KMEMLEAK
28 select HAVE_DMA_API_DEBUG
30 select HAVE_DMA_CONTIGUOUS if MMU
31 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
32 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
33 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
34 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
35 select HAVE_GENERIC_DMA_COHERENT
36 select HAVE_GENERIC_HARDIRQS
37 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
38 select HAVE_IDE if PCI || ISA || PCMCIA
40 select HAVE_KERNEL_GZIP
41 select HAVE_KERNEL_LZMA
42 select HAVE_KERNEL_LZO
44 select HAVE_KPROBES if !XIP_KERNEL
45 select HAVE_KRETPROBES if (HAVE_KPROBES)
47 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
48 select HAVE_PERF_EVENTS
49 select HAVE_REGS_AND_STACK_ACCESS_API
50 select HAVE_SYSCALL_TRACEPOINTS
53 select PERF_USE_VMALLOC
55 select SYS_SUPPORTS_APM_EMULATION
56 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
57 select MODULES_USE_ELF_REL
58 select CLONE_BACKWARDS
59 select OLD_SIGSUSPEND3
62 The ARM series is a line of low-power-consumption RISC chip designs
63 licensed by ARM Ltd and targeted at embedded applications and
64 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
65 manufactured, but legacy ARM-based PC hardware remains popular in
66 Europe. There is an ARM Linux project with a web page at
67 <http://www.arm.linux.org.uk/>.
69 config ARM_HAS_SG_CHAIN
72 config NEED_SG_DMA_LENGTH
75 config ARM_DMA_USE_IOMMU
77 select ARM_HAS_SG_CHAIN
78 select NEED_SG_DMA_LENGTH
86 config SYS_SUPPORTS_APM_EMULATION
94 select GENERIC_ALLOCATOR
105 The Extended Industry Standard Architecture (EISA) bus was
106 developed as an open alternative to the IBM MicroChannel bus.
108 The EISA bus provided some of the features of the IBM MicroChannel
109 bus while maintaining backward compatibility with cards made for
110 the older ISA bus. The EISA bus saw limited use between 1988 and
111 1995 when it was made obsolete by the PCI bus.
113 Say Y here if you are building a kernel for an EISA-based machine.
120 config STACKTRACE_SUPPORT
124 config HAVE_LATENCYTOP_SUPPORT
129 config LOCKDEP_SUPPORT
133 config TRACE_IRQFLAGS_SUPPORT
137 config RWSEM_GENERIC_SPINLOCK
141 config RWSEM_XCHGADD_ALGORITHM
144 config ARCH_HAS_ILOG2_U32
147 config ARCH_HAS_ILOG2_U64
150 config ARCH_HAS_CPUFREQ
153 Internal node to signify that the ARCH has CPUFREQ support
154 and that the relevant menu configurations are displayed for
157 config GENERIC_HWEIGHT
161 config GENERIC_CALIBRATE_DELAY
165 config ARCH_MAY_HAVE_PC_FDC
171 config NEED_DMA_MAP_STATE
174 config ARCH_HAS_DMA_SET_COHERENT_MASK
177 config GENERIC_ISA_DMA
183 config NEED_RET_TO_USER
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NEED_MACH_GPIO_H
217 Select this when mach/gpio.h is required to provide special
218 definitions for this platform. The need for mach/gpio.h should
219 be avoided when possible.
221 config NEED_MACH_IO_H
224 Select this when mach/io.h is required to provide special
225 definitions for this platform. The need for mach/io.h should
226 be avoided when possible.
228 config NEED_MACH_MEMORY_H
231 Select this when mach/memory.h is required to provide special
232 definitions for this platform. The need for mach/memory.h should
233 be avoided when possible.
236 hex "Physical address of main memory" if MMU
237 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
238 default DRAM_BASE if !MMU
240 Please provide the physical address corresponding to the
241 location of main memory in your system.
247 source "init/Kconfig"
249 source "kernel/Kconfig.freezer"
254 bool "MMU-based Paged Memory Management Support"
257 Select if you want MMU-based virtualised addressing space
258 support by paged memory management. If unsure, say 'Y'.
261 # The "ARM system type" choice list is ordered alphabetically by option
262 # text. Please add new entries in the option alphabetic order.
265 prompt "ARM system type"
266 default ARCH_MULTIPLATFORM
268 config ARCH_MULTIPLATFORM
269 bool "Allow multiple platforms to be selected"
271 select ARM_PATCH_PHYS_VIRT
274 select MULTI_IRQ_HANDLER
278 config ARCH_INTEGRATOR
279 bool "ARM Ltd. Integrator family"
280 select ARCH_HAS_CPUFREQ
283 select COMMON_CLK_VERSATILE
284 select GENERIC_CLOCKEVENTS
287 select MULTI_IRQ_HANDLER
288 select NEED_MACH_MEMORY_H
289 select PLAT_VERSATILE
291 select VERSATILE_FPGA_IRQ
293 Support for ARM's Integrator platform.
296 bool "ARM Ltd. RealView family"
297 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select ARM_TIMER_SP804
301 select COMMON_CLK_VERSATILE
302 select GENERIC_CLOCKEVENTS
303 select GPIO_PL061 if GPIOLIB
305 select NEED_MACH_MEMORY_H
306 select PLAT_VERSATILE
307 select PLAT_VERSATILE_CLCD
309 This enables support for ARM Ltd RealView boards.
311 config ARCH_VERSATILE
312 bool "ARM Ltd. Versatile family"
313 select ARCH_WANT_OPTIONAL_GPIOLIB
315 select ARM_TIMER_SP804
318 select GENERIC_CLOCKEVENTS
319 select HAVE_MACH_CLKDEV
321 select PLAT_VERSATILE
322 select PLAT_VERSATILE_CLCD
323 select PLAT_VERSATILE_CLOCK
324 select VERSATILE_FPGA_IRQ
326 This enables support for ARM Ltd Versatile board.
330 select ARCH_REQUIRE_GPIOLIB
334 select NEED_MACH_GPIO_H
335 select NEED_MACH_IO_H if PCCARD
337 select PINCTRL_AT91 if USE_OF
339 This enables support for systems based on Atmel
340 AT91RM9200 and AT91SAM9* processors.
343 bool "Broadcom BCM2835 family"
344 select ARCH_REQUIRE_GPIOLIB
346 select ARM_ERRATA_411920
347 select ARM_TIMER_SP804
351 select GENERIC_CLOCKEVENTS
353 select MULTI_IRQ_HANDLER
355 select PINCTRL_BCM2835
359 This enables support for the Broadcom BCM2835 SoC. This SoC is
360 use in the Raspberry Pi, and Roku 2 devices.
363 bool "Cavium Networks CNS3XXX family"
366 select GENERIC_CLOCKEVENTS
367 select MIGHT_HAVE_CACHE_L2X0
368 select MIGHT_HAVE_PCI
369 select PCI_DOMAINS if PCI
371 Support for Cavium Networks CNS3XXX platform.
374 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
375 select ARCH_REQUIRE_GPIOLIB
380 select GENERIC_CLOCKEVENTS
381 select MULTI_IRQ_HANDLER
382 select NEED_MACH_MEMORY_H
385 Support for Cirrus Logic 711x/721x/731x based boards.
388 bool "Cortina Systems Gemini"
389 select ARCH_REQUIRE_GPIOLIB
390 select ARCH_USES_GETTIMEOFFSET
393 Support for the Cortina Systems Gemini family SoCs
397 select ARCH_REQUIRE_GPIOLIB
399 select GENERIC_CLOCKEVENTS
400 select GENERIC_IRQ_CHIP
401 select MIGHT_HAVE_CACHE_L2X0
407 Support for CSR SiRFprimaII/Marco/Polo platforms
411 select ARCH_USES_GETTIMEOFFSET
414 select NEED_MACH_IO_H
415 select NEED_MACH_MEMORY_H
418 This is an evaluation board for the StrongARM processor available
419 from Digital. It has limited hardware on-board, including an
420 Ethernet interface, two PCMCIA sockets, two serial ports and a
425 select ARCH_HAS_HOLES_MEMORYMODEL
426 select ARCH_REQUIRE_GPIOLIB
427 select ARCH_USES_GETTIMEOFFSET
432 select NEED_MACH_MEMORY_H
434 This enables support for the Cirrus EP93xx series of CPUs.
436 config ARCH_FOOTBRIDGE
440 select GENERIC_CLOCKEVENTS
442 select NEED_MACH_IO_H if !MMU
443 select NEED_MACH_MEMORY_H
445 Support for systems based on the DC21285 companion chip
446 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
449 bool "Freescale MXS-based"
450 select ARCH_REQUIRE_GPIOLIB
454 select GENERIC_CLOCKEVENTS
455 select HAVE_CLK_PREPARE
456 select MULTI_IRQ_HANDLER
461 Support for Freescale MXS-based family of processors
464 bool "Hilscher NetX based"
468 select GENERIC_CLOCKEVENTS
470 This enables support for systems based on the Hilscher NetX Soc
473 bool "Hynix HMS720x-based"
474 select ARCH_USES_GETTIMEOFFSET
478 This enables support for systems based on the Hynix HMS720x
483 select ARCH_SUPPORTS_MSI
485 select NEED_MACH_MEMORY_H
486 select NEED_RET_TO_USER
491 Support for Intel's IOP13XX (XScale) family of processors.
496 select ARCH_REQUIRE_GPIOLIB
498 select NEED_MACH_GPIO_H
499 select NEED_RET_TO_USER
503 Support for Intel's 80219 and IOP32X (XScale) family of
509 select ARCH_REQUIRE_GPIOLIB
511 select NEED_MACH_GPIO_H
512 select NEED_RET_TO_USER
516 Support for Intel's IOP33X (XScale) family of processors.
521 select ARCH_HAS_DMA_SET_COHERENT_MASK
522 select ARCH_REQUIRE_GPIOLIB
525 select DMABOUNCE if PCI
526 select GENERIC_CLOCKEVENTS
527 select MIGHT_HAVE_PCI
528 select NEED_MACH_IO_H
530 Support for Intel's IXP4XX (XScale) family of processors.
534 select ARCH_REQUIRE_GPIOLIB
535 select COMMON_CLK_DOVE
537 select GENERIC_CLOCKEVENTS
538 select MIGHT_HAVE_PCI
541 select PLAT_ORION_LEGACY
542 select USB_ARCH_HAS_EHCI
544 Support for the Marvell Dove SoC 88AP510
547 bool "Marvell Kirkwood"
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
554 select PINCTRL_KIRKWOOD
555 select PLAT_ORION_LEGACY
557 Support for the following Marvell Kirkwood series SoCs:
558 88F6180, 88F6192 and 88F6281.
561 bool "Marvell MV78xx0"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_CLOCKEVENTS
566 select PLAT_ORION_LEGACY
568 Support for the following Marvell MV78xx0 series SoCs:
574 select ARCH_REQUIRE_GPIOLIB
576 select GENERIC_CLOCKEVENTS
578 select PLAT_ORION_LEGACY
580 Support for the following Marvell Orion 5x series SoCs:
581 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
582 Orion-2 (5281), Orion-1-90 (6183).
585 bool "Marvell PXA168/910/MMP2"
587 select ARCH_REQUIRE_GPIOLIB
589 select GENERIC_ALLOCATOR
590 select GENERIC_CLOCKEVENTS
593 select NEED_MACH_GPIO_H
598 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
601 bool "Micrel/Kendin KS8695"
602 select ARCH_REQUIRE_GPIOLIB
605 select GENERIC_CLOCKEVENTS
606 select NEED_MACH_MEMORY_H
608 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
609 System-on-Chip devices.
612 bool "Nuvoton W90X900 CPU"
613 select ARCH_REQUIRE_GPIOLIB
617 select GENERIC_CLOCKEVENTS
619 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
620 At present, the w90x900 has been renamed nuc900, regarding
621 the ARM series product line, you can login the following
622 link address to know more.
624 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
625 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
629 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
637 select USB_ARCH_HAS_OHCI
640 Support for the NXP LPC32XX family of processors
644 select ARCH_HAS_CPUFREQ
648 select GENERIC_CLOCKEVENTS
652 select MIGHT_HAVE_CACHE_L2X0
656 This enables support for NVIDIA Tegra based systems (Tegra APX,
657 Tegra 6xx and Tegra 2 series).
660 bool "PXA2xx/PXA3xx-based"
662 select ARCH_HAS_CPUFREQ
664 select ARCH_REQUIRE_GPIOLIB
665 select ARM_CPU_SUSPEND if PM
669 select GENERIC_CLOCKEVENTS
672 select MULTI_IRQ_HANDLER
673 select NEED_MACH_GPIO_H
677 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
681 select ARCH_REQUIRE_GPIOLIB
683 select GENERIC_CLOCKEVENTS
686 Support for Qualcomm MSM/QSD based systems. This runs on the
687 apps processor of the MSM/QSD and depends on a shared memory
688 interface to the modem processor which runs the baseband
689 stack and controls some vital subsystems
690 (clock and power control, etc).
693 bool "Renesas SH-Mobile / R-Mobile"
695 select GENERIC_CLOCKEVENTS
697 select HAVE_MACH_CLKDEV
699 select MIGHT_HAVE_CACHE_L2X0
700 select MULTI_IRQ_HANDLER
701 select NEED_MACH_MEMORY_H
703 select PM_GENERIC_DOMAINS if PM
706 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
711 select ARCH_MAY_HAVE_PC_FDC
712 select ARCH_SPARSEMEM_ENABLE
713 select ARCH_USES_GETTIMEOFFSET
716 select HAVE_PATA_PLATFORM
718 select NEED_MACH_IO_H
719 select NEED_MACH_MEMORY_H
722 On the Acorn Risc-PC, Linux can support the internal IDE disk and
723 CD-ROM interface, serial and parallel port, and the floppy drive.
727 select ARCH_HAS_CPUFREQ
729 select ARCH_REQUIRE_GPIOLIB
730 select ARCH_SPARSEMEM_ENABLE
735 select GENERIC_CLOCKEVENTS
738 select NEED_MACH_GPIO_H
739 select NEED_MACH_MEMORY_H
742 Support for StrongARM 11x0 based boards.
745 bool "Samsung S3C24XX SoCs"
746 select ARCH_HAS_CPUFREQ
747 select ARCH_USES_GETTIMEOFFSET
751 select HAVE_S3C2410_I2C if I2C
752 select HAVE_S3C2410_WATCHDOG if WATCHDOG
753 select HAVE_S3C_RTC if RTC_CLASS
754 select NEED_MACH_GPIO_H
755 select NEED_MACH_IO_H
757 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
758 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
759 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
760 Samsung SMDK2410 development board (and derivatives).
763 bool "Samsung S3C64XX"
764 select ARCH_HAS_CPUFREQ
765 select ARCH_REQUIRE_GPIOLIB
766 select ARCH_USES_GETTIMEOFFSET
771 select HAVE_S3C2410_I2C if I2C
772 select HAVE_S3C2410_WATCHDOG if WATCHDOG
774 select NEED_MACH_GPIO_H
778 select S3C_GPIO_TRACK
779 select SAMSUNG_CLKSRC
780 select SAMSUNG_GPIOLIB_4BIT
781 select SAMSUNG_IRQ_VIC_TIMER
782 select USB_ARCH_HAS_OHCI
784 Samsung S3C64XX series based systems
787 bool "Samsung S5P6440 S5P6450"
791 select GENERIC_CLOCKEVENTS
794 select HAVE_S3C2410_I2C if I2C
795 select HAVE_S3C2410_WATCHDOG if WATCHDOG
796 select HAVE_S3C_RTC if RTC_CLASS
797 select NEED_MACH_GPIO_H
799 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
803 bool "Samsung S5PC100"
804 select ARCH_USES_GETTIMEOFFSET
809 select HAVE_S3C2410_I2C if I2C
810 select HAVE_S3C2410_WATCHDOG if WATCHDOG
811 select HAVE_S3C_RTC if RTC_CLASS
812 select NEED_MACH_GPIO_H
814 Samsung S5PC100 series based systems
817 bool "Samsung S5PV210/S5PC110"
818 select ARCH_HAS_CPUFREQ
819 select ARCH_HAS_HOLES_MEMORYMODEL
820 select ARCH_SPARSEMEM_ENABLE
824 select GENERIC_CLOCKEVENTS
827 select HAVE_S3C2410_I2C if I2C
828 select HAVE_S3C2410_WATCHDOG if WATCHDOG
829 select HAVE_S3C_RTC if RTC_CLASS
830 select NEED_MACH_GPIO_H
831 select NEED_MACH_MEMORY_H
833 Samsung S5PV210/S5PC110 series based systems
836 bool "Samsung EXYNOS"
837 select ARCH_HAS_CPUFREQ
838 select ARCH_HAS_HOLES_MEMORYMODEL
839 select ARCH_SPARSEMEM_ENABLE
842 select GENERIC_CLOCKEVENTS
845 select HAVE_S3C2410_I2C if I2C
846 select HAVE_S3C2410_WATCHDOG if WATCHDOG
847 select HAVE_S3C_RTC if RTC_CLASS
848 select NEED_MACH_GPIO_H
849 select NEED_MACH_MEMORY_H
851 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
855 select ARCH_USES_GETTIMEOFFSET
859 select NEED_MACH_MEMORY_H
863 Support for the StrongARM based Digital DNARD machine, also known
864 as "Shark" (<http://www.shark-linux.de/shark.html>).
867 bool "ST-Ericsson U300 Series"
869 select ARCH_REQUIRE_GPIOLIB
871 select ARM_PATCH_PHYS_VIRT
877 select GENERIC_CLOCKEVENTS
882 Support for ST-Ericsson U300 series mobile platforms.
885 bool "ST-Ericsson U8500 Series"
887 select ARCH_HAS_CPUFREQ
888 select ARCH_REQUIRE_GPIOLIB
892 select GENERIC_CLOCKEVENTS
894 select MIGHT_HAVE_CACHE_L2X0
897 Support for ST-Ericsson's Ux500 architecture
900 bool "STMicroelectronics Nomadik"
901 select ARCH_REQUIRE_GPIOLIB
906 select GENERIC_CLOCKEVENTS
907 select MIGHT_HAVE_CACHE_L2X0
909 select PINCTRL_STN8815
912 Support for the Nomadik platform by ST-Ericsson
916 select ARCH_HAS_CPUFREQ
917 select ARCH_REQUIRE_GPIOLIB
922 select GENERIC_CLOCKEVENTS
925 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
929 select ARCH_HAS_HOLES_MEMORYMODEL
930 select ARCH_REQUIRE_GPIOLIB
932 select GENERIC_ALLOCATOR
933 select GENERIC_CLOCKEVENTS
934 select GENERIC_IRQ_CHIP
936 select NEED_MACH_GPIO_H
940 Support for TI's DaVinci platform.
945 select ARCH_HAS_CPUFREQ
946 select ARCH_HAS_HOLES_MEMORYMODEL
947 select ARCH_REQUIRE_GPIOLIB
949 select GENERIC_CLOCKEVENTS
952 Support for TI's OMAP platform (OMAP1/2/3/4).
954 config ARCH_VT8500_SINGLE
955 bool "VIA/WonderMedia 85xx"
956 select ARCH_HAS_CPUFREQ
957 select ARCH_REQUIRE_GPIOLIB
961 select GENERIC_CLOCKEVENTS
964 select MULTI_IRQ_HANDLER
968 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
972 menu "Multiple platform selection"
973 depends on ARCH_MULTIPLATFORM
975 comment "CPU Core family selection"
978 bool "ARMv4 based platforms (FA526, StrongARM)"
979 depends on !ARCH_MULTI_V6_V7
980 select ARCH_MULTI_V4_V5
982 config ARCH_MULTI_V4T
983 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
984 depends on !ARCH_MULTI_V6_V7
985 select ARCH_MULTI_V4_V5
988 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
989 depends on !ARCH_MULTI_V6_V7
990 select ARCH_MULTI_V4_V5
992 config ARCH_MULTI_V4_V5
996 bool "ARMv6 based platforms (ARM11, Scorpion, ...)"
997 select ARCH_MULTI_V6_V7
1000 config ARCH_MULTI_V7
1001 bool "ARMv7 based platforms (Cortex-A, PJ4, Krait)"
1003 select ARCH_MULTI_V6_V7
1004 select ARCH_VEXPRESS
1007 config ARCH_MULTI_V6_V7
1010 config ARCH_MULTI_CPU_AUTO
1011 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
1012 select ARCH_MULTI_V5
1017 # This is sorted alphabetically by mach-* pathname. However, plat-*
1018 # Kconfigs may be included either alphabetically (according to the
1019 # plat- suffix) or along side the corresponding mach-* source.
1021 source "arch/arm/mach-mvebu/Kconfig"
1023 source "arch/arm/mach-at91/Kconfig"
1025 source "arch/arm/mach-bcm/Kconfig"
1027 source "arch/arm/mach-clps711x/Kconfig"
1029 source "arch/arm/mach-cns3xxx/Kconfig"
1031 source "arch/arm/mach-davinci/Kconfig"
1033 source "arch/arm/mach-dove/Kconfig"
1035 source "arch/arm/mach-ep93xx/Kconfig"
1037 source "arch/arm/mach-footbridge/Kconfig"
1039 source "arch/arm/mach-gemini/Kconfig"
1041 source "arch/arm/mach-h720x/Kconfig"
1043 source "arch/arm/mach-highbank/Kconfig"
1045 source "arch/arm/mach-integrator/Kconfig"
1047 source "arch/arm/mach-iop32x/Kconfig"
1049 source "arch/arm/mach-iop33x/Kconfig"
1051 source "arch/arm/mach-iop13xx/Kconfig"
1053 source "arch/arm/mach-ixp4xx/Kconfig"
1055 source "arch/arm/mach-kirkwood/Kconfig"
1057 source "arch/arm/mach-ks8695/Kconfig"
1059 source "arch/arm/mach-msm/Kconfig"
1061 source "arch/arm/mach-mv78xx0/Kconfig"
1063 source "arch/arm/mach-imx/Kconfig"
1065 source "arch/arm/mach-mxs/Kconfig"
1067 source "arch/arm/mach-netx/Kconfig"
1069 source "arch/arm/mach-nomadik/Kconfig"
1071 source "arch/arm/plat-omap/Kconfig"
1073 source "arch/arm/mach-omap1/Kconfig"
1075 source "arch/arm/mach-omap2/Kconfig"
1077 source "arch/arm/mach-orion5x/Kconfig"
1079 source "arch/arm/mach-picoxcell/Kconfig"
1081 source "arch/arm/mach-pxa/Kconfig"
1082 source "arch/arm/plat-pxa/Kconfig"
1084 source "arch/arm/mach-mmp/Kconfig"
1086 source "arch/arm/mach-realview/Kconfig"
1088 source "arch/arm/mach-sa1100/Kconfig"
1090 source "arch/arm/plat-samsung/Kconfig"
1091 source "arch/arm/plat-s3c24xx/Kconfig"
1093 source "arch/arm/mach-socfpga/Kconfig"
1095 source "arch/arm/plat-spear/Kconfig"
1097 source "arch/arm/mach-s3c24xx/Kconfig"
1099 source "arch/arm/mach-s3c2412/Kconfig"
1100 source "arch/arm/mach-s3c2440/Kconfig"
1104 source "arch/arm/mach-s3c64xx/Kconfig"
1107 source "arch/arm/mach-s5p64x0/Kconfig"
1109 source "arch/arm/mach-s5pc100/Kconfig"
1111 source "arch/arm/mach-s5pv210/Kconfig"
1113 source "arch/arm/mach-exynos/Kconfig"
1115 source "arch/arm/mach-shmobile/Kconfig"
1117 source "arch/arm/mach-sunxi/Kconfig"
1119 source "arch/arm/mach-prima2/Kconfig"
1121 source "arch/arm/mach-tegra/Kconfig"
1123 source "arch/arm/mach-u300/Kconfig"
1125 source "arch/arm/mach-ux500/Kconfig"
1127 source "arch/arm/mach-versatile/Kconfig"
1129 source "arch/arm/mach-vexpress/Kconfig"
1130 source "arch/arm/plat-versatile/Kconfig"
1132 source "arch/arm/mach-vt8500/Kconfig"
1134 source "arch/arm/mach-w90x900/Kconfig"
1136 source "arch/arm/mach-zynq/Kconfig"
1138 # Definitions to make life easier
1144 select GENERIC_CLOCKEVENTS
1150 select GENERIC_IRQ_CHIP
1153 config PLAT_ORION_LEGACY
1160 config PLAT_VERSATILE
1163 config ARM_TIMER_SP804
1166 select HAVE_SCHED_CLOCK
1168 source arch/arm/mm/Kconfig
1172 default 16 if ARCH_EP93XX
1176 bool "Enable iWMMXt support"
1177 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1178 default y if PXA27x || PXA3xx || ARCH_MMP
1180 Enable support for iWMMXt context switching at run time if
1181 running on a CPU that supports it.
1185 depends on CPU_XSCALE
1188 config MULTI_IRQ_HANDLER
1191 Allow each machine to specify it's own IRQ handler at run time.
1194 source "arch/arm/Kconfig-nommu"
1197 config ARM_ERRATA_326103
1198 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1201 Executing a SWP instruction to read-only memory does not set bit 11
1202 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1203 treat the access as a read, preventing a COW from occurring and
1204 causing the faulting task to livelock.
1206 config ARM_ERRATA_411920
1207 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1208 depends on CPU_V6 || CPU_V6K
1210 Invalidation of the Instruction Cache operation can
1211 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1212 It does not affect the MPCore. This option enables the ARM Ltd.
1213 recommended workaround.
1215 config ARM_ERRATA_430973
1216 bool "ARM errata: Stale prediction on replaced interworking branch"
1219 This option enables the workaround for the 430973 Cortex-A8
1220 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1221 interworking branch is replaced with another code sequence at the
1222 same virtual address, whether due to self-modifying code or virtual
1223 to physical address re-mapping, Cortex-A8 does not recover from the
1224 stale interworking branch prediction. This results in Cortex-A8
1225 executing the new code sequence in the incorrect ARM or Thumb state.
1226 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1227 and also flushes the branch target cache at every context switch.
1228 Note that setting specific bits in the ACTLR register may not be
1229 available in non-secure mode.
1231 config ARM_ERRATA_458693
1232 bool "ARM errata: Processor deadlock when a false hazard is created"
1234 depends on !ARCH_MULTIPLATFORM
1236 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1237 erratum. For very specific sequences of memory operations, it is
1238 possible for a hazard condition intended for a cache line to instead
1239 be incorrectly associated with a different cache line. This false
1240 hazard might then cause a processor deadlock. The workaround enables
1241 the L1 caching of the NEON accesses and disables the PLD instruction
1242 in the ACTLR register. Note that setting specific bits in the ACTLR
1243 register may not be available in non-secure mode.
1245 config ARM_ERRATA_460075
1246 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1248 depends on !ARCH_MULTIPLATFORM
1250 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1251 erratum. Any asynchronous access to the L2 cache may encounter a
1252 situation in which recent store transactions to the L2 cache are lost
1253 and overwritten with stale memory contents from external memory. The
1254 workaround disables the write-allocate mode for the L2 cache via the
1255 ACTLR register. Note that setting specific bits in the ACTLR register
1256 may not be available in non-secure mode.
1258 config ARM_ERRATA_742230
1259 bool "ARM errata: DMB operation may be faulty"
1260 depends on CPU_V7 && SMP
1261 depends on !ARCH_MULTIPLATFORM
1263 This option enables the workaround for the 742230 Cortex-A9
1264 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1265 between two write operations may not ensure the correct visibility
1266 ordering of the two writes. This workaround sets a specific bit in
1267 the diagnostic register of the Cortex-A9 which causes the DMB
1268 instruction to behave as a DSB, ensuring the correct behaviour of
1271 config ARM_ERRATA_742231
1272 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1273 depends on CPU_V7 && SMP
1274 depends on !ARCH_MULTIPLATFORM
1276 This option enables the workaround for the 742231 Cortex-A9
1277 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1278 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1279 accessing some data located in the same cache line, may get corrupted
1280 data due to bad handling of the address hazard when the line gets
1281 replaced from one of the CPUs at the same time as another CPU is
1282 accessing it. This workaround sets specific bits in the diagnostic
1283 register of the Cortex-A9 which reduces the linefill issuing
1284 capabilities of the processor.
1286 config PL310_ERRATA_588369
1287 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1288 depends on CACHE_L2X0
1290 The PL310 L2 cache controller implements three types of Clean &
1291 Invalidate maintenance operations: by Physical Address
1292 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1293 They are architecturally defined to behave as the execution of a
1294 clean operation followed immediately by an invalidate operation,
1295 both performing to the same memory location. This functionality
1296 is not correctly implemented in PL310 as clean lines are not
1297 invalidated as a result of these operations.
1299 config ARM_ERRATA_720789
1300 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1303 This option enables the workaround for the 720789 Cortex-A9 (prior to
1304 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1305 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1306 As a consequence of this erratum, some TLB entries which should be
1307 invalidated are not, resulting in an incoherency in the system page
1308 tables. The workaround changes the TLB flushing routines to invalidate
1309 entries regardless of the ASID.
1311 config PL310_ERRATA_727915
1312 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1313 depends on CACHE_L2X0
1315 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1316 operation (offset 0x7FC). This operation runs in background so that
1317 PL310 can handle normal accesses while it is in progress. Under very
1318 rare circumstances, due to this erratum, write data can be lost when
1319 PL310 treats a cacheable write transaction during a Clean &
1320 Invalidate by Way operation.
1322 config ARM_ERRATA_743622
1323 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1325 depends on !ARCH_MULTIPLATFORM
1327 This option enables the workaround for the 743622 Cortex-A9
1328 (r2p*) erratum. Under very rare conditions, a faulty
1329 optimisation in the Cortex-A9 Store Buffer may lead to data
1330 corruption. This workaround sets a specific bit in the diagnostic
1331 register of the Cortex-A9 which disables the Store Buffer
1332 optimisation, preventing the defect from occurring. This has no
1333 visible impact on the overall performance or power consumption of the
1336 config ARM_ERRATA_751472
1337 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1339 depends on !ARCH_MULTIPLATFORM
1341 This option enables the workaround for the 751472 Cortex-A9 (prior
1342 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1343 completion of a following broadcasted operation if the second
1344 operation is received by a CPU before the ICIALLUIS has completed,
1345 potentially leading to corrupted entries in the cache or TLB.
1347 config PL310_ERRATA_753970
1348 bool "PL310 errata: cache sync operation may be faulty"
1349 depends on CACHE_PL310
1351 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1353 Under some condition the effect of cache sync operation on
1354 the store buffer still remains when the operation completes.
1355 This means that the store buffer is always asked to drain and
1356 this prevents it from merging any further writes. The workaround
1357 is to replace the normal offset of cache sync operation (0x730)
1358 by another offset targeting an unmapped PL310 register 0x740.
1359 This has the same effect as the cache sync operation: store buffer
1360 drain and waiting for all buffers empty.
1362 config ARM_ERRATA_754322
1363 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1366 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1367 r3p*) erratum. A speculative memory access may cause a page table walk
1368 which starts prior to an ASID switch but completes afterwards. This
1369 can populate the micro-TLB with a stale entry which may be hit with
1370 the new ASID. This workaround places two dsb instructions in the mm
1371 switching code so that no page table walks can cross the ASID switch.
1373 config ARM_ERRATA_754327
1374 bool "ARM errata: no automatic Store Buffer drain"
1375 depends on CPU_V7 && SMP
1377 This option enables the workaround for the 754327 Cortex-A9 (prior to
1378 r2p0) erratum. The Store Buffer does not have any automatic draining
1379 mechanism and therefore a livelock may occur if an external agent
1380 continuously polls a memory location waiting to observe an update.
1381 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1382 written polling loops from denying visibility of updates to memory.
1384 config ARM_ERRATA_364296
1385 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1386 depends on CPU_V6 && !SMP
1388 This options enables the workaround for the 364296 ARM1136
1389 r0p2 erratum (possible cache data corruption with
1390 hit-under-miss enabled). It sets the undocumented bit 31 in
1391 the auxiliary control register and the FI bit in the control
1392 register, thus disabling hit-under-miss without putting the
1393 processor into full low interrupt latency mode. ARM11MPCore
1396 config ARM_ERRATA_764369
1397 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1398 depends on CPU_V7 && SMP
1400 This option enables the workaround for erratum 764369
1401 affecting Cortex-A9 MPCore with two or more processors (all
1402 current revisions). Under certain timing circumstances, a data
1403 cache line maintenance operation by MVA targeting an Inner
1404 Shareable memory region may fail to proceed up to either the
1405 Point of Coherency or to the Point of Unification of the
1406 system. This workaround adds a DSB instruction before the
1407 relevant cache maintenance functions and sets a specific bit
1408 in the diagnostic control register of the SCU.
1410 config PL310_ERRATA_769419
1411 bool "PL310 errata: no automatic Store Buffer drain"
1412 depends on CACHE_L2X0
1414 On revisions of the PL310 prior to r3p2, the Store Buffer does
1415 not automatically drain. This can cause normal, non-cacheable
1416 writes to be retained when the memory system is idle, leading
1417 to suboptimal I/O performance for drivers using coherent DMA.
1418 This option adds a write barrier to the cpu_idle loop so that,
1419 on systems with an outer cache, the store buffer is drained
1422 config ARM_ERRATA_775420
1423 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1426 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1427 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1428 operation aborts with MMU exception, it might cause the processor
1429 to deadlock. This workaround puts DSB before executing ISB if
1430 an abort may occur on cache maintenance.
1434 source "arch/arm/common/Kconfig"
1444 Find out whether you have ISA slots on your motherboard. ISA is the
1445 name of a bus system, i.e. the way the CPU talks to the other stuff
1446 inside your box. Other bus systems are PCI, EISA, MicroChannel
1447 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1448 newer boards don't support it. If you have ISA, say Y, otherwise N.
1450 # Select ISA DMA controller support
1455 # Select ISA DMA interface
1460 bool "PCI support" if MIGHT_HAVE_PCI
1462 Find out whether you have a PCI motherboard. PCI is the name of a
1463 bus system, i.e. the way the CPU talks to the other stuff inside
1464 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1465 VESA. If you have PCI, say Y, otherwise N.
1471 config PCI_NANOENGINE
1472 bool "BSE nanoEngine PCI support"
1473 depends on SA1100_NANOENGINE
1475 Enable PCI on the BSE nanoEngine board.
1480 # Select the host bridge type
1481 config PCI_HOST_VIA82C505
1483 depends on PCI && ARCH_SHARK
1486 config PCI_HOST_ITE8152
1488 depends on PCI && MACH_ARMCORE
1492 source "drivers/pci/Kconfig"
1494 source "drivers/pcmcia/Kconfig"
1498 menu "Kernel Features"
1503 This option should be selected by machines which have an SMP-
1506 The only effect of this option is to make the SMP-related
1507 options available to the user for configuration.
1510 bool "Symmetric Multi-Processing"
1511 depends on CPU_V6K || CPU_V7
1512 depends on GENERIC_CLOCKEVENTS
1515 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1516 select USE_GENERIC_SMP_HELPERS
1518 This enables support for systems with more than one CPU. If you have
1519 a system with only one CPU, like most personal computers, say N. If
1520 you have a system with more than one CPU, say Y.
1522 If you say N here, the kernel will run on single and multiprocessor
1523 machines, but will use only one CPU of a multiprocessor machine. If
1524 you say Y here, the kernel will run on many, but not all, single
1525 processor machines. On a single processor machine, the kernel will
1526 run faster if you say N here.
1528 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1529 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1530 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1532 If you don't know what to do here, say N.
1535 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1536 depends on EXPERIMENTAL
1537 depends on SMP && !XIP_KERNEL
1540 SMP kernels contain instructions which fail on non-SMP processors.
1541 Enabling this option allows the kernel to modify itself to make
1542 these instructions safe. Disabling it allows about 1K of space
1545 If you don't know what to do here, say Y.
1547 config ARM_CPU_TOPOLOGY
1548 bool "Support cpu topology definition"
1549 depends on SMP && CPU_V7
1552 Support ARM cpu topology definition. The MPIDR register defines
1553 affinity between processors which is then used to describe the cpu
1554 topology of an ARM System.
1557 bool "Multi-core scheduler support"
1558 depends on ARM_CPU_TOPOLOGY
1560 Multi-core scheduler support improves the CPU scheduler's decision
1561 making when dealing with multi-core CPU chips at a cost of slightly
1562 increased overhead in some places. If unsure say N here.
1565 bool "SMT scheduler support"
1566 depends on ARM_CPU_TOPOLOGY
1568 Improves the CPU scheduler's decision making when dealing with
1569 MultiThreading at a cost of slightly increased overhead in some
1570 places. If unsure say N here.
1575 This option enables support for the ARM system coherency unit
1577 config ARM_ARCH_TIMER
1578 bool "Architected timer support"
1581 This option enables support for the ARM architected timer
1587 This options enables support for the ARM timer and watchdog unit
1590 prompt "Memory split"
1593 Select the desired split between kernel and user memory.
1595 If you are not absolutely sure what you are doing, leave this
1599 bool "3G/1G user/kernel split"
1601 bool "2G/2G user/kernel split"
1603 bool "1G/3G user/kernel split"
1608 default 0x40000000 if VMSPLIT_1G
1609 default 0x80000000 if VMSPLIT_2G
1613 int "Maximum number of CPUs (2-32)"
1619 bool "Support for hot-pluggable CPUs"
1620 depends on SMP && HOTPLUG
1622 Say Y here to experiment with turning CPUs off and on. CPUs
1623 can be controlled through /sys/devices/system/cpu.
1626 bool "Use local timer interrupts"
1629 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1631 Enable support for local timers on SMP platforms, rather then the
1632 legacy IPI broadcast method. Local timers allows the system
1633 accounting to be spread across the timer interval, preventing a
1634 "thundering herd" at every timer tick.
1638 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1639 default 355 if ARCH_U8500
1640 default 264 if MACH_H4700
1641 default 512 if SOC_OMAP5
1642 default 288 if ARCH_VT8500
1645 Maximum number of GPIOs in the system.
1647 If unsure, leave the default value.
1649 source kernel/Kconfig.preempt
1653 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1654 ARCH_S5PV210 || ARCH_EXYNOS4
1655 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1656 default AT91_TIMER_HZ if ARCH_AT91
1657 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1660 config THUMB2_KERNEL
1661 bool "Compile the kernel in Thumb-2 mode"
1662 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1664 select ARM_ASM_UNIFIED
1667 By enabling this option, the kernel will be compiled in
1668 Thumb-2 mode. A compiler/assembler that understand the unified
1669 ARM-Thumb syntax is needed.
1673 config THUMB2_AVOID_R_ARM_THM_JUMP11
1674 bool "Work around buggy Thumb-2 short branch relocations in gas"
1675 depends on THUMB2_KERNEL && MODULES
1678 Various binutils versions can resolve Thumb-2 branches to
1679 locally-defined, preemptible global symbols as short-range "b.n"
1680 branch instructions.
1682 This is a problem, because there's no guarantee the final
1683 destination of the symbol, or any candidate locations for a
1684 trampoline, are within range of the branch. For this reason, the
1685 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1686 relocation in modules at all, and it makes little sense to add
1689 The symptom is that the kernel fails with an "unsupported
1690 relocation" error when loading some modules.
1692 Until fixed tools are available, passing
1693 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1694 code which hits this problem, at the cost of a bit of extra runtime
1695 stack usage in some cases.
1697 The problem is described in more detail at:
1698 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1700 Only Thumb-2 kernels are affected.
1702 Unless you are sure your tools don't have this problem, say Y.
1704 config ARM_ASM_UNIFIED
1708 bool "Use the ARM EABI to compile the kernel"
1710 This option allows for the kernel to be compiled using the latest
1711 ARM ABI (aka EABI). This is only useful if you are using a user
1712 space environment that is also compiled with EABI.
1714 Since there are major incompatibilities between the legacy ABI and
1715 EABI, especially with regard to structure member alignment, this
1716 option also changes the kernel syscall calling convention to
1717 disambiguate both ABIs and allow for backward compatibility support
1718 (selected with CONFIG_OABI_COMPAT).
1720 To use this you need GCC version 4.0.0 or later.
1723 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1724 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1727 This option preserves the old syscall interface along with the
1728 new (ARM EABI) one. It also provides a compatibility layer to
1729 intercept syscalls that have structure arguments which layout
1730 in memory differs between the legacy ABI and the new ARM EABI
1731 (only for non "thumb" binaries). This option adds a tiny
1732 overhead to all syscalls and produces a slightly larger kernel.
1733 If you know you'll be using only pure EABI user space then you
1734 can say N here. If this option is not selected and you attempt
1735 to execute a legacy ABI binary then the result will be
1736 UNPREDICTABLE (in fact it can be predicted that it won't work
1737 at all). If in doubt say Y.
1739 config ARCH_HAS_HOLES_MEMORYMODEL
1742 config ARCH_SPARSEMEM_ENABLE
1745 config ARCH_SPARSEMEM_DEFAULT
1746 def_bool ARCH_SPARSEMEM_ENABLE
1748 config ARCH_SELECT_MEMORY_MODEL
1749 def_bool ARCH_SPARSEMEM_ENABLE
1751 config HAVE_ARCH_PFN_VALID
1752 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1755 bool "High Memory Support"
1758 The address space of ARM processors is only 4 Gigabytes large
1759 and it has to accommodate user address space, kernel address
1760 space as well as some memory mapped IO. That means that, if you
1761 have a large amount of physical memory and/or IO, not all of the
1762 memory can be "permanently mapped" by the kernel. The physical
1763 memory that is not permanently mapped is called "high memory".
1765 Depending on the selected kernel/user memory split, minimum
1766 vmalloc space and actual amount of RAM, you may not need this
1767 option which should result in a slightly faster kernel.
1772 bool "Allocate 2nd-level pagetables from highmem"
1775 config HW_PERF_EVENTS
1776 bool "Enable hardware performance counter support for perf events"
1777 depends on PERF_EVENTS
1780 Enable hardware performance counter support for perf events. If
1781 disabled, perf events will use software events only.
1785 config FORCE_MAX_ZONEORDER
1786 int "Maximum zone order" if ARCH_SHMOBILE
1787 range 11 64 if ARCH_SHMOBILE
1788 default "12" if SOC_AM33XX
1789 default "9" if SA1111
1792 The kernel memory allocator divides physically contiguous memory
1793 blocks into "zones", where each zone is a power of two number of
1794 pages. This option selects the largest power of two that the kernel
1795 keeps in the memory allocator. If you need to allocate very large
1796 blocks of physically contiguous memory, then you may need to
1797 increase this value.
1799 This config option is actually maximum order plus one. For example,
1800 a value of 11 means that the largest free memory block is 2^10 pages.
1802 config ALIGNMENT_TRAP
1804 depends on CPU_CP15_MMU
1805 default y if !ARCH_EBSA110
1806 select HAVE_PROC_CPU if PROC_FS
1808 ARM processors cannot fetch/store information which is not
1809 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1810 address divisible by 4. On 32-bit ARM processors, these non-aligned
1811 fetch/store instructions will be emulated in software if you say
1812 here, which has a severe performance impact. This is necessary for
1813 correct operation of some network protocols. With an IP-only
1814 configuration it is safe to say N, otherwise say Y.
1816 config UACCESS_WITH_MEMCPY
1817 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1819 default y if CPU_FEROCEON
1821 Implement faster copy_to_user and clear_user methods for CPU
1822 cores where a 8-word STM instruction give significantly higher
1823 memory write throughput than a sequence of individual 32bit stores.
1825 A possible side effect is a slight increase in scheduling latency
1826 between threads sharing the same address space if they invoke
1827 such copy operations with large buffers.
1829 However, if the CPU data cache is using a write-allocate mode,
1830 this option is unlikely to provide any performance gain.
1834 prompt "Enable seccomp to safely compute untrusted bytecode"
1836 This kernel feature is useful for number crunching applications
1837 that may need to compute untrusted bytecode during their
1838 execution. By using pipes or other transports made available to
1839 the process as file descriptors supporting the read/write
1840 syscalls, it's possible to isolate those applications in
1841 their own address space using seccomp. Once seccomp is
1842 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1843 and the task is only allowed to execute a few safe syscalls
1844 defined by each seccomp mode.
1846 config CC_STACKPROTECTOR
1847 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1848 depends on EXPERIMENTAL
1850 This option turns on the -fstack-protector GCC feature. This
1851 feature puts, at the beginning of functions, a canary value on
1852 the stack just before the return address, and validates
1853 the value just before actually returning. Stack based buffer
1854 overflows (that need to overwrite this return address) now also
1855 overwrite the canary, which gets detected and the attack is then
1856 neutralized via a kernel panic.
1857 This feature requires gcc version 4.2 or above.
1864 bool "Xen guest support on ARM (EXPERIMENTAL)"
1865 depends on EXPERIMENTAL && ARM && OF
1866 depends on CPU_V7 && !CPU_V6
1868 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1875 bool "Flattened Device Tree support"
1878 select OF_EARLY_FLATTREE
1880 Include support for flattened device tree machine descriptions.
1883 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1886 This is the traditional way of passing data to the kernel at boot
1887 time. If you are solely relying on the flattened device tree (or
1888 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1889 to remove ATAGS support from your kernel binary. If unsure,
1892 config DEPRECATED_PARAM_STRUCT
1893 bool "Provide old way to pass kernel parameters"
1896 This was deprecated in 2001 and announced to live on for 5 years.
1897 Some old boot loaders still use this way.
1899 # Compressed boot loader in ROM. Yes, we really want to ask about
1900 # TEXT and BSS so we preserve their values in the config files.
1901 config ZBOOT_ROM_TEXT
1902 hex "Compressed ROM boot loader base address"
1905 The physical address at which the ROM-able zImage is to be
1906 placed in the target. Platforms which normally make use of
1907 ROM-able zImage formats normally set this to a suitable
1908 value in their defconfig file.
1910 If ZBOOT_ROM is not enabled, this has no effect.
1912 config ZBOOT_ROM_BSS
1913 hex "Compressed ROM boot loader BSS address"
1916 The base address of an area of read/write memory in the target
1917 for the ROM-able zImage which must be available while the
1918 decompressor is running. It must be large enough to hold the
1919 entire decompressed kernel plus an additional 128 KiB.
1920 Platforms which normally make use of ROM-able zImage formats
1921 normally set this to a suitable value in their defconfig file.
1923 If ZBOOT_ROM is not enabled, this has no effect.
1926 bool "Compressed boot loader in ROM/flash"
1927 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1929 Say Y here if you intend to execute your compressed kernel image
1930 (zImage) directly from ROM or flash. If unsure, say N.
1933 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1934 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1935 default ZBOOT_ROM_NONE
1937 Include experimental SD/MMC loading code in the ROM-able zImage.
1938 With this enabled it is possible to write the ROM-able zImage
1939 kernel image to an MMC or SD card and boot the kernel straight
1940 from the reset vector. At reset the processor Mask ROM will load
1941 the first part of the ROM-able zImage which in turn loads the
1942 rest the kernel image to RAM.
1944 config ZBOOT_ROM_NONE
1945 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1947 Do not load image from SD or MMC
1949 config ZBOOT_ROM_MMCIF
1950 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1952 Load image from MMCIF hardware block.
1954 config ZBOOT_ROM_SH_MOBILE_SDHI
1955 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1957 Load image from SDHI hardware block
1961 config ARM_APPENDED_DTB
1962 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1963 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1965 With this option, the boot code will look for a device tree binary
1966 (DTB) appended to zImage
1967 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1969 This is meant as a backward compatibility convenience for those
1970 systems with a bootloader that can't be upgraded to accommodate
1971 the documented boot protocol using a device tree.
1973 Beware that there is very little in terms of protection against
1974 this option being confused by leftover garbage in memory that might
1975 look like a DTB header after a reboot if no actual DTB is appended
1976 to zImage. Do not leave this option active in a production kernel
1977 if you don't intend to always append a DTB. Proper passing of the
1978 location into r2 of a bootloader provided DTB is always preferable
1981 config ARM_ATAG_DTB_COMPAT
1982 bool "Supplement the appended DTB with traditional ATAG information"
1983 depends on ARM_APPENDED_DTB
1985 Some old bootloaders can't be updated to a DTB capable one, yet
1986 they provide ATAGs with memory configuration, the ramdisk address,
1987 the kernel cmdline string, etc. Such information is dynamically
1988 provided by the bootloader and can't always be stored in a static
1989 DTB. To allow a device tree enabled kernel to be used with such
1990 bootloaders, this option allows zImage to extract the information
1991 from the ATAG list and store it at run time into the appended DTB.
1994 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1995 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1997 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1998 bool "Use bootloader kernel arguments if available"
2000 Uses the command-line options passed by the boot loader instead of
2001 the device tree bootargs property. If the boot loader doesn't provide
2002 any, the device tree bootargs property will be used.
2004 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2005 bool "Extend with bootloader kernel arguments"
2007 The command-line arguments provided by the boot loader will be
2008 appended to the the device tree bootargs property.
2013 string "Default kernel command string"
2016 On some architectures (EBSA110 and CATS), there is currently no way
2017 for the boot loader to pass arguments to the kernel. For these
2018 architectures, you should supply some command-line options at build
2019 time by entering them here. As a minimum, you should specify the
2020 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2023 prompt "Kernel command line type" if CMDLINE != ""
2024 default CMDLINE_FROM_BOOTLOADER
2027 config CMDLINE_FROM_BOOTLOADER
2028 bool "Use bootloader kernel arguments if available"
2030 Uses the command-line options passed by the boot loader. If
2031 the boot loader doesn't provide any, the default kernel command
2032 string provided in CMDLINE will be used.
2034 config CMDLINE_EXTEND
2035 bool "Extend bootloader kernel arguments"
2037 The command-line arguments provided by the boot loader will be
2038 appended to the default kernel command string.
2040 config CMDLINE_FORCE
2041 bool "Always use the default kernel command string"
2043 Always use the default kernel command string, even if the boot
2044 loader passes other arguments to the kernel.
2045 This is useful if you cannot or don't want to change the
2046 command-line options your boot loader passes to the kernel.
2050 bool "Kernel Execute-In-Place from ROM"
2051 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2053 Execute-In-Place allows the kernel to run from non-volatile storage
2054 directly addressable by the CPU, such as NOR flash. This saves RAM
2055 space since the text section of the kernel is not loaded from flash
2056 to RAM. Read-write sections, such as the data section and stack,
2057 are still copied to RAM. The XIP kernel is not compressed since
2058 it has to run directly from flash, so it will take more space to
2059 store it. The flash address used to link the kernel object files,
2060 and for storing it, is configuration dependent. Therefore, if you
2061 say Y here, you must know the proper physical address where to
2062 store the kernel image depending on your own flash memory usage.
2064 Also note that the make target becomes "make xipImage" rather than
2065 "make zImage" or "make Image". The final kernel binary to put in
2066 ROM memory will be arch/arm/boot/xipImage.
2070 config XIP_PHYS_ADDR
2071 hex "XIP Kernel Physical Location"
2072 depends on XIP_KERNEL
2073 default "0x00080000"
2075 This is the physical address in your flash memory the kernel will
2076 be linked for and stored to. This address is dependent on your
2080 bool "Kexec system call (EXPERIMENTAL)"
2081 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2083 kexec is a system call that implements the ability to shutdown your
2084 current kernel, and to start another kernel. It is like a reboot
2085 but it is independent of the system firmware. And like a reboot
2086 you can start any kernel with it, not just Linux.
2088 It is an ongoing process to be certain the hardware in a machine
2089 is properly shutdown, so do not be surprised if this code does not
2090 initially work for you. It may help to enable device hotplugging
2094 bool "Export atags in procfs"
2095 depends on ATAGS && KEXEC
2098 Should the atags used to boot the kernel be exported in an "atags"
2099 file in procfs. Useful with kexec.
2102 bool "Build kdump crash kernel (EXPERIMENTAL)"
2103 depends on EXPERIMENTAL
2105 Generate crash dump after being started by kexec. This should
2106 be normally only set in special crash dump kernels which are
2107 loaded in the main kernel with kexec-tools into a specially
2108 reserved region and then later executed after a crash by
2109 kdump/kexec. The crash dump kernel must be compiled to a
2110 memory address not used by the main kernel
2112 For more details see Documentation/kdump/kdump.txt
2114 config AUTO_ZRELADDR
2115 bool "Auto calculation of the decompressed kernel image address"
2116 depends on !ZBOOT_ROM && !ARCH_U300
2118 ZRELADDR is the physical address where the decompressed kernel
2119 image will be placed. If AUTO_ZRELADDR is selected, the address
2120 will be determined at run-time by masking the current IP with
2121 0xf8000000. This assumes the zImage being placed in the first 128MB
2122 from start of memory.
2126 menu "CPU Power Management"
2130 source "drivers/cpufreq/Kconfig"
2133 tristate "CPUfreq driver for i.MX CPUs"
2134 depends on ARCH_MXC && CPU_FREQ
2135 select CPU_FREQ_TABLE
2137 This enables the CPUfreq driver for i.MX CPUs.
2139 config CPU_FREQ_SA1100
2142 config CPU_FREQ_SA1110
2145 config CPU_FREQ_INTEGRATOR
2146 tristate "CPUfreq driver for ARM Integrator CPUs"
2147 depends on ARCH_INTEGRATOR && CPU_FREQ
2150 This enables the CPUfreq driver for ARM Integrator CPUs.
2152 For details, take a look at <file:Documentation/cpu-freq>.
2158 depends on CPU_FREQ && ARCH_PXA && PXA25x
2160 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2161 select CPU_FREQ_TABLE
2166 Internal configuration node for common cpufreq on Samsung SoC
2168 config CPU_FREQ_S3C24XX
2169 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2170 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2173 This enables the CPUfreq driver for the Samsung S3C24XX family
2176 For details, take a look at <file:Documentation/cpu-freq>.
2180 config CPU_FREQ_S3C24XX_PLL
2181 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2182 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2184 Compile in support for changing the PLL frequency from the
2185 S3C24XX series CPUfreq driver. The PLL takes time to settle
2186 after a frequency change, so by default it is not enabled.
2188 This also means that the PLL tables for the selected CPU(s) will
2189 be built which may increase the size of the kernel image.
2191 config CPU_FREQ_S3C24XX_DEBUG
2192 bool "Debug CPUfreq Samsung driver core"
2193 depends on CPU_FREQ_S3C24XX
2195 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2197 config CPU_FREQ_S3C24XX_IODEBUG
2198 bool "Debug CPUfreq Samsung driver IO timing"
2199 depends on CPU_FREQ_S3C24XX
2201 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2203 config CPU_FREQ_S3C24XX_DEBUGFS
2204 bool "Export debugfs for CPUFreq"
2205 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2207 Export status information via debugfs.
2211 source "drivers/cpuidle/Kconfig"
2215 menu "Floating point emulation"
2217 comment "At least one emulation must be selected"
2220 bool "NWFPE math emulation"
2221 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2223 Say Y to include the NWFPE floating point emulator in the kernel.
2224 This is necessary to run most binaries. Linux does not currently
2225 support floating point hardware so you need to say Y here even if
2226 your machine has an FPA or floating point co-processor podule.
2228 You may say N here if you are going to load the Acorn FPEmulator
2229 early in the bootup.
2232 bool "Support extended precision"
2233 depends on FPE_NWFPE
2235 Say Y to include 80-bit support in the kernel floating-point
2236 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2237 Note that gcc does not generate 80-bit operations by default,
2238 so in most cases this option only enlarges the size of the
2239 floating point emulator without any good reason.
2241 You almost surely want to say N here.
2244 bool "FastFPE math emulation (EXPERIMENTAL)"
2245 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2247 Say Y here to include the FAST floating point emulator in the kernel.
2248 This is an experimental much faster emulator which now also has full
2249 precision for the mantissa. It does not support any exceptions.
2250 It is very simple, and approximately 3-6 times faster than NWFPE.
2252 It should be sufficient for most programs. It may be not suitable
2253 for scientific calculations, but you have to check this for yourself.
2254 If you do not feel you need a faster FP emulation you should better
2258 bool "VFP-format floating point maths"
2259 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2261 Say Y to include VFP support code in the kernel. This is needed
2262 if your hardware includes a VFP unit.
2264 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2265 release notes and additional status information.
2267 Say N if your target does not have VFP hardware.
2275 bool "Advanced SIMD (NEON) Extension support"
2276 depends on VFPv3 && CPU_V7
2278 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2283 menu "Userspace binary formats"
2285 source "fs/Kconfig.binfmt"
2288 tristate "RISC OS personality"
2291 Say Y here to include the kernel code necessary if you want to run
2292 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2293 experimental; if this sounds frightening, say N and sleep in peace.
2294 You can also say M here to compile this support as a module (which
2295 will be called arthur).
2299 menu "Power management options"
2301 source "kernel/power/Kconfig"
2303 config ARCH_SUSPEND_POSSIBLE
2304 depends on !ARCH_S5PC100
2305 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2306 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2309 config ARM_CPU_SUSPEND
2314 source "net/Kconfig"
2316 source "drivers/Kconfig"
2320 source "arch/arm/Kconfig.debug"
2322 source "security/Kconfig"
2324 source "crypto/Kconfig"
2326 source "lib/Kconfig"