1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
15 select INIT_SP_RELATIVE
17 U-Boot expects to be linked to a specific hard-coded address, and to
18 be loaded to and run from that address. This option lifts that
19 restriction, thus allowing the code to be loaded to and executed
20 from almost any address. This logic relies on the relocation
21 information that is embedded in the binary to support U-Boot
22 relocating itself to the top-of-RAM later during execution.
24 config INIT_SP_RELATIVE
25 bool "Specify the early stack pointer relative to the .bss section"
27 U-Boot typically uses a hard-coded value for the stack pointer
28 before relocation. Enable this option to instead calculate the
29 initial SP at run-time. This is useful to avoid hard-coding addresses
30 into U-Boot, so that it can be loaded and executed at arbitrary
31 addresses and thus avoid using arbitrary addresses at runtime.
33 If this option is enabled, the early stack pointer is set to
34 &_bss_start with a offset value added. The offset is specified by
35 SYS_INIT_SP_BSS_OFFSET.
37 config SYS_INIT_SP_BSS_OFFSET
38 int "Early stack offset from the .bss base address"
39 depends on INIT_SP_RELATIVE
42 This option's value is the offset added to &_bss_start in order to
43 calculate the stack pointer. This offset should be large enough so
44 that the early malloc region, global data (gd), and early stack usage
45 do not overlap any appended DTB.
47 config LINUX_KERNEL_IMAGE_HEADER
50 Place a Linux kernel image header at the start of the U-Boot binary.
51 The format of the header is described in the Linux kernel source at
52 Documentation/arm64/booting.txt. This feature is useful since the
53 image header reports the amount of memory (BSS and similar) that
54 U-Boot needs to use, but which isn't part of the binary.
56 if LINUX_KERNEL_IMAGE_HEADER
57 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
60 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
61 TEXT_OFFSET value written to the Linux kernel image header.
68 ARM GICV3 Interrupt translation service (ITS).
69 Basic support for programming locality specific peripheral
70 interrupts (LPI) configuration tables and enable LPI tables.
71 LPI configuration table can be used by u-boot or Linux.
72 ARM GICV3 has limitation, once the LPI table is enabled, LPI
73 configuration table can not be re-programmed, unless GICV3 reset.
77 default y if ARM64 && !POSITION_INDEPENDENT
79 config DMA_ADDR_T_64BIT
89 # Used for compatibility with asm files copied from the kernel
90 config ARM_ASM_UNIFIED
94 # Used for compatibility with asm files copied from the kernel
99 bool "Do not enable icache"
102 Do not enable instruction cache in U-Boot.
104 config SPL_SYS_ICACHE_OFF
105 bool "Do not enable icache in SPL"
107 default SYS_ICACHE_OFF
109 Do not enable instruction cache in SPL.
111 config SYS_DCACHE_OFF
112 bool "Do not enable dcache"
115 Do not enable data cache in U-Boot.
117 config SPL_SYS_DCACHE_OFF
118 bool "Do not enable dcache in SPL"
120 default SYS_DCACHE_OFF
122 Do not enable data cache in SPL.
124 config SYS_ARM_CACHE_CP15
125 bool "CP15 based cache enabling support"
127 Select this if your processor suports enabling caches by using
131 bool "MMU-based Paged Memory Management Support"
132 select SYS_ARM_CACHE_CP15
134 Select if you want MMU-based virtualised addressing space
135 support via paged memory management.
138 bool 'Use the ARM v7 PMSA Compliant MPU'
140 Some ARM systems without an MMU have instead a Memory Protection
141 Unit (MPU) that defines the type and permissions for regions of
143 If your CPU has an MPU then you should choose 'y' here unless you
144 know that you do not want to use the MPU.
146 # If set, the workarounds for these ARM errata are applied early during U-Boot
147 # startup. Note that in general these options force the workarounds to be
148 # applied; no CPU-type/version detection exists, unlike the similar options in
149 # the Linux kernel. Do not set these options unless they apply! Also note that
150 # the following can be machine-specific errata. These do have ability to
151 # provide rudimentary version and machine-specific checks, but expect no
153 # CONFIG_ARM_ERRATA_430973
154 # CONFIG_ARM_ERRATA_454179
155 # CONFIG_ARM_ERRATA_621766
156 # CONFIG_ARM_ERRATA_798870
157 # CONFIG_ARM_ERRATA_801819
158 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
159 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
161 config ARM_ERRATA_430973
164 config ARM_ERRATA_454179
167 config ARM_ERRATA_621766
170 config ARM_ERRATA_716044
173 config ARM_ERRATA_725233
176 config ARM_ERRATA_742230
179 config ARM_ERRATA_743622
182 config ARM_ERRATA_751472
185 config ARM_ERRATA_761320
188 config ARM_ERRATA_773022
191 config ARM_ERRATA_774769
194 config ARM_ERRATA_794072
197 config ARM_ERRATA_798870
200 config ARM_ERRATA_801819
203 config ARM_ERRATA_826974
206 config ARM_ERRATA_828024
209 config ARM_ERRATA_829520
212 config ARM_ERRATA_833069
215 config ARM_ERRATA_833471
218 config ARM_ERRATA_845369
221 config ARM_ERRATA_852421
224 config ARM_ERRATA_852423
227 config ARM_ERRATA_855873
230 config ARM_CORTEX_A8_CVE_2017_5715
233 config ARM_CORTEX_A15_CVE_2017_5715
238 select SYS_CACHE_SHIFT_5
243 select SYS_CACHE_SHIFT_5
248 select SYS_CACHE_SHIFT_5
253 select SYS_CACHE_SHIFT_5
258 select SYS_CACHE_SHIFT_5
264 select SYS_CACHE_SHIFT_5
271 select SYS_CACHE_SHIFT_6
278 select SYS_CACHE_SHIFT_5
279 select SYS_THUMB_BUILD
285 select SYS_ARM_CACHE_CP15
287 select SYS_CACHE_SHIFT_6
291 select SYS_CACHE_SHIFT_5
296 select SYS_CACHE_SHIFT_5
300 default "arm720t" if CPU_ARM720T
301 default "arm920t" if CPU_ARM920T
302 default "arm926ejs" if CPU_ARM926EJS
303 default "arm946es" if CPU_ARM946ES
304 default "arm1136" if CPU_ARM1136
305 default "arm1176" if CPU_ARM1176
306 default "armv7" if CPU_V7A
307 default "armv7" if CPU_V7R
308 default "armv7m" if CPU_V7M
309 default "pxa" if CPU_PXA
310 default "sa1100" if CPU_SA1100
311 default "armv8" if ARM64
315 default 4 if CPU_ARM720T
316 default 4 if CPU_ARM920T
317 default 5 if CPU_ARM926EJS
318 default 5 if CPU_ARM946ES
319 default 6 if CPU_ARM1136
320 default 6 if CPU_ARM1176
325 default 4 if CPU_SA1100
328 config SYS_CACHE_SHIFT_5
331 config SYS_CACHE_SHIFT_6
334 config SYS_CACHE_SHIFT_7
337 config SYS_CACHELINE_SIZE
339 default 128 if SYS_CACHE_SHIFT_7
340 default 64 if SYS_CACHE_SHIFT_6
341 default 32 if SYS_CACHE_SHIFT_5
344 prompt "Select the ARM data write cache policy"
345 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
346 TARGET_BCMNSP || CPU_PXA || RZA1
347 default SYS_ARM_CACHE_WRITEBACK
349 config SYS_ARM_CACHE_WRITEBACK
350 bool "Write-back (WB)"
352 A write updates the cache only and marks the cache line as dirty.
353 External memory is updated only when the line is evicted or explicitly
356 config SYS_ARM_CACHE_WRITETHROUGH
357 bool "Write-through (WT)"
359 A write updates both the cache and the external memory system.
360 This does not mark the cache line as dirty.
362 config SYS_ARM_CACHE_WRITEALLOC
363 bool "Write allocation (WA)"
365 A cache line is allocated on a write miss. This means that executing a
366 store instruction on the processor might cause a burst read to occur.
367 There is a linefill to obtain the data for the cache line, before the
372 bool "Enable ARCH_CPU_INIT"
374 Some architectures require a call to arch_cpu_init().
375 Say Y here to enable it
377 config SYS_ARCH_TIMER
378 bool "ARM Generic Timer support"
379 depends on CPU_V7A || ARM64
382 The ARM Generic Timer (aka arch-timer) provides an architected
383 interface to a timer source on an SoC.
384 It is mandatory for ARMv8 implementation and widely available
388 bool "Support for ARM SMC Calling Convention (SMCCC)"
389 depends on CPU_V7A || ARM64
392 Say Y here if you want to enable ARM SMC Calling Convention.
393 This should be enabled if U-Boot needs to communicate with system
394 firmware (for example, PSCI) according to SMCCC.
397 bool "support boot from semihosting"
399 In emulated environments, semihosting is a way for
400 the hosted environment to call out to the emulator to
401 retrieve files from the host machine.
403 config SYS_THUMB_BUILD
404 bool "Build U-Boot using the Thumb instruction set"
407 Use this flag to build U-Boot using the Thumb instruction set for
408 ARM architectures. Thumb instruction set provides better code
409 density. For ARM architectures that support Thumb2 this flag will
410 result in Thumb2 code generated by GCC.
412 config SPL_SYS_THUMB_BUILD
413 bool "Build SPL using the Thumb instruction set"
414 default y if SYS_THUMB_BUILD
415 depends on !ARM64 && SPL
417 Use this flag to build SPL using the Thumb instruction set for
418 ARM architectures. Thumb instruction set provides better code
419 density. For ARM architectures that support Thumb2 this flag will
420 result in Thumb2 code generated by GCC.
422 config TPL_SYS_THUMB_BUILD
423 bool "Build TPL using the Thumb instruction set"
424 default y if SYS_THUMB_BUILD
425 depends on TPL && !ARM64
427 Use this flag to build TPL using the Thumb instruction set for
428 ARM architectures. Thumb instruction set provides better code
429 density. For ARM architectures that support Thumb2 this flag will
430 result in Thumb2 code generated by GCC.
433 config SYS_L2CACHE_OFF
436 If SoC does not support L2CACHE or one does not want to enable
437 L2CACHE, choose this option.
439 config ENABLE_ARM_SOC_BOOT0_HOOK
440 bool "prepare BOOT0 header"
442 If the SoC's BOOT0 requires a header area filled with (magic)
443 values, then choose this option, and create a file included as
444 <asm/arch/boot0.h> which contains the required assembler code.
446 config ARM_CORTEX_CPU_IS_UP
450 config USE_ARCH_MEMCPY
451 bool "Use an assembly optimized implementation of memcpy"
455 Enable the generation of an optimized version of memcpy.
456 Such an implementation may be faster under some conditions
457 but may increase the binary size.
459 config SPL_USE_ARCH_MEMCPY
460 bool "Use an assembly optimized implementation of memcpy for SPL"
461 default y if USE_ARCH_MEMCPY
462 depends on !ARM64 && SPL
464 Enable the generation of an optimized version of memcpy.
465 Such an implementation may be faster under some conditions
466 but may increase the binary size.
468 config TPL_USE_ARCH_MEMCPY
469 bool "Use an assembly optimized implementation of memcpy for TPL"
470 default y if USE_ARCH_MEMCPY
471 depends on !ARM64 && TPL
473 Enable the generation of an optimized version of memcpy.
474 Such an implementation may be faster under some conditions
475 but may increase the binary size.
477 config USE_ARCH_MEMSET
478 bool "Use an assembly optimized implementation of memset"
482 Enable the generation of an optimized version of memset.
483 Such an implementation may be faster under some conditions
484 but may increase the binary size.
486 config SPL_USE_ARCH_MEMSET
487 bool "Use an assembly optimized implementation of memset for SPL"
488 default y if USE_ARCH_MEMSET
489 depends on !ARM64 && SPL
491 Enable the generation of an optimized version of memset.
492 Such an implementation may be faster under some conditions
493 but may increase the binary size.
495 config TPL_USE_ARCH_MEMSET
496 bool "Use an assembly optimized implementation of memset for TPL"
497 default y if USE_ARCH_MEMSET
498 depends on !ARM64 && TPL
500 Enable the generation of an optimized version of memset.
501 Such an implementation may be faster under some conditions
502 but may increase the binary size.
504 config SET_STACK_SIZE
505 bool "Enable an option to set max stack size that can be used"
506 default y if ARCH_VERSAL || ARCH_ZYNQMP || ARCH_ZYNQ
508 This will enable an option to set max stack size that can be
512 hex "Define max stack size that can be used by U-Boot"
513 depends on SET_STACK_SIZE
514 default 0x4000000 if ARCH_VERSAL || ARCH_ZYNQMP
515 default 0x1000000 if ARCH_ZYNQ
517 Define Max stack size that can be used by U-Boot so that the
518 initrd_high will be calculated as base stack pointer minus this
521 config ARM64_SUPPORT_AARCH32
522 bool "ARM64 system support AArch32 execution state"
524 default y if !TARGET_THUNDERX_88XX
526 This ARM64 system supports AArch32 execution state.
529 prompt "Target select"
534 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
536 config TARGET_EDB93XX
537 bool "Support edb93xx"
541 config TARGET_ASPENITE
542 bool "Support aspenite"
546 bool "Support gplugd"
552 select SPL_DM_SPI if SPL
555 Support for TI's DaVinci platform.
558 bool "Marvell Kirkwood"
559 select ARCH_MISC_INIT
560 select BOARD_EARLY_INIT_F
564 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
570 select SPL_DM_SPI if SPL
571 select SPL_DM_SPI_FLASH if SPL
586 config TARGET_SPEAR300
587 bool "Support spear300"
588 select BOARD_EARLY_INIT_F
593 config TARGET_SPEAR310
594 bool "Support spear310"
595 select BOARD_EARLY_INIT_F
600 config TARGET_SPEAR320
601 bool "Support spear320"
602 select BOARD_EARLY_INIT_F
607 config TARGET_SPEAR600
608 bool "Support spear600"
609 select BOARD_EARLY_INIT_F
614 config TARGET_STV0991
615 bool "Support stv0991"
628 select BOARD_LATE_INIT
637 config TARGET_MX35PDK
638 bool "Support mx35pdk"
639 select BOARD_LATE_INIT
643 bool "Broadcom BCM283X family"
649 select SERIAL_SEARCH_ALL
654 bool "Broadcom BCM63158 family"
660 bool "Broadcom BCM68360 family"
666 bool "Broadcom BCM6858 family"
671 config TARGET_VEXPRESS_CA15_TC2
672 bool "Support vexpress_ca15_tc2"
674 select CPU_V7_HAS_NONSEC
675 select CPU_V7_HAS_VIRT
679 bool "Broadcom BCM7XXX family"
683 select OF_PRIOR_STAGE
686 This enables support for Broadcom ARM-based set-top box
687 chipsets, including the 7445 family of chips.
689 config TARGET_VEXPRESS_CA5X2
690 bool "Support vexpress_ca5x2"
694 config TARGET_VEXPRESS_CA9X4
695 bool "Support vexpress_ca9x4"
699 config TARGET_BCM23550_W1D
700 bool "Support bcm23550_w1d"
705 config TARGET_BCM28155_AP
706 bool "Support bcm28155_ap"
711 config TARGET_BCMCYGNUS
712 bool "Support bcmcygnus"
715 imply BCM_SF2_ETH_GMAC
723 bool "Support bcmnsp"
727 bool "Support Broadcom Northstar2"
730 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
731 ARMv8 Cortex-A57 processors targeting a broad range of networking
735 bool "Samsung EXYNOS"
744 imply SYS_THUMB_BUILD
749 bool "Samsung S5PC1XX"
758 bool "Calxeda Highbank"
762 config ARCH_INTEGRATOR
763 bool "ARM Ltd. Integrator family"
774 select SYS_ARCH_TIMER
775 select SYS_THUMB_BUILD
781 bool "Texas Instruments' K3 Architecture"
786 config ARCH_OMAP2PLUS
789 select SPL_BOARD_INIT if SPL
790 select SPL_STACK_R if SPL
796 imply DISTRO_DEFAULTS
799 Support for the Meson SoC family developed by Amlogic Inc.,
800 targeted at media players and tablet computers. We currently
801 support the S905 (GXBaby) 64-bit SoC.
808 select SPL_LIBCOMMON_SUPPORT if SPL
809 select SPL_LIBGENERIC_SUPPORT if SPL
810 select SPL_OF_CONTROL if SPL
813 Support for the MediaTek SoCs family developed by MediaTek Inc.
814 Please refer to doc/README.mediatek for more information.
817 bool "NXP LPC32xx platform"
827 bool "NXP i.MX8 platform"
831 select ENABLE_ARM_SOC_BOOT0_HOOK
834 bool "NXP i.MX8M platform"
841 bool "NXP i.MXRT platform"
849 bool "NXP i.MX23 family"
860 bool "NXP i.MX28 family"
866 bool "NXP i.MX31 family"
872 select ROM_UNIFIED_SECTIONS
874 imply SYS_THUMB_BUILD
878 select ARCH_MISC_INIT
880 select SYS_FSL_HAS_SEC if IMX_HAB
881 select SYS_FSL_SEC_COMPAT_4
882 select SYS_FSL_SEC_LE
883 imply BOARD_EARLY_INIT_F
885 imply SYS_THUMB_BUILD
890 select SYS_FSL_HAS_SEC if IMX_HAB
891 select SYS_FSL_SEC_COMPAT_4
892 select SYS_FSL_SEC_LE
894 imply SYS_THUMB_BUILD
898 default "arch/arm/mach-omap2/u-boot-spl.lds"
903 select BOARD_EARLY_INIT_F
908 bool "Actions Semi OWL SoCs"
915 select SYS_RELOC_GD_ENV_ADDR
919 bool "QEMU Virtual Platform"
920 select ARCH_SUPPORT_TFABOOT
930 bool "Renesas ARM SoCs"
931 select BOARD_EARLY_INIT_F if !RZA1
936 imply SYS_THUMB_BUILD
937 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
939 config TARGET_S32V234EVB
940 bool "Support s32v234evb"
942 select SYS_FSL_ERRATUM_ESDHC111
944 config ARCH_SNAPDRAGON
945 bool "Qualcomm Snapdragon SoCs"
958 bool "Altera SOCFPGA family"
959 select ARCH_EARLY_INIT_R
960 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
961 select ARM64 if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
962 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
965 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
967 select SPL_DM_RESET if DM_RESET
969 select SPL_LIBCOMMON_SUPPORT
970 select SPL_LIBGENERIC_SUPPORT
971 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
972 select SPL_OF_CONTROL
973 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_STRATIX10 || TARGET_SOCFPGA_AGILEX
974 select SPL_SERIAL_SUPPORT
976 select SPL_WATCHDOG_SUPPORT
979 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
981 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
982 select SYSRESET_SOCFPGA_S10 if TARGET_SOCFPGA_STRATIX10
992 imply SPL_DM_SPI_FLASH
993 imply SPL_LIBDISK_SUPPORT
994 imply SPL_MMC_SUPPORT
995 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
996 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
997 imply SPL_SPI_FLASH_SUPPORT
998 imply SPL_SPI_SUPPORT
1002 bool "Support sunxi (Allwinner) SoCs"
1005 select CMD_MMC if MMC
1006 select CMD_USB if DISTRO_DEFAULTS
1012 select DM_MMC if MMC
1013 select DM_SCSI if SCSI
1015 select DM_USB if DISTRO_DEFAULTS
1016 select OF_BOARD_SETUP
1019 select SPECIFY_CONSOLE_INDEX
1020 select SPL_STACK_R if SPL
1021 select SPL_SYS_MALLOC_SIMPLE if SPL
1022 select SPL_SYS_THUMB_BUILD if !ARM64
1025 select SYS_THUMB_BUILD if !ARM64
1026 select USB if DISTRO_DEFAULTS
1027 select USB_KEYBOARD if DISTRO_DEFAULTS
1028 select USB_STORAGE if DISTRO_DEFAULTS
1029 select SPL_USE_TINY_PRINTF
1031 select SYS_RELOC_GD_ENV_ADDR
1034 imply CMD_UBI if MTD_RAW_NAND
1035 imply DISTRO_DEFAULTS
1038 imply OF_LIBFDT_OVERLAY
1039 imply PRE_CONSOLE_BUFFER
1040 imply SPL_GPIO_SUPPORT
1041 imply SPL_LIBCOMMON_SUPPORT
1042 imply SPL_LIBGENERIC_SUPPORT
1043 imply SPL_MMC_SUPPORT if MMC
1044 imply SPL_POWER_SUPPORT
1045 imply SPL_SERIAL_SUPPORT
1049 bool "ST-Ericsson U8500 Series"
1053 select DM_MMC if MMC
1055 select DM_USB if USB
1059 imply ARM_PL180_MMCI
1061 imply NOMADIK_MTU_TIMER
1064 imply SYSRESET_SYSCON
1067 bool "Support Xilinx Versal Platform"
1071 select DM_ETH if NET
1072 select DM_MMC if MMC
1075 imply BOARD_LATE_INIT
1078 bool "Freescale Vybrid"
1080 select SYS_FSL_ERRATUM_ESDHC111
1085 bool "Xilinx Zynq based platform"
1090 select DM_ETH if NET
1091 select DM_MMC if MMC
1095 select DM_USB if USB
1098 select SPL_BOARD_INIT if SPL
1099 select SPL_CLK if SPL
1100 select SPL_DM if SPL
1101 select SPL_DM_SPI if SPL
1102 select SPL_DM_SPI_FLASH if SPL
1103 select SPL_OF_CONTROL if SPL
1104 select SPL_SEPARATE_BSS if SPL
1106 imply ARCH_EARLY_INIT_R
1107 imply BOARD_LATE_INIT
1113 config ARCH_ZYNQMP_R5
1114 bool "Xilinx ZynqMP R5 based platform"
1118 select DM_ETH if NET
1119 select DM_MMC if MMC
1126 bool "Xilinx ZynqMP based platform"
1130 select DM_ETH if NET
1132 select DM_MMC if MMC
1134 select DM_SPI if SPI
1135 select DM_SPI_FLASH if DM_SPI
1136 select DM_USB if USB
1139 select SPL_BOARD_INIT if SPL
1140 select SPL_CLK if SPL
1141 select SPL_DM_SPI if SPI
1142 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1143 select SPL_DM_MAILBOX if SPL
1144 select SPL_FIRMWARE if SPL
1145 select SPL_SEPARATE_BSS if SPL
1148 imply BOARD_LATE_INIT
1156 imply DISTRO_DEFAULTS
1159 config TARGET_VEXPRESS64_AEMV8A
1160 bool "Support vexpress_aemv8a"
1164 config TARGET_VEXPRESS64_BASE_FVP
1165 bool "Support Versatile Express ARMv8a FVP BASE model"
1170 config TARGET_VEXPRESS64_JUNO
1171 bool "Support Versatile Express Juno Development Platform"
1186 config TARGET_LS2080A_EMU
1187 bool "Support ls2080a_emu"
1190 select ARMV8_MULTIENTRY
1191 select FSL_DDR_SYNC_REFRESH
1193 Support for Freescale LS2080A_EMU platform.
1194 The LS2080A Development System (EMULATOR) is a pre-silicon
1195 development platform that supports the QorIQ LS2080A
1196 Layerscape Architecture processor.
1198 config TARGET_LS2080A_SIMU
1199 bool "Support ls2080a_simu"
1202 select ARMV8_MULTIENTRY
1203 select BOARD_LATE_INIT
1205 Support for Freescale LS2080A_SIMU platform.
1206 The LS2080A Development System (QDS) is a pre silicon
1207 development platform that supports the QorIQ LS2080A
1208 Layerscape Architecture processor.
1210 config TARGET_LS1088AQDS
1211 bool "Support ls1088aqds"
1214 select ARMV8_MULTIENTRY
1215 select ARCH_SUPPORT_TFABOOT
1216 select BOARD_LATE_INIT
1218 select FSL_DDR_INTERACTIVE if !SD_BOOT
1220 Support for NXP LS1088AQDS platform.
1221 The LS1088A Development System (QDS) is a high-performance
1222 development platform that supports the QorIQ LS1088A
1223 Layerscape Architecture processor.
1225 config TARGET_LS2080AQDS
1226 bool "Support ls2080aqds"
1229 select ARMV8_MULTIENTRY
1230 select ARCH_SUPPORT_TFABOOT
1231 select BOARD_LATE_INIT
1236 select FSL_DDR_INTERACTIVE if !SPL
1238 Support for Freescale LS2080AQDS platform.
1239 The LS2080A Development System (QDS) is a high-performance
1240 development platform that supports the QorIQ LS2080A
1241 Layerscape Architecture processor.
1243 config TARGET_LS2080ARDB
1244 bool "Support ls2080ardb"
1247 select ARMV8_MULTIENTRY
1248 select ARCH_SUPPORT_TFABOOT
1249 select BOARD_LATE_INIT
1252 select FSL_DDR_INTERACTIVE if !SPL
1256 Support for Freescale LS2080ARDB platform.
1257 The LS2080A Reference design board (RDB) is a high-performance
1258 development platform that supports the QorIQ LS2080A
1259 Layerscape Architecture processor.
1261 config TARGET_LS2081ARDB
1262 bool "Support ls2081ardb"
1265 select ARMV8_MULTIENTRY
1266 select BOARD_LATE_INIT
1269 Support for Freescale LS2081ARDB platform.
1270 The LS2081A Reference design board (RDB) is a high-performance
1271 development platform that supports the QorIQ LS2081A/LS2041A
1272 Layerscape Architecture processor.
1274 config TARGET_LX2160ARDB
1275 bool "Support lx2160ardb"
1278 select ARMV8_MULTIENTRY
1279 select ARCH_SUPPORT_TFABOOT
1280 select BOARD_LATE_INIT
1282 Support for NXP LX2160ARDB platform.
1283 The lx2160ardb (LX2160A Reference design board (RDB)
1284 is a high-performance development platform that supports the
1285 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1287 config TARGET_LX2160AQDS
1288 bool "Support lx2160aqds"
1291 select ARMV8_MULTIENTRY
1292 select ARCH_SUPPORT_TFABOOT
1293 select BOARD_LATE_INIT
1295 Support for NXP LX2160AQDS platform.
1296 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1297 is a high-performance development platform that supports the
1298 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1301 bool "Support HiKey 96boards Consumer Edition Platform"
1308 select SPECIFY_CONSOLE_INDEX
1311 Support for HiKey 96boards platform. It features a HI6220
1312 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1314 config TARGET_HIKEY960
1315 bool "Support HiKey960 96boards Consumer Edition Platform"
1323 Support for HiKey960 96boards platform. It features a HI3660
1324 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1326 config TARGET_POPLAR
1327 bool "Support Poplar 96boards Enterprise Edition Platform"
1336 Support for Poplar 96boards EE platform. It features a HI3798cv200
1337 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1338 making it capable of running any commercial set-top solution based on
1341 config TARGET_LS1012AQDS
1342 bool "Support ls1012aqds"
1345 select ARCH_SUPPORT_TFABOOT
1346 select BOARD_LATE_INIT
1348 Support for Freescale LS1012AQDS platform.
1349 The LS1012A Development System (QDS) is a high-performance
1350 development platform that supports the QorIQ LS1012A
1351 Layerscape Architecture processor.
1353 config TARGET_LS1012ARDB
1354 bool "Support ls1012ardb"
1357 select ARCH_SUPPORT_TFABOOT
1358 select BOARD_LATE_INIT
1362 Support for Freescale LS1012ARDB platform.
1363 The LS1012A Reference design board (RDB) is a high-performance
1364 development platform that supports the QorIQ LS1012A
1365 Layerscape Architecture processor.
1367 config TARGET_LS1012A2G5RDB
1368 bool "Support ls1012a2g5rdb"
1371 select ARCH_SUPPORT_TFABOOT
1372 select BOARD_LATE_INIT
1375 Support for Freescale LS1012A2G5RDB platform.
1376 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1377 development platform that supports the QorIQ LS1012A
1378 Layerscape Architecture processor.
1380 config TARGET_LS1012AFRWY
1381 bool "Support ls1012afrwy"
1384 select ARCH_SUPPORT_TFABOOT
1385 select BOARD_LATE_INIT
1389 Support for Freescale LS1012AFRWY platform.
1390 The LS1012A FRWY board (FRWY) is a high-performance
1391 development platform that supports the QorIQ LS1012A
1392 Layerscape Architecture processor.
1394 config TARGET_LS1012AFRDM
1395 bool "Support ls1012afrdm"
1398 select ARCH_SUPPORT_TFABOOT
1400 Support for Freescale LS1012AFRDM platform.
1401 The LS1012A Freedom board (FRDM) is a high-performance
1402 development platform that supports the QorIQ LS1012A
1403 Layerscape Architecture processor.
1405 config TARGET_LS1028AQDS
1406 bool "Support ls1028aqds"
1409 select ARMV8_MULTIENTRY
1410 select ARCH_SUPPORT_TFABOOT
1411 select BOARD_LATE_INIT
1413 Support for Freescale LS1028AQDS platform
1414 The LS1028A Development System (QDS) is a high-performance
1415 development platform that supports the QorIQ LS1028A
1416 Layerscape Architecture processor.
1418 config TARGET_LS1028ARDB
1419 bool "Support ls1028ardb"
1422 select ARMV8_MULTIENTRY
1423 select ARCH_SUPPORT_TFABOOT
1424 select BOARD_LATE_INIT
1426 Support for Freescale LS1028ARDB platform
1427 The LS1028A Development System (RDB) is a high-performance
1428 development platform that supports the QorIQ LS1028A
1429 Layerscape Architecture processor.
1431 config TARGET_LS1088ARDB
1432 bool "Support ls1088ardb"
1435 select ARMV8_MULTIENTRY
1436 select ARCH_SUPPORT_TFABOOT
1437 select BOARD_LATE_INIT
1439 select FSL_DDR_INTERACTIVE if !SD_BOOT
1441 Support for NXP LS1088ARDB platform.
1442 The LS1088A Reference design board (RDB) is a high-performance
1443 development platform that supports the QorIQ LS1088A
1444 Layerscape Architecture processor.
1446 config TARGET_LS1021AQDS
1447 bool "Support ls1021aqds"
1449 select ARCH_SUPPORT_PSCI
1450 select BOARD_EARLY_INIT_F
1451 select BOARD_LATE_INIT
1453 select CPU_V7_HAS_NONSEC
1454 select CPU_V7_HAS_VIRT
1455 select LS1_DEEP_SLEEP
1458 select FSL_DDR_INTERACTIVE
1459 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1460 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1463 config TARGET_LS1021ATWR
1464 bool "Support ls1021atwr"
1466 select ARCH_SUPPORT_PSCI
1467 select BOARD_EARLY_INIT_F
1468 select BOARD_LATE_INIT
1470 select CPU_V7_HAS_NONSEC
1471 select CPU_V7_HAS_VIRT
1472 select LS1_DEEP_SLEEP
1474 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1477 config TARGET_LS1021ATSN
1478 bool "Support ls1021atsn"
1480 select ARCH_SUPPORT_PSCI
1481 select BOARD_EARLY_INIT_F
1482 select BOARD_LATE_INIT
1484 select CPU_V7_HAS_NONSEC
1485 select CPU_V7_HAS_VIRT
1486 select LS1_DEEP_SLEEP
1490 config TARGET_LS1021AIOT
1491 bool "Support ls1021aiot"
1493 select ARCH_SUPPORT_PSCI
1494 select BOARD_LATE_INIT
1496 select CPU_V7_HAS_NONSEC
1497 select CPU_V7_HAS_VIRT
1499 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1502 Support for Freescale LS1021AIOT platform.
1503 The LS1021A Freescale board (IOT) is a high-performance
1504 development platform that supports the QorIQ LS1021A
1505 Layerscape Architecture processor.
1507 config TARGET_LS1043AQDS
1508 bool "Support ls1043aqds"
1511 select ARMV8_MULTIENTRY
1512 select ARCH_SUPPORT_TFABOOT
1513 select BOARD_EARLY_INIT_F
1514 select BOARD_LATE_INIT
1516 select FSL_DDR_INTERACTIVE if !SPL
1517 select FSL_DSPI if !SPL_NO_DSPI
1518 select DM_SPI_FLASH if FSL_DSPI
1522 Support for Freescale LS1043AQDS platform.
1524 config TARGET_LS1043ARDB
1525 bool "Support ls1043ardb"
1528 select ARMV8_MULTIENTRY
1529 select ARCH_SUPPORT_TFABOOT
1530 select BOARD_EARLY_INIT_F
1531 select BOARD_LATE_INIT
1533 select FSL_DSPI if !SPL_NO_DSPI
1534 select DM_SPI_FLASH if FSL_DSPI
1536 Support for Freescale LS1043ARDB platform.
1538 config TARGET_LS1046AQDS
1539 bool "Support ls1046aqds"
1542 select ARMV8_MULTIENTRY
1543 select ARCH_SUPPORT_TFABOOT
1544 select BOARD_EARLY_INIT_F
1545 select BOARD_LATE_INIT
1546 select DM_SPI_FLASH if DM_SPI
1548 select FSL_DDR_BIST if !SPL
1549 select FSL_DDR_INTERACTIVE if !SPL
1550 select FSL_DDR_INTERACTIVE if !SPL
1553 Support for Freescale LS1046AQDS platform.
1554 The LS1046A Development System (QDS) is a high-performance
1555 development platform that supports the QorIQ LS1046A
1556 Layerscape Architecture processor.
1558 config TARGET_LS1046ARDB
1559 bool "Support ls1046ardb"
1562 select ARMV8_MULTIENTRY
1563 select ARCH_SUPPORT_TFABOOT
1564 select BOARD_EARLY_INIT_F
1565 select BOARD_LATE_INIT
1566 select DM_SPI_FLASH if DM_SPI
1567 select POWER_MC34VR500
1570 select FSL_DDR_INTERACTIVE if !SPL
1573 Support for Freescale LS1046ARDB platform.
1574 The LS1046A Reference Design Board (RDB) is a high-performance
1575 development platform that supports the QorIQ LS1046A
1576 Layerscape Architecture processor.
1578 config TARGET_LS1046AFRWY
1579 bool "Support ls1046afrwy"
1582 select ARMV8_MULTIENTRY
1583 select ARCH_SUPPORT_TFABOOT
1584 select BOARD_EARLY_INIT_F
1585 select BOARD_LATE_INIT
1586 select DM_SPI_FLASH if DM_SPI
1589 Support for Freescale LS1046AFRWY platform.
1590 The LS1046A Freeway Board (FRWY) is a high-performance
1591 development platform that supports the QorIQ LS1046A
1592 Layerscape Architecture processor.
1594 config TARGET_COLIBRI_PXA270
1595 bool "Support colibri_pxa270"
1598 config ARCH_UNIPHIER
1599 bool "Socionext UniPhier SoCs"
1600 select BOARD_LATE_INIT
1610 select OF_BOARD_SETUP
1614 select SPL_BOARD_INIT if SPL
1615 select SPL_DM if SPL
1616 select SPL_LIBCOMMON_SUPPORT if SPL
1617 select SPL_LIBGENERIC_SUPPORT if SPL
1618 select SPL_OF_CONTROL if SPL
1619 select SPL_PINCTRL if SPL
1622 imply DISTRO_DEFAULTS
1625 Support for UniPhier SoC family developed by Socionext Inc.
1626 (formerly, System LSI Business Division of Panasonic Corporation)
1629 bool "Support STMicroelectronics STM32 MCU with cortex M"
1636 bool "Support STMicrolectronics SoCs"
1645 Support for STMicroelectronics STiH407/10 SoC family.
1646 This SoC is used on Linaro 96Board STiH410-B2260
1649 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1650 select ARCH_MISC_INIT
1651 select ARCH_SUPPORT_TFABOOT
1652 select BOARD_LATE_INIT
1661 select OF_SYSTEM_SETUP
1667 select SYS_THUMB_BUILD
1671 imply OF_LIBFDT_OVERLAY
1672 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1675 Support for STM32MP SoC family developed by STMicroelectronics,
1676 MPUs based on ARM cortex A core
1677 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1678 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1680 SPL is the unsecure FSBL for the basic boot chain.
1682 config ARCH_ROCKCHIP
1683 bool "Support Rockchip SoCs"
1685 select BINMAN if !ARM64
1695 select DM_USB if USB
1696 select ENABLE_ARM_SOC_BOOT0_HOOK
1699 select SPL_DM if SPL
1700 select SPL_DM_SPI if SPL
1701 select SPL_DM_SPI_FLASH if SPL
1703 select SYS_THUMB_BUILD if !ARM64
1706 imply DEBUG_UART_BOARD_INIT
1707 imply DISTRO_DEFAULTS
1709 imply SARADC_ROCKCHIP
1711 imply SPL_SYS_MALLOC_SIMPLE
1714 imply USB_FUNCTION_FASTBOOT
1716 config TARGET_THUNDERX_88XX
1717 bool "Support ThunderX 88xx"
1721 select SYS_CACHE_SHIFT_7
1724 bool "Support Aspeed SoCs"
1729 config TARGET_DURIAN
1730 bool "Support Phytium Durian Platform"
1733 Support for durian platform.
1734 It has 2GB Sdram, uart and pcie.
1736 config TARGET_PRESIDIO_ASIC
1737 bool "Support Cortina Presidio ASIC Platform"
1742 config ARCH_SUPPORT_TFABOOT
1746 bool "Support for booting from TF-A"
1747 depends on ARCH_SUPPORT_TFABOOT
1750 Enabling this will make a U-Boot binary that is capable of being
1751 booted via TF-A (Trusted Firmware for Cortex-A).
1753 config TI_SECURE_DEVICE
1754 bool "HS Device Type Support"
1755 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1757 If a high secure (HS) device type is being used, this config
1758 must be set. This option impacts various aspects of the
1759 build system (to create signed boot images that can be
1760 authenticated) and the code. See the doc/README.ti-secure
1761 file for further details.
1763 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1764 config ISW_ENTRY_ADDR
1765 hex "Address in memory or XIP address of bootloader entry point"
1766 default 0x402F4000 if AM43XX
1767 default 0x402F0400 if AM33XX
1768 default 0x40301350 if OMAP54XX
1770 After any reset, the boot ROM searches the boot media for a valid
1771 boot image. For non-XIP devices, the ROM then copies the image into
1772 internal memory. For all boot modes, after the ROM processes the
1773 boot image it eventually computes the entry point address depending
1774 on the device type (secure/non-secure), boot media (xip/non-xip) and
1778 source "arch/arm/mach-aspeed/Kconfig"
1780 source "arch/arm/mach-at91/Kconfig"
1782 source "arch/arm/mach-bcm283x/Kconfig"
1784 source "arch/arm/mach-bcmstb/Kconfig"
1786 source "arch/arm/mach-davinci/Kconfig"
1788 source "arch/arm/mach-exynos/Kconfig"
1790 source "arch/arm/mach-highbank/Kconfig"
1792 source "arch/arm/mach-integrator/Kconfig"
1794 source "arch/arm/mach-k3/Kconfig"
1796 source "arch/arm/mach-keystone/Kconfig"
1798 source "arch/arm/mach-kirkwood/Kconfig"
1800 source "arch/arm/mach-lpc32xx/Kconfig"
1802 source "arch/arm/mach-mvebu/Kconfig"
1804 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1806 source "arch/arm/mach-imx/mx2/Kconfig"
1808 source "arch/arm/mach-imx/mx3/Kconfig"
1810 source "arch/arm/mach-imx/mx5/Kconfig"
1812 source "arch/arm/mach-imx/mx6/Kconfig"
1814 source "arch/arm/mach-imx/mx7/Kconfig"
1816 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1818 source "arch/arm/mach-imx/imx8/Kconfig"
1820 source "arch/arm/mach-imx/imx8m/Kconfig"
1822 source "arch/arm/mach-imx/imxrt/Kconfig"
1824 source "arch/arm/mach-imx/mxs/Kconfig"
1826 source "arch/arm/mach-omap2/Kconfig"
1828 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1830 source "arch/arm/mach-orion5x/Kconfig"
1832 source "arch/arm/mach-owl/Kconfig"
1834 source "arch/arm/mach-rmobile/Kconfig"
1836 source "arch/arm/mach-meson/Kconfig"
1838 source "arch/arm/mach-mediatek/Kconfig"
1840 source "arch/arm/mach-qemu/Kconfig"
1842 source "arch/arm/mach-rockchip/Kconfig"
1844 source "arch/arm/mach-s5pc1xx/Kconfig"
1846 source "arch/arm/mach-snapdragon/Kconfig"
1848 source "arch/arm/mach-socfpga/Kconfig"
1850 source "arch/arm/mach-sti/Kconfig"
1852 source "arch/arm/mach-stm32/Kconfig"
1854 source "arch/arm/mach-stm32mp/Kconfig"
1856 source "arch/arm/mach-sunxi/Kconfig"
1858 source "arch/arm/mach-tegra/Kconfig"
1860 source "arch/arm/mach-u8500/Kconfig"
1862 source "arch/arm/mach-uniphier/Kconfig"
1864 source "arch/arm/cpu/armv7/vf610/Kconfig"
1866 source "arch/arm/mach-zynq/Kconfig"
1868 source "arch/arm/mach-zynqmp/Kconfig"
1870 source "arch/arm/mach-versal/Kconfig"
1872 source "arch/arm/mach-zynqmp-r5/Kconfig"
1874 source "arch/arm/cpu/armv7/Kconfig"
1876 source "arch/arm/cpu/armv8/Kconfig"
1878 source "arch/arm/mach-imx/Kconfig"
1880 source "board/bosch/shc/Kconfig"
1881 source "board/bosch/guardian/Kconfig"
1882 source "board/CarMediaLab/flea3/Kconfig"
1883 source "board/Marvell/aspenite/Kconfig"
1884 source "board/Marvell/gplugd/Kconfig"
1885 source "board/armadeus/apf27/Kconfig"
1886 source "board/armltd/vexpress/Kconfig"
1887 source "board/armltd/vexpress64/Kconfig"
1888 source "board/cortina/presidio-asic/Kconfig"
1889 source "board/broadcom/bcm23550_w1d/Kconfig"
1890 source "board/broadcom/bcm28155_ap/Kconfig"
1891 source "board/broadcom/bcm963158/Kconfig"
1892 source "board/broadcom/bcm968360bg/Kconfig"
1893 source "board/broadcom/bcm968580xref/Kconfig"
1894 source "board/broadcom/bcmcygnus/Kconfig"
1895 source "board/broadcom/bcmnsp/Kconfig"
1896 source "board/broadcom/bcmns2/Kconfig"
1897 source "board/cavium/thunderx/Kconfig"
1898 source "board/cirrus/edb93xx/Kconfig"
1899 source "board/eets/pdu001/Kconfig"
1900 source "board/emulation/qemu-arm/Kconfig"
1901 source "board/freescale/ls2080a/Kconfig"
1902 source "board/freescale/ls2080aqds/Kconfig"
1903 source "board/freescale/ls2080ardb/Kconfig"
1904 source "board/freescale/ls1088a/Kconfig"
1905 source "board/freescale/ls1028a/Kconfig"
1906 source "board/freescale/ls1021aqds/Kconfig"
1907 source "board/freescale/ls1043aqds/Kconfig"
1908 source "board/freescale/ls1021atwr/Kconfig"
1909 source "board/freescale/ls1021atsn/Kconfig"
1910 source "board/freescale/ls1021aiot/Kconfig"
1911 source "board/freescale/ls1046aqds/Kconfig"
1912 source "board/freescale/ls1043ardb/Kconfig"
1913 source "board/freescale/ls1046ardb/Kconfig"
1914 source "board/freescale/ls1046afrwy/Kconfig"
1915 source "board/freescale/ls1012aqds/Kconfig"
1916 source "board/freescale/ls1012ardb/Kconfig"
1917 source "board/freescale/ls1012afrdm/Kconfig"
1918 source "board/freescale/lx2160a/Kconfig"
1919 source "board/freescale/mx35pdk/Kconfig"
1920 source "board/freescale/s32v234evb/Kconfig"
1921 source "board/grinn/chiliboard/Kconfig"
1922 source "board/gumstix/pepper/Kconfig"
1923 source "board/hisilicon/hikey/Kconfig"
1924 source "board/hisilicon/hikey960/Kconfig"
1925 source "board/hisilicon/poplar/Kconfig"
1926 source "board/isee/igep003x/Kconfig"
1927 source "board/silica/pengwyn/Kconfig"
1928 source "board/spear/spear300/Kconfig"
1929 source "board/spear/spear310/Kconfig"
1930 source "board/spear/spear320/Kconfig"
1931 source "board/spear/spear600/Kconfig"
1932 source "board/spear/x600/Kconfig"
1933 source "board/st/stv0991/Kconfig"
1934 source "board/tcl/sl50/Kconfig"
1935 source "board/birdland/bav335x/Kconfig"
1936 source "board/toradex/colibri_pxa270/Kconfig"
1937 source "board/variscite/dart_6ul/Kconfig"
1938 source "board/vscom/baltos/Kconfig"
1939 source "board/xilinx/Kconfig"
1940 source "board/xilinx/zynq/Kconfig"
1941 source "board/xilinx/zynqmp/Kconfig"
1942 source "board/phytium/durian/Kconfig"
1944 source "arch/arm/Kconfig.debug"
1949 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
1950 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
1951 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64