5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
10 select SYS_SUPPORTS_APM_EMULATION
11 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
12 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
15 select HAVE_KPROBES if !XIP_KERNEL
16 select HAVE_KRETPROBES if (HAVE_KPROBES)
17 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
18 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
19 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
20 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
21 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
22 select HAVE_GENERIC_DMA_COHERENT
23 select HAVE_KERNEL_GZIP
24 select HAVE_KERNEL_LZO
25 select HAVE_KERNEL_LZMA
28 select HAVE_PERF_EVENTS
29 select PERF_USE_VMALLOC
30 select HAVE_REGS_AND_STACK_ACCESS_API
31 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
32 select HAVE_C_RECORDMCOUNT
33 select HAVE_GENERIC_HARDIRQS
34 select GENERIC_IRQ_SHOW
35 select CPU_PM if (SUSPEND || CPU_IDLE)
36 select GENERIC_PCI_IOMAP
37 select HAVE_BPF_JIT if NET
39 The ARM series is a line of low-power-consumption RISC chip designs
40 licensed by ARM Ltd and targeted at embedded applications and
41 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
42 manufactured, but legacy ARM-based PC hardware remains popular in
43 Europe. There is an ARM Linux project with a web page at
44 <http://www.arm.linux.org.uk/>.
46 config ARM_HAS_SG_CHAIN
55 config SYS_SUPPORTS_APM_EMULATION
61 config ARCH_USES_GETTIMEOFFSET
65 config GENERIC_CLOCKEVENTS
68 config GENERIC_CLOCKEVENTS_BROADCAST
70 depends on GENERIC_CLOCKEVENTS
79 select GENERIC_ALLOCATOR
90 The Extended Industry Standard Architecture (EISA) bus was
91 developed as an open alternative to the IBM MicroChannel bus.
93 The EISA bus provided some of the features of the IBM MicroChannel
94 bus while maintaining backward compatibility with cards made for
95 the older ISA bus. The EISA bus saw limited use between 1988 and
96 1995 when it was made obsolete by the PCI bus.
98 Say Y here if you are building a kernel for an EISA-based machine.
108 MicroChannel Architecture is found in some IBM PS/2 machines and
109 laptops. It is a bus system similar to PCI or ISA. See
110 <file:Documentation/mca.txt> (and especially the web page given
111 there) before attempting to build an MCA bus kernel.
113 config STACKTRACE_SUPPORT
117 config HAVE_LATENCYTOP_SUPPORT
122 config LOCKDEP_SUPPORT
126 config TRACE_IRQFLAGS_SUPPORT
130 config HARDIRQS_SW_RESEND
134 config GENERIC_IRQ_PROBE
138 config GENERIC_LOCKBREAK
141 depends on SMP && PREEMPT
143 config RWSEM_GENERIC_SPINLOCK
147 config RWSEM_XCHGADD_ALGORITHM
150 config ARCH_HAS_ILOG2_U32
153 config ARCH_HAS_ILOG2_U64
156 config ARCH_HAS_CPUFREQ
159 Internal node to signify that the ARCH has CPUFREQ support
160 and that the relevant menu configurations are displayed for
163 config ARCH_HAS_CPU_IDLE_WAIT
166 config GENERIC_HWEIGHT
170 config GENERIC_CALIBRATE_DELAY
174 config ARCH_MAY_HAVE_PC_FDC
180 config NEED_DMA_MAP_STATE
183 config ARCH_HAS_DMA_SET_COHERENT_MASK
186 config GENERIC_ISA_DMA
192 config NEED_RET_TO_USER
200 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
201 default DRAM_BASE if REMAP_VECTORS_TO_RAM
204 The base address of exception vectors.
206 config ARM_PATCH_PHYS_VIRT
207 bool "Patch physical to virtual translations at runtime" if EMBEDDED
209 depends on !XIP_KERNEL && MMU
210 depends on !ARCH_REALVIEW || !SPARSEMEM
212 Patch phys-to-virt and virt-to-phys translation functions at
213 boot and module load time according to the position of the
214 kernel in system memory.
216 This can only be used with non-XIP MMU kernels where the base
217 of physical memory is at a 16MB boundary.
219 Only disable this option if you know that you do not require
220 this feature (eg, building a kernel for a single machine) and
221 you need to shrink the kernel to the minimal size.
223 config NEED_MACH_IO_H
226 Select this when mach/io.h is required to provide special
227 definitions for this platform. The need for mach/io.h should
228 be avoided when possible.
230 config NEED_MACH_MEMORY_H
233 Select this when mach/memory.h is required to provide special
234 definitions for this platform. The need for mach/memory.h should
235 be avoided when possible.
238 hex "Physical address of main memory" if MMU
239 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
240 default DRAM_BASE if !MMU
242 Please provide the physical address corresponding to the
243 location of main memory in your system.
249 source "init/Kconfig"
251 source "kernel/Kconfig.freezer"
256 bool "MMU-based Paged Memory Management Support"
259 Select if you want MMU-based virtualised addressing space
260 support by paged memory management. If unsure, say 'Y'.
263 # The "ARM system type" choice list is ordered alphabetically by option
264 # text. Please add new entries in the option alphabetic order.
267 prompt "ARM system type"
268 default ARCH_VERSATILE
270 config ARCH_INTEGRATOR
271 bool "ARM Ltd. Integrator family"
273 select ARCH_HAS_CPUFREQ
275 select HAVE_MACH_CLKDEV
278 select GENERIC_CLOCKEVENTS
279 select PLAT_VERSATILE
280 select PLAT_VERSATILE_FPGA_IRQ
281 select NEED_MACH_IO_H
282 select NEED_MACH_MEMORY_H
285 Support for ARM's Integrator platform.
288 bool "ARM Ltd. RealView family"
291 select HAVE_MACH_CLKDEV
293 select GENERIC_CLOCKEVENTS
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLCD
297 select ARM_TIMER_SP804
298 select GPIO_PL061 if GPIOLIB
299 select NEED_MACH_MEMORY_H
301 This enables support for ARM Ltd RealView boards.
303 config ARCH_VERSATILE
304 bool "ARM Ltd. Versatile family"
308 select HAVE_MACH_CLKDEV
310 select GENERIC_CLOCKEVENTS
311 select ARCH_WANT_OPTIONAL_GPIOLIB
312 select PLAT_VERSATILE
313 select PLAT_VERSATILE_CLCD
314 select PLAT_VERSATILE_FPGA_IRQ
315 select ARM_TIMER_SP804
317 This enables support for ARM Ltd Versatile board.
320 bool "ARM Ltd. Versatile Express family"
321 select ARCH_WANT_OPTIONAL_GPIOLIB
323 select ARM_TIMER_SP804
325 select HAVE_MACH_CLKDEV
326 select GENERIC_CLOCKEVENTS
328 select HAVE_PATA_PLATFORM
331 select PLAT_VERSATILE
332 select PLAT_VERSATILE_CLCD
334 This enables support for the ARM Ltd Versatile Express boards.
338 select ARCH_REQUIRE_GPIOLIB
342 select NEED_MACH_IO_H if PCCARD
344 This enables support for systems based on the Atmel AT91RM9200,
348 bool "Broadcom BCMRING"
352 select ARM_TIMER_SP804
354 select GENERIC_CLOCKEVENTS
355 select ARCH_WANT_OPTIONAL_GPIOLIB
357 Support for Broadcom's BCMRing platform.
360 bool "Calxeda Highbank-based"
361 select ARCH_WANT_OPTIONAL_GPIOLIB
364 select ARM_TIMER_SP804
368 select GENERIC_CLOCKEVENTS
374 Support for the Calxeda Highbank SoC based boards.
377 bool "Cirrus Logic CLPS711x/EP721x-based"
379 select ARCH_USES_GETTIMEOFFSET
380 select NEED_MACH_MEMORY_H
382 Support for Cirrus Logic 711x/721x based boards.
385 bool "Cavium Networks CNS3XXX family"
387 select GENERIC_CLOCKEVENTS
389 select MIGHT_HAVE_CACHE_L2X0
390 select MIGHT_HAVE_PCI
391 select PCI_DOMAINS if PCI
393 Support for Cavium Networks CNS3XXX platform.
396 bool "Cortina Systems Gemini"
398 select ARCH_REQUIRE_GPIOLIB
399 select ARCH_USES_GETTIMEOFFSET
401 Support for the Cortina Systems Gemini family SoCs
404 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
407 select GENERIC_CLOCKEVENTS
409 select GENERIC_IRQ_CHIP
410 select MIGHT_HAVE_CACHE_L2X0
414 Support for CSR SiRFSoC ARM Cortex A9 Platform
421 select ARCH_USES_GETTIMEOFFSET
422 select NEED_MACH_IO_H
423 select NEED_MACH_MEMORY_H
425 This is an evaluation board for the StrongARM processor available
426 from Digital. It has limited hardware on-board, including an
427 Ethernet interface, two PCMCIA sockets, two serial ports and a
436 select ARCH_REQUIRE_GPIOLIB
437 select ARCH_HAS_HOLES_MEMORYMODEL
438 select ARCH_USES_GETTIMEOFFSET
439 select NEED_MACH_MEMORY_H
441 This enables support for the Cirrus EP93xx series of CPUs.
443 config ARCH_FOOTBRIDGE
447 select GENERIC_CLOCKEVENTS
449 select NEED_MACH_IO_H
450 select NEED_MACH_MEMORY_H
452 Support for systems based on the DC21285 companion chip
453 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
456 bool "Freescale MXC/iMX-based"
457 select GENERIC_CLOCKEVENTS
458 select ARCH_REQUIRE_GPIOLIB
461 select GENERIC_IRQ_CHIP
462 select MULTI_IRQ_HANDLER
464 Support for Freescale MXC/iMX-based family of processors
467 bool "Freescale MXS-based"
468 select GENERIC_CLOCKEVENTS
469 select ARCH_REQUIRE_GPIOLIB
472 select HAVE_CLK_PREPARE
474 Support for Freescale MXS-based family of processors
477 bool "Hilscher NetX based"
481 select GENERIC_CLOCKEVENTS
483 This enables support for systems based on the Hilscher NetX Soc
486 bool "Hynix HMS720x-based"
489 select ARCH_USES_GETTIMEOFFSET
491 This enables support for systems based on the Hynix HMS720x
499 select ARCH_SUPPORTS_MSI
501 select NEED_MACH_IO_H
502 select NEED_MACH_MEMORY_H
503 select NEED_RET_TO_USER
505 Support for Intel's IOP13XX (XScale) family of processors.
511 select NEED_MACH_IO_H
512 select NEED_RET_TO_USER
515 select ARCH_REQUIRE_GPIOLIB
517 Support for Intel's 80219 and IOP32X (XScale) family of
524 select NEED_MACH_IO_H
525 select NEED_RET_TO_USER
528 select ARCH_REQUIRE_GPIOLIB
530 Support for Intel's IOP33X (XScale) family of processors.
537 select ARCH_USES_GETTIMEOFFSET
538 select NEED_MACH_IO_H
539 select NEED_MACH_MEMORY_H
541 Support for Intel's IXP23xx (XScale) family of processors.
544 bool "IXP2400/2800-based"
548 select ARCH_USES_GETTIMEOFFSET
549 select NEED_MACH_IO_H
550 select NEED_MACH_MEMORY_H
552 Support for Intel's IXP2400/2800 (XScale) family of processors.
557 select ARCH_HAS_DMA_SET_COHERENT_MASK
561 select GENERIC_CLOCKEVENTS
562 select MIGHT_HAVE_PCI
563 select NEED_MACH_IO_H
564 select DMABOUNCE if PCI
566 Support for Intel's IXP4XX (XScale) family of processors.
572 select ARCH_REQUIRE_GPIOLIB
573 select GENERIC_CLOCKEVENTS
574 select NEED_MACH_IO_H
577 Support for the Marvell Dove SoC 88AP510
580 bool "Marvell Kirkwood"
583 select ARCH_REQUIRE_GPIOLIB
584 select GENERIC_CLOCKEVENTS
585 select NEED_MACH_IO_H
588 Support for the following Marvell Kirkwood series SoCs:
589 88F6180, 88F6192 and 88F6281.
595 select ARCH_REQUIRE_GPIOLIB
598 select USB_ARCH_HAS_OHCI
600 select GENERIC_CLOCKEVENTS
602 Support for the NXP LPC32XX family of processors
605 bool "Marvell MV78xx0"
608 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
610 select NEED_MACH_IO_H
613 Support for the following Marvell MV78xx0 series SoCs:
621 select ARCH_REQUIRE_GPIOLIB
622 select GENERIC_CLOCKEVENTS
625 Support for the following Marvell Orion 5x series SoCs:
626 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
627 Orion-2 (5281), Orion-1-90 (6183).
630 bool "Marvell PXA168/910/MMP2"
632 select ARCH_REQUIRE_GPIOLIB
634 select GENERIC_CLOCKEVENTS
639 select GENERIC_ALLOCATOR
641 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
644 bool "Micrel/Kendin KS8695"
646 select ARCH_REQUIRE_GPIOLIB
647 select ARCH_USES_GETTIMEOFFSET
648 select NEED_MACH_MEMORY_H
650 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
651 System-on-Chip devices.
654 bool "Nuvoton W90X900 CPU"
656 select ARCH_REQUIRE_GPIOLIB
659 select GENERIC_CLOCKEVENTS
661 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
662 At present, the w90x900 has been renamed nuc900, regarding
663 the ARM series product line, you can login the following
664 link address to know more.
666 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
667 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
673 select GENERIC_CLOCKEVENTS
677 select MIGHT_HAVE_CACHE_L2X0
678 select NEED_MACH_IO_H if PCI
679 select ARCH_HAS_CPUFREQ
681 This enables support for NVIDIA Tegra based systems (Tegra APX,
682 Tegra 6xx and Tegra 2 series).
684 config ARCH_PICOXCELL
685 bool "Picochip picoXcell"
686 select ARCH_REQUIRE_GPIOLIB
687 select ARM_PATCH_PHYS_VIRT
691 select GENERIC_CLOCKEVENTS
698 This enables support for systems based on the Picochip picoXcell
699 family of Femtocell devices. The picoxcell support requires device tree
703 bool "Philips Nexperia PNX4008 Mobile"
706 select ARCH_USES_GETTIMEOFFSET
708 This enables support for Philips PNX4008 mobile platform.
711 bool "PXA2xx/PXA3xx-based"
714 select ARCH_HAS_CPUFREQ
717 select ARCH_REQUIRE_GPIOLIB
718 select GENERIC_CLOCKEVENTS
724 select MULTI_IRQ_HANDLER
725 select ARM_CPU_SUSPEND if PM
728 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
733 select GENERIC_CLOCKEVENTS
734 select ARCH_REQUIRE_GPIOLIB
737 Support for Qualcomm MSM/QSD based systems. This runs on the
738 apps processor of the MSM/QSD and depends on a shared memory
739 interface to the modem processor which runs the baseband
740 stack and controls some vital subsystems
741 (clock and power control, etc).
744 bool "Renesas SH-Mobile / R-Mobile"
747 select HAVE_MACH_CLKDEV
749 select GENERIC_CLOCKEVENTS
750 select MIGHT_HAVE_CACHE_L2X0
753 select MULTI_IRQ_HANDLER
754 select PM_GENERIC_DOMAINS if PM
755 select NEED_MACH_MEMORY_H
757 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
763 select ARCH_MAY_HAVE_PC_FDC
764 select HAVE_PATA_PLATFORM
767 select ARCH_SPARSEMEM_ENABLE
768 select ARCH_USES_GETTIMEOFFSET
770 select NEED_MACH_IO_H
771 select NEED_MACH_MEMORY_H
773 On the Acorn Risc-PC, Linux can support the internal IDE disk and
774 CD-ROM interface, serial and parallel port, and the floppy drive.
781 select ARCH_SPARSEMEM_ENABLE
783 select ARCH_HAS_CPUFREQ
785 select GENERIC_CLOCKEVENTS
788 select ARCH_REQUIRE_GPIOLIB
790 select NEED_MACH_MEMORY_H
793 Support for StrongARM 11x0 based boards.
796 bool "Samsung S3C24XX SoCs"
798 select ARCH_HAS_CPUFREQ
801 select ARCH_USES_GETTIMEOFFSET
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C_RTC if RTC_CLASS
804 select HAVE_S3C2410_WATCHDOG if WATCHDOG
805 select NEED_MACH_IO_H
807 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
808 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
809 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
810 Samsung SMDK2410 development board (and derivatives).
813 bool "Samsung S3C64XX"
821 select ARCH_USES_GETTIMEOFFSET
822 select ARCH_HAS_CPUFREQ
823 select ARCH_REQUIRE_GPIOLIB
824 select SAMSUNG_CLKSRC
825 select SAMSUNG_IRQ_VIC_TIMER
826 select S3C_GPIO_TRACK
828 select USB_ARCH_HAS_OHCI
829 select SAMSUNG_GPIOLIB_4BIT
830 select HAVE_S3C2410_I2C if I2C
831 select HAVE_S3C2410_WATCHDOG if WATCHDOG
833 Samsung S3C64XX series based systems
836 bool "Samsung S5P6440 S5P6450"
842 select HAVE_S3C2410_WATCHDOG if WATCHDOG
843 select GENERIC_CLOCKEVENTS
844 select HAVE_S3C2410_I2C if I2C
845 select HAVE_S3C_RTC if RTC_CLASS
847 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
851 bool "Samsung S5PC100"
856 select ARCH_USES_GETTIMEOFFSET
857 select HAVE_S3C2410_I2C if I2C
858 select HAVE_S3C_RTC if RTC_CLASS
859 select HAVE_S3C2410_WATCHDOG if WATCHDOG
861 Samsung S5PC100 series based systems
864 bool "Samsung S5PV210/S5PC110"
866 select ARCH_SPARSEMEM_ENABLE
867 select ARCH_HAS_HOLES_MEMORYMODEL
872 select ARCH_HAS_CPUFREQ
873 select GENERIC_CLOCKEVENTS
874 select HAVE_S3C2410_I2C if I2C
875 select HAVE_S3C_RTC if RTC_CLASS
876 select HAVE_S3C2410_WATCHDOG if WATCHDOG
877 select NEED_MACH_MEMORY_H
879 Samsung S5PV210/S5PC110 series based systems
882 bool "SAMSUNG EXYNOS"
884 select ARCH_SPARSEMEM_ENABLE
885 select ARCH_HAS_HOLES_MEMORYMODEL
889 select ARCH_HAS_CPUFREQ
890 select GENERIC_CLOCKEVENTS
891 select HAVE_S3C_RTC if RTC_CLASS
892 select HAVE_S3C2410_I2C if I2C
893 select HAVE_S3C2410_WATCHDOG if WATCHDOG
894 select NEED_MACH_MEMORY_H
896 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
905 select ARCH_USES_GETTIMEOFFSET
906 select NEED_MACH_MEMORY_H
907 select NEED_MACH_IO_H
909 Support for the StrongARM based Digital DNARD machine, also known
910 as "Shark" (<http://www.shark-linux.de/shark.html>).
913 bool "ST-Ericsson U300 Series"
919 select ARM_PATCH_PHYS_VIRT
921 select GENERIC_CLOCKEVENTS
923 select HAVE_MACH_CLKDEV
925 select ARCH_REQUIRE_GPIOLIB
927 Support for ST-Ericsson U300 series mobile platforms.
930 bool "ST-Ericsson U8500 Series"
934 select GENERIC_CLOCKEVENTS
936 select ARCH_REQUIRE_GPIOLIB
937 select ARCH_HAS_CPUFREQ
939 select MIGHT_HAVE_CACHE_L2X0
941 Support for ST-Ericsson's Ux500 architecture
944 bool "STMicroelectronics Nomadik"
949 select GENERIC_CLOCKEVENTS
950 select MIGHT_HAVE_CACHE_L2X0
951 select ARCH_REQUIRE_GPIOLIB
953 Support for the Nomadik platform by ST-Ericsson
957 select GENERIC_CLOCKEVENTS
958 select ARCH_REQUIRE_GPIOLIB
962 select GENERIC_ALLOCATOR
963 select GENERIC_IRQ_CHIP
964 select ARCH_HAS_HOLES_MEMORYMODEL
966 Support for TI's DaVinci platform.
971 select ARCH_REQUIRE_GPIOLIB
972 select ARCH_HAS_CPUFREQ
974 select GENERIC_CLOCKEVENTS
975 select ARCH_HAS_HOLES_MEMORYMODEL
977 Support for TI's OMAP platform (OMAP1/2/3/4).
982 select ARCH_REQUIRE_GPIOLIB
985 select GENERIC_CLOCKEVENTS
988 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
991 bool "VIA/WonderMedia 85xx"
994 select ARCH_HAS_CPUFREQ
995 select GENERIC_CLOCKEVENTS
996 select ARCH_REQUIRE_GPIOLIB
999 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1002 bool "Xilinx Zynq ARM Cortex A9 Platform"
1004 select GENERIC_CLOCKEVENTS
1005 select CLKDEV_LOOKUP
1009 select MIGHT_HAVE_CACHE_L2X0
1012 Support for Xilinx Zynq ARM Cortex A9 Platform
1016 # This is sorted alphabetically by mach-* pathname. However, plat-*
1017 # Kconfigs may be included either alphabetically (according to the
1018 # plat- suffix) or along side the corresponding mach-* source.
1020 source "arch/arm/mach-at91/Kconfig"
1022 source "arch/arm/mach-bcmring/Kconfig"
1024 source "arch/arm/mach-clps711x/Kconfig"
1026 source "arch/arm/mach-cns3xxx/Kconfig"
1028 source "arch/arm/mach-davinci/Kconfig"
1030 source "arch/arm/mach-dove/Kconfig"
1032 source "arch/arm/mach-ep93xx/Kconfig"
1034 source "arch/arm/mach-footbridge/Kconfig"
1036 source "arch/arm/mach-gemini/Kconfig"
1038 source "arch/arm/mach-h720x/Kconfig"
1040 source "arch/arm/mach-integrator/Kconfig"
1042 source "arch/arm/mach-iop32x/Kconfig"
1044 source "arch/arm/mach-iop33x/Kconfig"
1046 source "arch/arm/mach-iop13xx/Kconfig"
1048 source "arch/arm/mach-ixp4xx/Kconfig"
1050 source "arch/arm/mach-ixp2000/Kconfig"
1052 source "arch/arm/mach-ixp23xx/Kconfig"
1054 source "arch/arm/mach-kirkwood/Kconfig"
1056 source "arch/arm/mach-ks8695/Kconfig"
1058 source "arch/arm/mach-lpc32xx/Kconfig"
1060 source "arch/arm/mach-msm/Kconfig"
1062 source "arch/arm/mach-mv78xx0/Kconfig"
1064 source "arch/arm/plat-mxc/Kconfig"
1066 source "arch/arm/mach-mxs/Kconfig"
1068 source "arch/arm/mach-netx/Kconfig"
1070 source "arch/arm/mach-nomadik/Kconfig"
1071 source "arch/arm/plat-nomadik/Kconfig"
1073 source "arch/arm/plat-omap/Kconfig"
1075 source "arch/arm/mach-omap1/Kconfig"
1077 source "arch/arm/mach-omap2/Kconfig"
1079 source "arch/arm/mach-orion5x/Kconfig"
1081 source "arch/arm/mach-pxa/Kconfig"
1082 source "arch/arm/plat-pxa/Kconfig"
1084 source "arch/arm/mach-mmp/Kconfig"
1086 source "arch/arm/mach-realview/Kconfig"
1088 source "arch/arm/mach-sa1100/Kconfig"
1090 source "arch/arm/plat-samsung/Kconfig"
1091 source "arch/arm/plat-s3c24xx/Kconfig"
1092 source "arch/arm/plat-s5p/Kconfig"
1094 source "arch/arm/plat-spear/Kconfig"
1096 source "arch/arm/mach-s3c24xx/Kconfig"
1098 source "arch/arm/mach-s3c2412/Kconfig"
1099 source "arch/arm/mach-s3c2440/Kconfig"
1103 source "arch/arm/mach-s3c64xx/Kconfig"
1106 source "arch/arm/mach-s5p64x0/Kconfig"
1108 source "arch/arm/mach-s5pc100/Kconfig"
1110 source "arch/arm/mach-s5pv210/Kconfig"
1112 source "arch/arm/mach-exynos/Kconfig"
1114 source "arch/arm/mach-shmobile/Kconfig"
1116 source "arch/arm/mach-tegra/Kconfig"
1118 source "arch/arm/mach-u300/Kconfig"
1120 source "arch/arm/mach-ux500/Kconfig"
1122 source "arch/arm/mach-versatile/Kconfig"
1124 source "arch/arm/mach-vexpress/Kconfig"
1125 source "arch/arm/plat-versatile/Kconfig"
1127 source "arch/arm/mach-vt8500/Kconfig"
1129 source "arch/arm/mach-w90x900/Kconfig"
1131 # Definitions to make life easier
1137 select GENERIC_CLOCKEVENTS
1142 select GENERIC_IRQ_CHIP
1147 config PLAT_VERSATILE
1150 config ARM_TIMER_SP804
1153 select HAVE_SCHED_CLOCK
1155 source arch/arm/mm/Kconfig
1159 default 16 if ARCH_EP93XX
1163 bool "Enable iWMMXt support"
1164 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1165 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1167 Enable support for iWMMXt context switching at run time if
1168 running on a CPU that supports it.
1172 depends on CPU_XSCALE
1176 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1177 (!ARCH_OMAP3 || OMAP3_EMU)
1181 config MULTI_IRQ_HANDLER
1184 Allow each machine to specify it's own IRQ handler at run time.
1187 source "arch/arm/Kconfig-nommu"
1190 config ARM_ERRATA_326103
1191 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1194 Executing a SWP instruction to read-only memory does not set bit 11
1195 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1196 treat the access as a read, preventing a COW from occurring and
1197 causing the faulting task to livelock.
1199 config ARM_ERRATA_411920
1200 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1201 depends on CPU_V6 || CPU_V6K
1203 Invalidation of the Instruction Cache operation can
1204 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1205 It does not affect the MPCore. This option enables the ARM Ltd.
1206 recommended workaround.
1208 config ARM_ERRATA_430973
1209 bool "ARM errata: Stale prediction on replaced interworking branch"
1212 This option enables the workaround for the 430973 Cortex-A8
1213 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1214 interworking branch is replaced with another code sequence at the
1215 same virtual address, whether due to self-modifying code or virtual
1216 to physical address re-mapping, Cortex-A8 does not recover from the
1217 stale interworking branch prediction. This results in Cortex-A8
1218 executing the new code sequence in the incorrect ARM or Thumb state.
1219 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1220 and also flushes the branch target cache at every context switch.
1221 Note that setting specific bits in the ACTLR register may not be
1222 available in non-secure mode.
1224 config ARM_ERRATA_458693
1225 bool "ARM errata: Processor deadlock when a false hazard is created"
1228 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1229 erratum. For very specific sequences of memory operations, it is
1230 possible for a hazard condition intended for a cache line to instead
1231 be incorrectly associated with a different cache line. This false
1232 hazard might then cause a processor deadlock. The workaround enables
1233 the L1 caching of the NEON accesses and disables the PLD instruction
1234 in the ACTLR register. Note that setting specific bits in the ACTLR
1235 register may not be available in non-secure mode.
1237 config ARM_ERRATA_460075
1238 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1241 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1242 erratum. Any asynchronous access to the L2 cache may encounter a
1243 situation in which recent store transactions to the L2 cache are lost
1244 and overwritten with stale memory contents from external memory. The
1245 workaround disables the write-allocate mode for the L2 cache via the
1246 ACTLR register. Note that setting specific bits in the ACTLR register
1247 may not be available in non-secure mode.
1249 config ARM_ERRATA_742230
1250 bool "ARM errata: DMB operation may be faulty"
1251 depends on CPU_V7 && SMP
1253 This option enables the workaround for the 742230 Cortex-A9
1254 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1255 between two write operations may not ensure the correct visibility
1256 ordering of the two writes. This workaround sets a specific bit in
1257 the diagnostic register of the Cortex-A9 which causes the DMB
1258 instruction to behave as a DSB, ensuring the correct behaviour of
1261 config ARM_ERRATA_742231
1262 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1263 depends on CPU_V7 && SMP
1265 This option enables the workaround for the 742231 Cortex-A9
1266 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1267 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1268 accessing some data located in the same cache line, may get corrupted
1269 data due to bad handling of the address hazard when the line gets
1270 replaced from one of the CPUs at the same time as another CPU is
1271 accessing it. This workaround sets specific bits in the diagnostic
1272 register of the Cortex-A9 which reduces the linefill issuing
1273 capabilities of the processor.
1275 config PL310_ERRATA_588369
1276 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1277 depends on CACHE_L2X0
1279 The PL310 L2 cache controller implements three types of Clean &
1280 Invalidate maintenance operations: by Physical Address
1281 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1282 They are architecturally defined to behave as the execution of a
1283 clean operation followed immediately by an invalidate operation,
1284 both performing to the same memory location. This functionality
1285 is not correctly implemented in PL310 as clean lines are not
1286 invalidated as a result of these operations.
1288 config ARM_ERRATA_720789
1289 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1292 This option enables the workaround for the 720789 Cortex-A9 (prior to
1293 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1294 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1295 As a consequence of this erratum, some TLB entries which should be
1296 invalidated are not, resulting in an incoherency in the system page
1297 tables. The workaround changes the TLB flushing routines to invalidate
1298 entries regardless of the ASID.
1300 config PL310_ERRATA_727915
1301 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1302 depends on CACHE_L2X0
1304 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1305 operation (offset 0x7FC). This operation runs in background so that
1306 PL310 can handle normal accesses while it is in progress. Under very
1307 rare circumstances, due to this erratum, write data can be lost when
1308 PL310 treats a cacheable write transaction during a Clean &
1309 Invalidate by Way operation.
1311 config ARM_ERRATA_743622
1312 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1315 This option enables the workaround for the 743622 Cortex-A9
1316 (r2p*) erratum. Under very rare conditions, a faulty
1317 optimisation in the Cortex-A9 Store Buffer may lead to data
1318 corruption. This workaround sets a specific bit in the diagnostic
1319 register of the Cortex-A9 which disables the Store Buffer
1320 optimisation, preventing the defect from occurring. This has no
1321 visible impact on the overall performance or power consumption of the
1324 config ARM_ERRATA_751472
1325 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1328 This option enables the workaround for the 751472 Cortex-A9 (prior
1329 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1330 completion of a following broadcasted operation if the second
1331 operation is received by a CPU before the ICIALLUIS has completed,
1332 potentially leading to corrupted entries in the cache or TLB.
1334 config PL310_ERRATA_753970
1335 bool "PL310 errata: cache sync operation may be faulty"
1336 depends on CACHE_PL310
1338 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1340 Under some condition the effect of cache sync operation on
1341 the store buffer still remains when the operation completes.
1342 This means that the store buffer is always asked to drain and
1343 this prevents it from merging any further writes. The workaround
1344 is to replace the normal offset of cache sync operation (0x730)
1345 by another offset targeting an unmapped PL310 register 0x740.
1346 This has the same effect as the cache sync operation: store buffer
1347 drain and waiting for all buffers empty.
1349 config ARM_ERRATA_754322
1350 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1353 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1354 r3p*) erratum. A speculative memory access may cause a page table walk
1355 which starts prior to an ASID switch but completes afterwards. This
1356 can populate the micro-TLB with a stale entry which may be hit with
1357 the new ASID. This workaround places two dsb instructions in the mm
1358 switching code so that no page table walks can cross the ASID switch.
1360 config ARM_ERRATA_754327
1361 bool "ARM errata: no automatic Store Buffer drain"
1362 depends on CPU_V7 && SMP
1364 This option enables the workaround for the 754327 Cortex-A9 (prior to
1365 r2p0) erratum. The Store Buffer does not have any automatic draining
1366 mechanism and therefore a livelock may occur if an external agent
1367 continuously polls a memory location waiting to observe an update.
1368 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1369 written polling loops from denying visibility of updates to memory.
1371 config ARM_ERRATA_364296
1372 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1373 depends on CPU_V6 && !SMP
1375 This options enables the workaround for the 364296 ARM1136
1376 r0p2 erratum (possible cache data corruption with
1377 hit-under-miss enabled). It sets the undocumented bit 31 in
1378 the auxiliary control register and the FI bit in the control
1379 register, thus disabling hit-under-miss without putting the
1380 processor into full low interrupt latency mode. ARM11MPCore
1383 config ARM_ERRATA_764369
1384 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1385 depends on CPU_V7 && SMP
1387 This option enables the workaround for erratum 764369
1388 affecting Cortex-A9 MPCore with two or more processors (all
1389 current revisions). Under certain timing circumstances, a data
1390 cache line maintenance operation by MVA targeting an Inner
1391 Shareable memory region may fail to proceed up to either the
1392 Point of Coherency or to the Point of Unification of the
1393 system. This workaround adds a DSB instruction before the
1394 relevant cache maintenance functions and sets a specific bit
1395 in the diagnostic control register of the SCU.
1397 config PL310_ERRATA_769419
1398 bool "PL310 errata: no automatic Store Buffer drain"
1399 depends on CACHE_L2X0
1401 On revisions of the PL310 prior to r3p2, the Store Buffer does
1402 not automatically drain. This can cause normal, non-cacheable
1403 writes to be retained when the memory system is idle, leading
1404 to suboptimal I/O performance for drivers using coherent DMA.
1405 This option adds a write barrier to the cpu_idle loop so that,
1406 on systems with an outer cache, the store buffer is drained
1411 source "arch/arm/common/Kconfig"
1421 Find out whether you have ISA slots on your motherboard. ISA is the
1422 name of a bus system, i.e. the way the CPU talks to the other stuff
1423 inside your box. Other bus systems are PCI, EISA, MicroChannel
1424 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1425 newer boards don't support it. If you have ISA, say Y, otherwise N.
1427 # Select ISA DMA controller support
1432 # Select ISA DMA interface
1437 bool "PCI support" if MIGHT_HAVE_PCI
1439 Find out whether you have a PCI motherboard. PCI is the name of a
1440 bus system, i.e. the way the CPU talks to the other stuff inside
1441 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1442 VESA. If you have PCI, say Y, otherwise N.
1448 config PCI_NANOENGINE
1449 bool "BSE nanoEngine PCI support"
1450 depends on SA1100_NANOENGINE
1452 Enable PCI on the BSE nanoEngine board.
1457 # Select the host bridge type
1458 config PCI_HOST_VIA82C505
1460 depends on PCI && ARCH_SHARK
1463 config PCI_HOST_ITE8152
1465 depends on PCI && MACH_ARMCORE
1469 source "drivers/pci/Kconfig"
1471 source "drivers/pcmcia/Kconfig"
1475 menu "Kernel Features"
1477 source "kernel/time/Kconfig"
1482 This option should be selected by machines which have an SMP-
1485 The only effect of this option is to make the SMP-related
1486 options available to the user for configuration.
1489 bool "Symmetric Multi-Processing"
1490 depends on CPU_V6K || CPU_V7
1491 depends on GENERIC_CLOCKEVENTS
1494 select USE_GENERIC_SMP_HELPERS
1495 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1497 This enables support for systems with more than one CPU. If you have
1498 a system with only one CPU, like most personal computers, say N. If
1499 you have a system with more than one CPU, say Y.
1501 If you say N here, the kernel will run on single and multiprocessor
1502 machines, but will use only one CPU of a multiprocessor machine. If
1503 you say Y here, the kernel will run on many, but not all, single
1504 processor machines. On a single processor machine, the kernel will
1505 run faster if you say N here.
1507 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1508 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1509 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1511 If you don't know what to do here, say N.
1514 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1515 depends on EXPERIMENTAL
1516 depends on SMP && !XIP_KERNEL
1519 SMP kernels contain instructions which fail on non-SMP processors.
1520 Enabling this option allows the kernel to modify itself to make
1521 these instructions safe. Disabling it allows about 1K of space
1524 If you don't know what to do here, say Y.
1526 config ARM_CPU_TOPOLOGY
1527 bool "Support cpu topology definition"
1528 depends on SMP && CPU_V7
1531 Support ARM cpu topology definition. The MPIDR register defines
1532 affinity between processors which is then used to describe the cpu
1533 topology of an ARM System.
1536 bool "Multi-core scheduler support"
1537 depends on ARM_CPU_TOPOLOGY
1539 Multi-core scheduler support improves the CPU scheduler's decision
1540 making when dealing with multi-core CPU chips at a cost of slightly
1541 increased overhead in some places. If unsure say N here.
1544 bool "SMT scheduler support"
1545 depends on ARM_CPU_TOPOLOGY
1547 Improves the CPU scheduler's decision making when dealing with
1548 MultiThreading at a cost of slightly increased overhead in some
1549 places. If unsure say N here.
1554 This option enables support for the ARM system coherency unit
1561 This options enables support for the ARM timer and watchdog unit
1564 prompt "Memory split"
1567 Select the desired split between kernel and user memory.
1569 If you are not absolutely sure what you are doing, leave this
1573 bool "3G/1G user/kernel split"
1575 bool "2G/2G user/kernel split"
1577 bool "1G/3G user/kernel split"
1582 default 0x40000000 if VMSPLIT_1G
1583 default 0x80000000 if VMSPLIT_2G
1587 int "Maximum number of CPUs (2-32)"
1593 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1594 depends on SMP && HOTPLUG && EXPERIMENTAL
1596 Say Y here to experiment with turning CPUs off and on. CPUs
1597 can be controlled through /sys/devices/system/cpu.
1600 bool "Use local timer interrupts"
1603 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1605 Enable support for local timers on SMP platforms, rather then the
1606 legacy IPI broadcast method. Local timers allows the system
1607 accounting to be spread across the timer interval, preventing a
1608 "thundering herd" at every timer tick.
1612 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1613 default 355 if ARCH_U8500
1614 default 264 if MACH_H4700
1617 Maximum number of GPIOs in the system.
1619 If unsure, leave the default value.
1621 source kernel/Kconfig.preempt
1625 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1626 ARCH_S5PV210 || ARCH_EXYNOS4
1627 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1628 default AT91_TIMER_HZ if ARCH_AT91
1629 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1632 config THUMB2_KERNEL
1633 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1634 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1636 select ARM_ASM_UNIFIED
1639 By enabling this option, the kernel will be compiled in
1640 Thumb-2 mode. A compiler/assembler that understand the unified
1641 ARM-Thumb syntax is needed.
1645 config THUMB2_AVOID_R_ARM_THM_JUMP11
1646 bool "Work around buggy Thumb-2 short branch relocations in gas"
1647 depends on THUMB2_KERNEL && MODULES
1650 Various binutils versions can resolve Thumb-2 branches to
1651 locally-defined, preemptible global symbols as short-range "b.n"
1652 branch instructions.
1654 This is a problem, because there's no guarantee the final
1655 destination of the symbol, or any candidate locations for a
1656 trampoline, are within range of the branch. For this reason, the
1657 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1658 relocation in modules at all, and it makes little sense to add
1661 The symptom is that the kernel fails with an "unsupported
1662 relocation" error when loading some modules.
1664 Until fixed tools are available, passing
1665 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1666 code which hits this problem, at the cost of a bit of extra runtime
1667 stack usage in some cases.
1669 The problem is described in more detail at:
1670 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1672 Only Thumb-2 kernels are affected.
1674 Unless you are sure your tools don't have this problem, say Y.
1676 config ARM_ASM_UNIFIED
1680 bool "Use the ARM EABI to compile the kernel"
1682 This option allows for the kernel to be compiled using the latest
1683 ARM ABI (aka EABI). This is only useful if you are using a user
1684 space environment that is also compiled with EABI.
1686 Since there are major incompatibilities between the legacy ABI and
1687 EABI, especially with regard to structure member alignment, this
1688 option also changes the kernel syscall calling convention to
1689 disambiguate both ABIs and allow for backward compatibility support
1690 (selected with CONFIG_OABI_COMPAT).
1692 To use this you need GCC version 4.0.0 or later.
1695 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1696 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1699 This option preserves the old syscall interface along with the
1700 new (ARM EABI) one. It also provides a compatibility layer to
1701 intercept syscalls that have structure arguments which layout
1702 in memory differs between the legacy ABI and the new ARM EABI
1703 (only for non "thumb" binaries). This option adds a tiny
1704 overhead to all syscalls and produces a slightly larger kernel.
1705 If you know you'll be using only pure EABI user space then you
1706 can say N here. If this option is not selected and you attempt
1707 to execute a legacy ABI binary then the result will be
1708 UNPREDICTABLE (in fact it can be predicted that it won't work
1709 at all). If in doubt say Y.
1711 config ARCH_HAS_HOLES_MEMORYMODEL
1714 config ARCH_SPARSEMEM_ENABLE
1717 config ARCH_SPARSEMEM_DEFAULT
1718 def_bool ARCH_SPARSEMEM_ENABLE
1720 config ARCH_SELECT_MEMORY_MODEL
1721 def_bool ARCH_SPARSEMEM_ENABLE
1723 config HAVE_ARCH_PFN_VALID
1724 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1727 bool "High Memory Support"
1730 The address space of ARM processors is only 4 Gigabytes large
1731 and it has to accommodate user address space, kernel address
1732 space as well as some memory mapped IO. That means that, if you
1733 have a large amount of physical memory and/or IO, not all of the
1734 memory can be "permanently mapped" by the kernel. The physical
1735 memory that is not permanently mapped is called "high memory".
1737 Depending on the selected kernel/user memory split, minimum
1738 vmalloc space and actual amount of RAM, you may not need this
1739 option which should result in a slightly faster kernel.
1744 bool "Allocate 2nd-level pagetables from highmem"
1747 config HW_PERF_EVENTS
1748 bool "Enable hardware performance counter support for perf events"
1749 depends on PERF_EVENTS && CPU_HAS_PMU
1752 Enable hardware performance counter support for perf events. If
1753 disabled, perf events will use software events only.
1757 config FORCE_MAX_ZONEORDER
1758 int "Maximum zone order" if ARCH_SHMOBILE
1759 range 11 64 if ARCH_SHMOBILE
1760 default "9" if SA1111
1763 The kernel memory allocator divides physically contiguous memory
1764 blocks into "zones", where each zone is a power of two number of
1765 pages. This option selects the largest power of two that the kernel
1766 keeps in the memory allocator. If you need to allocate very large
1767 blocks of physically contiguous memory, then you may need to
1768 increase this value.
1770 This config option is actually maximum order plus one. For example,
1771 a value of 11 means that the largest free memory block is 2^10 pages.
1774 bool "Timer and CPU usage LEDs"
1775 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1776 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1777 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1778 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1779 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1780 ARCH_AT91 || ARCH_DAVINCI || \
1781 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1783 If you say Y here, the LEDs on your machine will be used
1784 to provide useful information about your current system status.
1786 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1787 be able to select which LEDs are active using the options below. If
1788 you are compiling a kernel for the EBSA-110 or the LART however, the
1789 red LED will simply flash regularly to indicate that the system is
1790 still functional. It is safe to say Y here if you have a CATS
1791 system, but the driver will do nothing.
1794 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1795 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1796 || MACH_OMAP_PERSEUS2
1798 depends on !GENERIC_CLOCKEVENTS
1799 default y if ARCH_EBSA110
1801 If you say Y here, one of the system LEDs (the green one on the
1802 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1803 will flash regularly to indicate that the system is still
1804 operational. This is mainly useful to kernel hackers who are
1805 debugging unstable kernels.
1807 The LART uses the same LED for both Timer LED and CPU usage LED
1808 functions. You may choose to use both, but the Timer LED function
1809 will overrule the CPU usage LED.
1812 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1814 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1815 || MACH_OMAP_PERSEUS2
1818 If you say Y here, the red LED will be used to give a good real
1819 time indication of CPU usage, by lighting whenever the idle task
1820 is not currently executing.
1822 The LART uses the same LED for both Timer LED and CPU usage LED
1823 functions. You may choose to use both, but the Timer LED function
1824 will overrule the CPU usage LED.
1826 config ALIGNMENT_TRAP
1828 depends on CPU_CP15_MMU
1829 default y if !ARCH_EBSA110
1830 select HAVE_PROC_CPU if PROC_FS
1832 ARM processors cannot fetch/store information which is not
1833 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1834 address divisible by 4. On 32-bit ARM processors, these non-aligned
1835 fetch/store instructions will be emulated in software if you say
1836 here, which has a severe performance impact. This is necessary for
1837 correct operation of some network protocols. With an IP-only
1838 configuration it is safe to say N, otherwise say Y.
1840 config UACCESS_WITH_MEMCPY
1841 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1842 depends on MMU && EXPERIMENTAL
1843 default y if CPU_FEROCEON
1845 Implement faster copy_to_user and clear_user methods for CPU
1846 cores where a 8-word STM instruction give significantly higher
1847 memory write throughput than a sequence of individual 32bit stores.
1849 A possible side effect is a slight increase in scheduling latency
1850 between threads sharing the same address space if they invoke
1851 such copy operations with large buffers.
1853 However, if the CPU data cache is using a write-allocate mode,
1854 this option is unlikely to provide any performance gain.
1858 prompt "Enable seccomp to safely compute untrusted bytecode"
1860 This kernel feature is useful for number crunching applications
1861 that may need to compute untrusted bytecode during their
1862 execution. By using pipes or other transports made available to
1863 the process as file descriptors supporting the read/write
1864 syscalls, it's possible to isolate those applications in
1865 their own address space using seccomp. Once seccomp is
1866 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1867 and the task is only allowed to execute a few safe syscalls
1868 defined by each seccomp mode.
1870 config CC_STACKPROTECTOR
1871 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1872 depends on EXPERIMENTAL
1874 This option turns on the -fstack-protector GCC feature. This
1875 feature puts, at the beginning of functions, a canary value on
1876 the stack just before the return address, and validates
1877 the value just before actually returning. Stack based buffer
1878 overflows (that need to overwrite this return address) now also
1879 overwrite the canary, which gets detected and the attack is then
1880 neutralized via a kernel panic.
1881 This feature requires gcc version 4.2 or above.
1883 config DEPRECATED_PARAM_STRUCT
1884 bool "Provide old way to pass kernel parameters"
1886 This was deprecated in 2001 and announced to live on for 5 years.
1887 Some old boot loaders still use this way.
1894 bool "Flattened Device Tree support"
1896 select OF_EARLY_FLATTREE
1899 Include support for flattened device tree machine descriptions.
1901 # Compressed boot loader in ROM. Yes, we really want to ask about
1902 # TEXT and BSS so we preserve their values in the config files.
1903 config ZBOOT_ROM_TEXT
1904 hex "Compressed ROM boot loader base address"
1907 The physical address at which the ROM-able zImage is to be
1908 placed in the target. Platforms which normally make use of
1909 ROM-able zImage formats normally set this to a suitable
1910 value in their defconfig file.
1912 If ZBOOT_ROM is not enabled, this has no effect.
1914 config ZBOOT_ROM_BSS
1915 hex "Compressed ROM boot loader BSS address"
1918 The base address of an area of read/write memory in the target
1919 for the ROM-able zImage which must be available while the
1920 decompressor is running. It must be large enough to hold the
1921 entire decompressed kernel plus an additional 128 KiB.
1922 Platforms which normally make use of ROM-able zImage formats
1923 normally set this to a suitable value in their defconfig file.
1925 If ZBOOT_ROM is not enabled, this has no effect.
1928 bool "Compressed boot loader in ROM/flash"
1929 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1931 Say Y here if you intend to execute your compressed kernel image
1932 (zImage) directly from ROM or flash. If unsure, say N.
1935 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1936 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1937 default ZBOOT_ROM_NONE
1939 Include experimental SD/MMC loading code in the ROM-able zImage.
1940 With this enabled it is possible to write the the ROM-able zImage
1941 kernel image to an MMC or SD card and boot the kernel straight
1942 from the reset vector. At reset the processor Mask ROM will load
1943 the first part of the the ROM-able zImage which in turn loads the
1944 rest the kernel image to RAM.
1946 config ZBOOT_ROM_NONE
1947 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1949 Do not load image from SD or MMC
1951 config ZBOOT_ROM_MMCIF
1952 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1954 Load image from MMCIF hardware block.
1956 config ZBOOT_ROM_SH_MOBILE_SDHI
1957 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1959 Load image from SDHI hardware block
1963 config ARM_APPENDED_DTB
1964 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1965 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1967 With this option, the boot code will look for a device tree binary
1968 (DTB) appended to zImage
1969 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1971 This is meant as a backward compatibility convenience for those
1972 systems with a bootloader that can't be upgraded to accommodate
1973 the documented boot protocol using a device tree.
1975 Beware that there is very little in terms of protection against
1976 this option being confused by leftover garbage in memory that might
1977 look like a DTB header after a reboot if no actual DTB is appended
1978 to zImage. Do not leave this option active in a production kernel
1979 if you don't intend to always append a DTB. Proper passing of the
1980 location into r2 of a bootloader provided DTB is always preferable
1983 config ARM_ATAG_DTB_COMPAT
1984 bool "Supplement the appended DTB with traditional ATAG information"
1985 depends on ARM_APPENDED_DTB
1987 Some old bootloaders can't be updated to a DTB capable one, yet
1988 they provide ATAGs with memory configuration, the ramdisk address,
1989 the kernel cmdline string, etc. Such information is dynamically
1990 provided by the bootloader and can't always be stored in a static
1991 DTB. To allow a device tree enabled kernel to be used with such
1992 bootloaders, this option allows zImage to extract the information
1993 from the ATAG list and store it at run time into the appended DTB.
1996 string "Default kernel command string"
1999 On some architectures (EBSA110 and CATS), there is currently no way
2000 for the boot loader to pass arguments to the kernel. For these
2001 architectures, you should supply some command-line options at build
2002 time by entering them here. As a minimum, you should specify the
2003 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2006 prompt "Kernel command line type" if CMDLINE != ""
2007 default CMDLINE_FROM_BOOTLOADER
2009 config CMDLINE_FROM_BOOTLOADER
2010 bool "Use bootloader kernel arguments if available"
2012 Uses the command-line options passed by the boot loader. If
2013 the boot loader doesn't provide any, the default kernel command
2014 string provided in CMDLINE will be used.
2016 config CMDLINE_EXTEND
2017 bool "Extend bootloader kernel arguments"
2019 The command-line arguments provided by the boot loader will be
2020 appended to the default kernel command string.
2022 config CMDLINE_FORCE
2023 bool "Always use the default kernel command string"
2025 Always use the default kernel command string, even if the boot
2026 loader passes other arguments to the kernel.
2027 This is useful if you cannot or don't want to change the
2028 command-line options your boot loader passes to the kernel.
2032 bool "Kernel Execute-In-Place from ROM"
2033 depends on !ZBOOT_ROM && !ARM_LPAE
2035 Execute-In-Place allows the kernel to run from non-volatile storage
2036 directly addressable by the CPU, such as NOR flash. This saves RAM
2037 space since the text section of the kernel is not loaded from flash
2038 to RAM. Read-write sections, such as the data section and stack,
2039 are still copied to RAM. The XIP kernel is not compressed since
2040 it has to run directly from flash, so it will take more space to
2041 store it. The flash address used to link the kernel object files,
2042 and for storing it, is configuration dependent. Therefore, if you
2043 say Y here, you must know the proper physical address where to
2044 store the kernel image depending on your own flash memory usage.
2046 Also note that the make target becomes "make xipImage" rather than
2047 "make zImage" or "make Image". The final kernel binary to put in
2048 ROM memory will be arch/arm/boot/xipImage.
2052 config XIP_PHYS_ADDR
2053 hex "XIP Kernel Physical Location"
2054 depends on XIP_KERNEL
2055 default "0x00080000"
2057 This is the physical address in your flash memory the kernel will
2058 be linked for and stored to. This address is dependent on your
2062 bool "Kexec system call (EXPERIMENTAL)"
2063 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2065 kexec is a system call that implements the ability to shutdown your
2066 current kernel, and to start another kernel. It is like a reboot
2067 but it is independent of the system firmware. And like a reboot
2068 you can start any kernel with it, not just Linux.
2070 It is an ongoing process to be certain the hardware in a machine
2071 is properly shutdown, so do not be surprised if this code does not
2072 initially work for you. It may help to enable device hotplugging
2076 bool "Export atags in procfs"
2080 Should the atags used to boot the kernel be exported in an "atags"
2081 file in procfs. Useful with kexec.
2084 bool "Build kdump crash kernel (EXPERIMENTAL)"
2085 depends on EXPERIMENTAL
2087 Generate crash dump after being started by kexec. This should
2088 be normally only set in special crash dump kernels which are
2089 loaded in the main kernel with kexec-tools into a specially
2090 reserved region and then later executed after a crash by
2091 kdump/kexec. The crash dump kernel must be compiled to a
2092 memory address not used by the main kernel
2094 For more details see Documentation/kdump/kdump.txt
2096 config AUTO_ZRELADDR
2097 bool "Auto calculation of the decompressed kernel image address"
2098 depends on !ZBOOT_ROM && !ARCH_U300
2100 ZRELADDR is the physical address where the decompressed kernel
2101 image will be placed. If AUTO_ZRELADDR is selected, the address
2102 will be determined at run-time by masking the current IP with
2103 0xf8000000. This assumes the zImage being placed in the first 128MB
2104 from start of memory.
2108 menu "CPU Power Management"
2112 source "drivers/cpufreq/Kconfig"
2115 tristate "CPUfreq driver for i.MX CPUs"
2116 depends on ARCH_MXC && CPU_FREQ
2118 This enables the CPUfreq driver for i.MX CPUs.
2120 config CPU_FREQ_SA1100
2123 config CPU_FREQ_SA1110
2126 config CPU_FREQ_INTEGRATOR
2127 tristate "CPUfreq driver for ARM Integrator CPUs"
2128 depends on ARCH_INTEGRATOR && CPU_FREQ
2131 This enables the CPUfreq driver for ARM Integrator CPUs.
2133 For details, take a look at <file:Documentation/cpu-freq>.
2139 depends on CPU_FREQ && ARCH_PXA && PXA25x
2141 select CPU_FREQ_TABLE
2142 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2147 Internal configuration node for common cpufreq on Samsung SoC
2149 config CPU_FREQ_S3C24XX
2150 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2151 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2154 This enables the CPUfreq driver for the Samsung S3C24XX family
2157 For details, take a look at <file:Documentation/cpu-freq>.
2161 config CPU_FREQ_S3C24XX_PLL
2162 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2163 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2165 Compile in support for changing the PLL frequency from the
2166 S3C24XX series CPUfreq driver. The PLL takes time to settle
2167 after a frequency change, so by default it is not enabled.
2169 This also means that the PLL tables for the selected CPU(s) will
2170 be built which may increase the size of the kernel image.
2172 config CPU_FREQ_S3C24XX_DEBUG
2173 bool "Debug CPUfreq Samsung driver core"
2174 depends on CPU_FREQ_S3C24XX
2176 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2178 config CPU_FREQ_S3C24XX_IODEBUG
2179 bool "Debug CPUfreq Samsung driver IO timing"
2180 depends on CPU_FREQ_S3C24XX
2182 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2184 config CPU_FREQ_S3C24XX_DEBUGFS
2185 bool "Export debugfs for CPUFreq"
2186 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2188 Export status information via debugfs.
2192 source "drivers/cpuidle/Kconfig"
2196 menu "Floating point emulation"
2198 comment "At least one emulation must be selected"
2201 bool "NWFPE math emulation"
2202 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2204 Say Y to include the NWFPE floating point emulator in the kernel.
2205 This is necessary to run most binaries. Linux does not currently
2206 support floating point hardware so you need to say Y here even if
2207 your machine has an FPA or floating point co-processor podule.
2209 You may say N here if you are going to load the Acorn FPEmulator
2210 early in the bootup.
2213 bool "Support extended precision"
2214 depends on FPE_NWFPE
2216 Say Y to include 80-bit support in the kernel floating-point
2217 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2218 Note that gcc does not generate 80-bit operations by default,
2219 so in most cases this option only enlarges the size of the
2220 floating point emulator without any good reason.
2222 You almost surely want to say N here.
2225 bool "FastFPE math emulation (EXPERIMENTAL)"
2226 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2228 Say Y here to include the FAST floating point emulator in the kernel.
2229 This is an experimental much faster emulator which now also has full
2230 precision for the mantissa. It does not support any exceptions.
2231 It is very simple, and approximately 3-6 times faster than NWFPE.
2233 It should be sufficient for most programs. It may be not suitable
2234 for scientific calculations, but you have to check this for yourself.
2235 If you do not feel you need a faster FP emulation you should better
2239 bool "VFP-format floating point maths"
2240 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2242 Say Y to include VFP support code in the kernel. This is needed
2243 if your hardware includes a VFP unit.
2245 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2246 release notes and additional status information.
2248 Say N if your target does not have VFP hardware.
2256 bool "Advanced SIMD (NEON) Extension support"
2257 depends on VFPv3 && CPU_V7
2259 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2264 menu "Userspace binary formats"
2266 source "fs/Kconfig.binfmt"
2269 tristate "RISC OS personality"
2272 Say Y here to include the kernel code necessary if you want to run
2273 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2274 experimental; if this sounds frightening, say N and sleep in peace.
2275 You can also say M here to compile this support as a module (which
2276 will be called arthur).
2280 menu "Power management options"
2282 source "kernel/power/Kconfig"
2284 config ARCH_SUSPEND_POSSIBLE
2285 depends on !ARCH_S5PC100
2286 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2287 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2290 config ARM_CPU_SUSPEND
2295 source "net/Kconfig"
2297 source "drivers/Kconfig"
2301 source "arch/arm/Kconfig.debug"
2303 source "security/Kconfig"
2305 source "crypto/Kconfig"
2307 source "lib/Kconfig"