5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
12 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
14 select HAVE_KPROBES if !XIP_KERNEL
15 select HAVE_KRETPROBES if (HAVE_KPROBES)
16 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
17 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
18 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
19 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
20 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
21 select HAVE_GENERIC_DMA_COHERENT
22 select HAVE_KERNEL_GZIP
23 select HAVE_KERNEL_LZO
24 select HAVE_KERNEL_LZMA
27 select HAVE_PERF_EVENTS
28 select PERF_USE_VMALLOC
29 select HAVE_REGS_AND_STACK_ACCESS_API
30 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
31 select HAVE_C_RECORDMCOUNT
32 select HAVE_GENERIC_HARDIRQS
33 select GENERIC_IRQ_SHOW
34 select CPU_PM if (SUSPEND || CPU_IDLE)
35 select GENERIC_PCI_IOMAP
36 select HAVE_BPF_JIT if NET
38 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
40 The ARM series is a line of low-power-consumption RISC chip designs
41 licensed by ARM Ltd and targeted at embedded applications and
42 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
43 manufactured, but legacy ARM-based PC hardware remains popular in
44 Europe. There is an ARM Linux project with a web page at
45 <http://www.arm.linux.org.uk/>.
47 config ARM_HAS_SG_CHAIN
56 config SYS_SUPPORTS_APM_EMULATION
64 select GENERIC_ALLOCATOR
75 The Extended Industry Standard Architecture (EISA) bus was
76 developed as an open alternative to the IBM MicroChannel bus.
78 The EISA bus provided some of the features of the IBM MicroChannel
79 bus while maintaining backward compatibility with cards made for
80 the older ISA bus. The EISA bus saw limited use between 1988 and
81 1995 when it was made obsolete by the PCI bus.
83 Say Y here if you are building a kernel for an EISA-based machine.
93 MicroChannel Architecture is found in some IBM PS/2 machines and
94 laptops. It is a bus system similar to PCI or ISA. See
95 <file:Documentation/mca.txt> (and especially the web page given
96 there) before attempting to build an MCA bus kernel.
98 config STACKTRACE_SUPPORT
102 config HAVE_LATENCYTOP_SUPPORT
107 config LOCKDEP_SUPPORT
111 config TRACE_IRQFLAGS_SUPPORT
115 config HARDIRQS_SW_RESEND
119 config GENERIC_IRQ_PROBE
123 config GENERIC_LOCKBREAK
126 depends on SMP && PREEMPT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config ARCH_HAS_CPU_IDLE_WAIT
151 config GENERIC_HWEIGHT
155 config GENERIC_CALIBRATE_DELAY
159 config ARCH_MAY_HAVE_PC_FDC
165 config NEED_DMA_MAP_STATE
168 config ARCH_HAS_DMA_SET_COHERENT_MASK
171 config GENERIC_ISA_DMA
177 config NEED_RET_TO_USER
185 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
186 default DRAM_BASE if REMAP_VECTORS_TO_RAM
189 The base address of exception vectors.
191 config ARM_PATCH_PHYS_VIRT
192 bool "Patch physical to virtual translations at runtime" if EMBEDDED
194 depends on !XIP_KERNEL && MMU
195 depends on !ARCH_REALVIEW || !SPARSEMEM
197 Patch phys-to-virt and virt-to-phys translation functions at
198 boot and module load time according to the position of the
199 kernel in system memory.
201 This can only be used with non-XIP MMU kernels where the base
202 of physical memory is at a 16MB boundary.
204 Only disable this option if you know that you do not require
205 this feature (eg, building a kernel for a single machine) and
206 you need to shrink the kernel to the minimal size.
208 config NEED_MACH_IO_H
211 Select this when mach/io.h is required to provide special
212 definitions for this platform. The need for mach/io.h should
213 be avoided when possible.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory" if MMU
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 default DRAM_BASE if !MMU
227 Please provide the physical address corresponding to the
228 location of main memory in your system.
234 source "init/Kconfig"
236 source "kernel/Kconfig.freezer"
241 bool "MMU-based Paged Memory Management Support"
244 Select if you want MMU-based virtualised addressing space
245 support by paged memory management. If unsure, say 'Y'.
248 # The "ARM system type" choice list is ordered alphabetically by option
249 # text. Please add new entries in the option alphabetic order.
252 prompt "ARM system type"
253 default ARCH_VERSATILE
255 config ARCH_INTEGRATOR
256 bool "ARM Ltd. Integrator family"
258 select ARCH_HAS_CPUFREQ
260 select HAVE_MACH_CLKDEV
263 select GENERIC_CLOCKEVENTS
264 select PLAT_VERSATILE
265 select PLAT_VERSATILE_FPGA_IRQ
266 select NEED_MACH_IO_H
267 select NEED_MACH_MEMORY_H
270 Support for ARM's Integrator platform.
273 bool "ARM Ltd. RealView family"
276 select HAVE_MACH_CLKDEV
278 select GENERIC_CLOCKEVENTS
279 select ARCH_WANT_OPTIONAL_GPIOLIB
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_CLCD
282 select ARM_TIMER_SP804
283 select GPIO_PL061 if GPIOLIB
284 select NEED_MACH_MEMORY_H
286 This enables support for ARM Ltd RealView boards.
288 config ARCH_VERSATILE
289 bool "ARM Ltd. Versatile family"
293 select HAVE_MACH_CLKDEV
295 select GENERIC_CLOCKEVENTS
296 select ARCH_WANT_OPTIONAL_GPIOLIB
297 select PLAT_VERSATILE
298 select PLAT_VERSATILE_CLCD
299 select PLAT_VERSATILE_FPGA_IRQ
300 select ARM_TIMER_SP804
302 This enables support for ARM Ltd Versatile board.
305 bool "ARM Ltd. Versatile Express family"
306 select ARCH_WANT_OPTIONAL_GPIOLIB
308 select ARM_TIMER_SP804
310 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
313 select HAVE_PATA_PLATFORM
316 select PLAT_VERSATILE
317 select PLAT_VERSATILE_CLCD
319 This enables support for the ARM Ltd Versatile Express boards.
323 select ARCH_REQUIRE_GPIOLIB
327 select NEED_MACH_IO_H if PCCARD
329 This enables support for systems based on the Atmel AT91RM9200,
333 bool "Broadcom BCMRING"
337 select ARM_TIMER_SP804
339 select GENERIC_CLOCKEVENTS
340 select ARCH_WANT_OPTIONAL_GPIOLIB
342 Support for Broadcom's BCMRing platform.
345 bool "Calxeda Highbank-based"
346 select ARCH_WANT_OPTIONAL_GPIOLIB
349 select ARM_TIMER_SP804
353 select GENERIC_CLOCKEVENTS
359 Support for the Calxeda Highbank SoC based boards.
362 bool "Cirrus Logic CLPS711x/EP721x-based"
364 select ARCH_USES_GETTIMEOFFSET
365 select NEED_MACH_MEMORY_H
367 Support for Cirrus Logic 711x/721x based boards.
370 bool "Cavium Networks CNS3XXX family"
372 select GENERIC_CLOCKEVENTS
374 select MIGHT_HAVE_CACHE_L2X0
375 select MIGHT_HAVE_PCI
376 select PCI_DOMAINS if PCI
378 Support for Cavium Networks CNS3XXX platform.
381 bool "Cortina Systems Gemini"
383 select ARCH_REQUIRE_GPIOLIB
384 select ARCH_USES_GETTIMEOFFSET
386 Support for the Cortina Systems Gemini family SoCs
389 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
392 select GENERIC_CLOCKEVENTS
394 select GENERIC_IRQ_CHIP
395 select MIGHT_HAVE_CACHE_L2X0
399 Support for CSR SiRFSoC ARM Cortex A9 Platform
406 select ARCH_USES_GETTIMEOFFSET
407 select NEED_MACH_IO_H
408 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
421 select ARCH_REQUIRE_GPIOLIB
422 select ARCH_HAS_HOLES_MEMORYMODEL
423 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_IO_H
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Freescale MXC/iMX-based"
442 select GENERIC_CLOCKEVENTS
443 select ARCH_REQUIRE_GPIOLIB
446 select GENERIC_IRQ_CHIP
447 select MULTI_IRQ_HANDLER
449 Support for Freescale MXC/iMX-based family of processors
452 bool "Freescale MXS-based"
453 select GENERIC_CLOCKEVENTS
454 select ARCH_REQUIRE_GPIOLIB
457 select HAVE_CLK_PREPARE
459 Support for Freescale MXS-based family of processors
462 bool "Hilscher NetX based"
466 select GENERIC_CLOCKEVENTS
468 This enables support for systems based on the Hilscher NetX Soc
471 bool "Hynix HMS720x-based"
474 select ARCH_USES_GETTIMEOFFSET
476 This enables support for systems based on the Hynix HMS720x
484 select ARCH_SUPPORTS_MSI
486 select NEED_MACH_IO_H
487 select NEED_MACH_MEMORY_H
488 select NEED_RET_TO_USER
490 Support for Intel's IOP13XX (XScale) family of processors.
496 select NEED_MACH_IO_H
497 select NEED_RET_TO_USER
500 select ARCH_REQUIRE_GPIOLIB
502 Support for Intel's 80219 and IOP32X (XScale) family of
509 select NEED_MACH_IO_H
510 select NEED_RET_TO_USER
513 select ARCH_REQUIRE_GPIOLIB
515 Support for Intel's IOP33X (XScale) family of processors.
522 select ARCH_USES_GETTIMEOFFSET
523 select NEED_MACH_IO_H
524 select NEED_MACH_MEMORY_H
526 Support for Intel's IXP23xx (XScale) family of processors.
529 bool "IXP2400/2800-based"
533 select ARCH_USES_GETTIMEOFFSET
534 select NEED_MACH_IO_H
535 select NEED_MACH_MEMORY_H
537 Support for Intel's IXP2400/2800 (XScale) family of processors.
542 select ARCH_HAS_DMA_SET_COHERENT_MASK
546 select GENERIC_CLOCKEVENTS
547 select MIGHT_HAVE_PCI
548 select NEED_MACH_IO_H
549 select DMABOUNCE if PCI
551 Support for Intel's IXP4XX (XScale) family of processors.
557 select ARCH_REQUIRE_GPIOLIB
558 select GENERIC_CLOCKEVENTS
559 select NEED_MACH_IO_H
562 Support for the Marvell Dove SoC 88AP510
565 bool "Marvell Kirkwood"
568 select ARCH_REQUIRE_GPIOLIB
569 select GENERIC_CLOCKEVENTS
570 select NEED_MACH_IO_H
573 Support for the following Marvell Kirkwood series SoCs:
574 88F6180, 88F6192 and 88F6281.
580 select ARCH_REQUIRE_GPIOLIB
583 select USB_ARCH_HAS_OHCI
585 select GENERIC_CLOCKEVENTS
587 Support for the NXP LPC32XX family of processors
590 bool "Marvell MV78xx0"
593 select ARCH_REQUIRE_GPIOLIB
594 select GENERIC_CLOCKEVENTS
595 select NEED_MACH_IO_H
598 Support for the following Marvell MV78xx0 series SoCs:
606 select ARCH_REQUIRE_GPIOLIB
607 select GENERIC_CLOCKEVENTS
610 Support for the following Marvell Orion 5x series SoCs:
611 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
612 Orion-2 (5281), Orion-1-90 (6183).
615 bool "Marvell PXA168/910/MMP2"
617 select ARCH_REQUIRE_GPIOLIB
619 select GENERIC_CLOCKEVENTS
624 select GENERIC_ALLOCATOR
626 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
629 bool "Micrel/Kendin KS8695"
631 select ARCH_REQUIRE_GPIOLIB
632 select ARCH_USES_GETTIMEOFFSET
633 select NEED_MACH_MEMORY_H
635 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
636 System-on-Chip devices.
639 bool "Nuvoton W90X900 CPU"
641 select ARCH_REQUIRE_GPIOLIB
644 select GENERIC_CLOCKEVENTS
646 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
647 At present, the w90x900 has been renamed nuc900, regarding
648 the ARM series product line, you can login the following
649 link address to know more.
651 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
652 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
658 select GENERIC_CLOCKEVENTS
662 select MIGHT_HAVE_CACHE_L2X0
663 select NEED_MACH_IO_H if PCI
664 select ARCH_HAS_CPUFREQ
666 This enables support for NVIDIA Tegra based systems (Tegra APX,
667 Tegra 6xx and Tegra 2 series).
669 config ARCH_PICOXCELL
670 bool "Picochip picoXcell"
671 select ARCH_REQUIRE_GPIOLIB
672 select ARM_PATCH_PHYS_VIRT
676 select GENERIC_CLOCKEVENTS
683 This enables support for systems based on the Picochip picoXcell
684 family of Femtocell devices. The picoxcell support requires device tree
688 bool "Philips Nexperia PNX4008 Mobile"
691 select ARCH_USES_GETTIMEOFFSET
693 This enables support for Philips PNX4008 mobile platform.
696 bool "PXA2xx/PXA3xx-based"
699 select ARCH_HAS_CPUFREQ
702 select ARCH_REQUIRE_GPIOLIB
703 select GENERIC_CLOCKEVENTS
709 select MULTI_IRQ_HANDLER
710 select ARM_CPU_SUSPEND if PM
713 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
718 select GENERIC_CLOCKEVENTS
719 select ARCH_REQUIRE_GPIOLIB
722 Support for Qualcomm MSM/QSD based systems. This runs on the
723 apps processor of the MSM/QSD and depends on a shared memory
724 interface to the modem processor which runs the baseband
725 stack and controls some vital subsystems
726 (clock and power control, etc).
729 bool "Renesas SH-Mobile / R-Mobile"
732 select HAVE_MACH_CLKDEV
734 select GENERIC_CLOCKEVENTS
735 select MIGHT_HAVE_CACHE_L2X0
738 select MULTI_IRQ_HANDLER
739 select PM_GENERIC_DOMAINS if PM
740 select NEED_MACH_MEMORY_H
742 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
748 select ARCH_MAY_HAVE_PC_FDC
749 select HAVE_PATA_PLATFORM
752 select ARCH_SPARSEMEM_ENABLE
753 select ARCH_USES_GETTIMEOFFSET
755 select NEED_MACH_IO_H
756 select NEED_MACH_MEMORY_H
758 On the Acorn Risc-PC, Linux can support the internal IDE disk and
759 CD-ROM interface, serial and parallel port, and the floppy drive.
766 select ARCH_SPARSEMEM_ENABLE
768 select ARCH_HAS_CPUFREQ
770 select GENERIC_CLOCKEVENTS
773 select ARCH_REQUIRE_GPIOLIB
775 select NEED_MACH_MEMORY_H
778 Support for StrongARM 11x0 based boards.
781 bool "Samsung S3C24XX SoCs"
783 select ARCH_HAS_CPUFREQ
786 select ARCH_USES_GETTIMEOFFSET
787 select HAVE_S3C2410_I2C if I2C
788 select HAVE_S3C_RTC if RTC_CLASS
789 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 select NEED_MACH_IO_H
792 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
793 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
794 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
795 Samsung SMDK2410 development board (and derivatives).
798 bool "Samsung S3C64XX"
806 select ARCH_USES_GETTIMEOFFSET
807 select ARCH_HAS_CPUFREQ
808 select ARCH_REQUIRE_GPIOLIB
809 select SAMSUNG_CLKSRC
810 select SAMSUNG_IRQ_VIC_TIMER
811 select S3C_GPIO_TRACK
813 select USB_ARCH_HAS_OHCI
814 select SAMSUNG_GPIOLIB_4BIT
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C2410_WATCHDOG if WATCHDOG
818 Samsung S3C64XX series based systems
821 bool "Samsung S5P6440 S5P6450"
827 select HAVE_S3C2410_WATCHDOG if WATCHDOG
828 select GENERIC_CLOCKEVENTS
829 select HAVE_S3C2410_I2C if I2C
830 select HAVE_S3C_RTC if RTC_CLASS
832 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
836 bool "Samsung S5PC100"
841 select ARCH_USES_GETTIMEOFFSET
842 select HAVE_S3C2410_I2C if I2C
843 select HAVE_S3C_RTC if RTC_CLASS
844 select HAVE_S3C2410_WATCHDOG if WATCHDOG
846 Samsung S5PC100 series based systems
849 bool "Samsung S5PV210/S5PC110"
851 select ARCH_SPARSEMEM_ENABLE
852 select ARCH_HAS_HOLES_MEMORYMODEL
857 select ARCH_HAS_CPUFREQ
858 select GENERIC_CLOCKEVENTS
859 select HAVE_S3C2410_I2C if I2C
860 select HAVE_S3C_RTC if RTC_CLASS
861 select HAVE_S3C2410_WATCHDOG if WATCHDOG
862 select NEED_MACH_MEMORY_H
864 Samsung S5PV210/S5PC110 series based systems
867 bool "SAMSUNG EXYNOS"
869 select ARCH_SPARSEMEM_ENABLE
870 select ARCH_HAS_HOLES_MEMORYMODEL
874 select ARCH_HAS_CPUFREQ
875 select GENERIC_CLOCKEVENTS
876 select HAVE_S3C_RTC if RTC_CLASS
877 select HAVE_S3C2410_I2C if I2C
878 select HAVE_S3C2410_WATCHDOG if WATCHDOG
879 select NEED_MACH_MEMORY_H
881 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
890 select ARCH_USES_GETTIMEOFFSET
891 select NEED_MACH_MEMORY_H
892 select NEED_MACH_IO_H
894 Support for the StrongARM based Digital DNARD machine, also known
895 as "Shark" (<http://www.shark-linux.de/shark.html>).
898 bool "ST-Ericsson U300 Series"
904 select ARM_PATCH_PHYS_VIRT
906 select GENERIC_CLOCKEVENTS
908 select HAVE_MACH_CLKDEV
910 select ARCH_REQUIRE_GPIOLIB
912 Support for ST-Ericsson U300 series mobile platforms.
915 bool "ST-Ericsson U8500 Series"
919 select GENERIC_CLOCKEVENTS
921 select ARCH_REQUIRE_GPIOLIB
922 select ARCH_HAS_CPUFREQ
924 select MIGHT_HAVE_CACHE_L2X0
926 Support for ST-Ericsson's Ux500 architecture
929 bool "STMicroelectronics Nomadik"
934 select GENERIC_CLOCKEVENTS
935 select MIGHT_HAVE_CACHE_L2X0
936 select ARCH_REQUIRE_GPIOLIB
938 Support for the Nomadik platform by ST-Ericsson
942 select GENERIC_CLOCKEVENTS
943 select ARCH_REQUIRE_GPIOLIB
947 select GENERIC_ALLOCATOR
948 select GENERIC_IRQ_CHIP
949 select ARCH_HAS_HOLES_MEMORYMODEL
951 Support for TI's DaVinci platform.
956 select ARCH_REQUIRE_GPIOLIB
957 select ARCH_HAS_CPUFREQ
959 select GENERIC_CLOCKEVENTS
960 select ARCH_HAS_HOLES_MEMORYMODEL
962 Support for TI's OMAP platform (OMAP1/2/3/4).
967 select ARCH_REQUIRE_GPIOLIB
970 select GENERIC_CLOCKEVENTS
973 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
976 bool "VIA/WonderMedia 85xx"
979 select ARCH_HAS_CPUFREQ
980 select GENERIC_CLOCKEVENTS
981 select ARCH_REQUIRE_GPIOLIB
984 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
987 bool "Xilinx Zynq ARM Cortex A9 Platform"
989 select GENERIC_CLOCKEVENTS
994 select MIGHT_HAVE_CACHE_L2X0
997 Support for Xilinx Zynq ARM Cortex A9 Platform
1001 # This is sorted alphabetically by mach-* pathname. However, plat-*
1002 # Kconfigs may be included either alphabetically (according to the
1003 # plat- suffix) or along side the corresponding mach-* source.
1005 source "arch/arm/mach-at91/Kconfig"
1007 source "arch/arm/mach-bcmring/Kconfig"
1009 source "arch/arm/mach-clps711x/Kconfig"
1011 source "arch/arm/mach-cns3xxx/Kconfig"
1013 source "arch/arm/mach-davinci/Kconfig"
1015 source "arch/arm/mach-dove/Kconfig"
1017 source "arch/arm/mach-ep93xx/Kconfig"
1019 source "arch/arm/mach-footbridge/Kconfig"
1021 source "arch/arm/mach-gemini/Kconfig"
1023 source "arch/arm/mach-h720x/Kconfig"
1025 source "arch/arm/mach-integrator/Kconfig"
1027 source "arch/arm/mach-iop32x/Kconfig"
1029 source "arch/arm/mach-iop33x/Kconfig"
1031 source "arch/arm/mach-iop13xx/Kconfig"
1033 source "arch/arm/mach-ixp4xx/Kconfig"
1035 source "arch/arm/mach-ixp2000/Kconfig"
1037 source "arch/arm/mach-ixp23xx/Kconfig"
1039 source "arch/arm/mach-kirkwood/Kconfig"
1041 source "arch/arm/mach-ks8695/Kconfig"
1043 source "arch/arm/mach-lpc32xx/Kconfig"
1045 source "arch/arm/mach-msm/Kconfig"
1047 source "arch/arm/mach-mv78xx0/Kconfig"
1049 source "arch/arm/plat-mxc/Kconfig"
1051 source "arch/arm/mach-mxs/Kconfig"
1053 source "arch/arm/mach-netx/Kconfig"
1055 source "arch/arm/mach-nomadik/Kconfig"
1056 source "arch/arm/plat-nomadik/Kconfig"
1058 source "arch/arm/plat-omap/Kconfig"
1060 source "arch/arm/mach-omap1/Kconfig"
1062 source "arch/arm/mach-omap2/Kconfig"
1064 source "arch/arm/mach-orion5x/Kconfig"
1066 source "arch/arm/mach-pxa/Kconfig"
1067 source "arch/arm/plat-pxa/Kconfig"
1069 source "arch/arm/mach-mmp/Kconfig"
1071 source "arch/arm/mach-realview/Kconfig"
1073 source "arch/arm/mach-sa1100/Kconfig"
1075 source "arch/arm/plat-samsung/Kconfig"
1076 source "arch/arm/plat-s3c24xx/Kconfig"
1077 source "arch/arm/plat-s5p/Kconfig"
1079 source "arch/arm/plat-spear/Kconfig"
1081 source "arch/arm/mach-s3c24xx/Kconfig"
1083 source "arch/arm/mach-s3c2412/Kconfig"
1084 source "arch/arm/mach-s3c2440/Kconfig"
1088 source "arch/arm/mach-s3c64xx/Kconfig"
1091 source "arch/arm/mach-s5p64x0/Kconfig"
1093 source "arch/arm/mach-s5pc100/Kconfig"
1095 source "arch/arm/mach-s5pv210/Kconfig"
1097 source "arch/arm/mach-exynos/Kconfig"
1099 source "arch/arm/mach-shmobile/Kconfig"
1101 source "arch/arm/mach-tegra/Kconfig"
1103 source "arch/arm/mach-u300/Kconfig"
1105 source "arch/arm/mach-ux500/Kconfig"
1107 source "arch/arm/mach-versatile/Kconfig"
1109 source "arch/arm/mach-vexpress/Kconfig"
1110 source "arch/arm/plat-versatile/Kconfig"
1112 source "arch/arm/mach-vt8500/Kconfig"
1114 source "arch/arm/mach-w90x900/Kconfig"
1116 # Definitions to make life easier
1122 select GENERIC_CLOCKEVENTS
1127 select GENERIC_IRQ_CHIP
1132 config PLAT_VERSATILE
1135 config ARM_TIMER_SP804
1138 select HAVE_SCHED_CLOCK
1140 source arch/arm/mm/Kconfig
1144 default 16 if ARCH_EP93XX
1148 bool "Enable iWMMXt support"
1149 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1150 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1152 Enable support for iWMMXt context switching at run time if
1153 running on a CPU that supports it.
1157 depends on CPU_XSCALE
1161 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1162 (!ARCH_OMAP3 || OMAP3_EMU)
1166 config MULTI_IRQ_HANDLER
1169 Allow each machine to specify it's own IRQ handler at run time.
1172 source "arch/arm/Kconfig-nommu"
1175 config ARM_ERRATA_326103
1176 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1179 Executing a SWP instruction to read-only memory does not set bit 11
1180 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1181 treat the access as a read, preventing a COW from occurring and
1182 causing the faulting task to livelock.
1184 config ARM_ERRATA_411920
1185 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1186 depends on CPU_V6 || CPU_V6K
1188 Invalidation of the Instruction Cache operation can
1189 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1190 It does not affect the MPCore. This option enables the ARM Ltd.
1191 recommended workaround.
1193 config ARM_ERRATA_430973
1194 bool "ARM errata: Stale prediction on replaced interworking branch"
1197 This option enables the workaround for the 430973 Cortex-A8
1198 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1199 interworking branch is replaced with another code sequence at the
1200 same virtual address, whether due to self-modifying code or virtual
1201 to physical address re-mapping, Cortex-A8 does not recover from the
1202 stale interworking branch prediction. This results in Cortex-A8
1203 executing the new code sequence in the incorrect ARM or Thumb state.
1204 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1205 and also flushes the branch target cache at every context switch.
1206 Note that setting specific bits in the ACTLR register may not be
1207 available in non-secure mode.
1209 config ARM_ERRATA_458693
1210 bool "ARM errata: Processor deadlock when a false hazard is created"
1213 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1214 erratum. For very specific sequences of memory operations, it is
1215 possible for a hazard condition intended for a cache line to instead
1216 be incorrectly associated with a different cache line. This false
1217 hazard might then cause a processor deadlock. The workaround enables
1218 the L1 caching of the NEON accesses and disables the PLD instruction
1219 in the ACTLR register. Note that setting specific bits in the ACTLR
1220 register may not be available in non-secure mode.
1222 config ARM_ERRATA_460075
1223 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1226 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1227 erratum. Any asynchronous access to the L2 cache may encounter a
1228 situation in which recent store transactions to the L2 cache are lost
1229 and overwritten with stale memory contents from external memory. The
1230 workaround disables the write-allocate mode for the L2 cache via the
1231 ACTLR register. Note that setting specific bits in the ACTLR register
1232 may not be available in non-secure mode.
1234 config ARM_ERRATA_742230
1235 bool "ARM errata: DMB operation may be faulty"
1236 depends on CPU_V7 && SMP
1238 This option enables the workaround for the 742230 Cortex-A9
1239 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1240 between two write operations may not ensure the correct visibility
1241 ordering of the two writes. This workaround sets a specific bit in
1242 the diagnostic register of the Cortex-A9 which causes the DMB
1243 instruction to behave as a DSB, ensuring the correct behaviour of
1246 config ARM_ERRATA_742231
1247 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1248 depends on CPU_V7 && SMP
1250 This option enables the workaround for the 742231 Cortex-A9
1251 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1252 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1253 accessing some data located in the same cache line, may get corrupted
1254 data due to bad handling of the address hazard when the line gets
1255 replaced from one of the CPUs at the same time as another CPU is
1256 accessing it. This workaround sets specific bits in the diagnostic
1257 register of the Cortex-A9 which reduces the linefill issuing
1258 capabilities of the processor.
1260 config PL310_ERRATA_588369
1261 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1262 depends on CACHE_L2X0
1264 The PL310 L2 cache controller implements three types of Clean &
1265 Invalidate maintenance operations: by Physical Address
1266 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1267 They are architecturally defined to behave as the execution of a
1268 clean operation followed immediately by an invalidate operation,
1269 both performing to the same memory location. This functionality
1270 is not correctly implemented in PL310 as clean lines are not
1271 invalidated as a result of these operations.
1273 config ARM_ERRATA_720789
1274 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1277 This option enables the workaround for the 720789 Cortex-A9 (prior to
1278 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1279 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1280 As a consequence of this erratum, some TLB entries which should be
1281 invalidated are not, resulting in an incoherency in the system page
1282 tables. The workaround changes the TLB flushing routines to invalidate
1283 entries regardless of the ASID.
1285 config PL310_ERRATA_727915
1286 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1287 depends on CACHE_L2X0
1289 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1290 operation (offset 0x7FC). This operation runs in background so that
1291 PL310 can handle normal accesses while it is in progress. Under very
1292 rare circumstances, due to this erratum, write data can be lost when
1293 PL310 treats a cacheable write transaction during a Clean &
1294 Invalidate by Way operation.
1296 config ARM_ERRATA_743622
1297 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1300 This option enables the workaround for the 743622 Cortex-A9
1301 (r2p*) erratum. Under very rare conditions, a faulty
1302 optimisation in the Cortex-A9 Store Buffer may lead to data
1303 corruption. This workaround sets a specific bit in the diagnostic
1304 register of the Cortex-A9 which disables the Store Buffer
1305 optimisation, preventing the defect from occurring. This has no
1306 visible impact on the overall performance or power consumption of the
1309 config ARM_ERRATA_751472
1310 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1313 This option enables the workaround for the 751472 Cortex-A9 (prior
1314 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1315 completion of a following broadcasted operation if the second
1316 operation is received by a CPU before the ICIALLUIS has completed,
1317 potentially leading to corrupted entries in the cache or TLB.
1319 config PL310_ERRATA_753970
1320 bool "PL310 errata: cache sync operation may be faulty"
1321 depends on CACHE_PL310
1323 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1325 Under some condition the effect of cache sync operation on
1326 the store buffer still remains when the operation completes.
1327 This means that the store buffer is always asked to drain and
1328 this prevents it from merging any further writes. The workaround
1329 is to replace the normal offset of cache sync operation (0x730)
1330 by another offset targeting an unmapped PL310 register 0x740.
1331 This has the same effect as the cache sync operation: store buffer
1332 drain and waiting for all buffers empty.
1334 config ARM_ERRATA_754322
1335 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1338 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1339 r3p*) erratum. A speculative memory access may cause a page table walk
1340 which starts prior to an ASID switch but completes afterwards. This
1341 can populate the micro-TLB with a stale entry which may be hit with
1342 the new ASID. This workaround places two dsb instructions in the mm
1343 switching code so that no page table walks can cross the ASID switch.
1345 config ARM_ERRATA_754327
1346 bool "ARM errata: no automatic Store Buffer drain"
1347 depends on CPU_V7 && SMP
1349 This option enables the workaround for the 754327 Cortex-A9 (prior to
1350 r2p0) erratum. The Store Buffer does not have any automatic draining
1351 mechanism and therefore a livelock may occur if an external agent
1352 continuously polls a memory location waiting to observe an update.
1353 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1354 written polling loops from denying visibility of updates to memory.
1356 config ARM_ERRATA_364296
1357 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1358 depends on CPU_V6 && !SMP
1360 This options enables the workaround for the 364296 ARM1136
1361 r0p2 erratum (possible cache data corruption with
1362 hit-under-miss enabled). It sets the undocumented bit 31 in
1363 the auxiliary control register and the FI bit in the control
1364 register, thus disabling hit-under-miss without putting the
1365 processor into full low interrupt latency mode. ARM11MPCore
1368 config ARM_ERRATA_764369
1369 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1370 depends on CPU_V7 && SMP
1372 This option enables the workaround for erratum 764369
1373 affecting Cortex-A9 MPCore with two or more processors (all
1374 current revisions). Under certain timing circumstances, a data
1375 cache line maintenance operation by MVA targeting an Inner
1376 Shareable memory region may fail to proceed up to either the
1377 Point of Coherency or to the Point of Unification of the
1378 system. This workaround adds a DSB instruction before the
1379 relevant cache maintenance functions and sets a specific bit
1380 in the diagnostic control register of the SCU.
1382 config PL310_ERRATA_769419
1383 bool "PL310 errata: no automatic Store Buffer drain"
1384 depends on CACHE_L2X0
1386 On revisions of the PL310 prior to r3p2, the Store Buffer does
1387 not automatically drain. This can cause normal, non-cacheable
1388 writes to be retained when the memory system is idle, leading
1389 to suboptimal I/O performance for drivers using coherent DMA.
1390 This option adds a write barrier to the cpu_idle loop so that,
1391 on systems with an outer cache, the store buffer is drained
1396 source "arch/arm/common/Kconfig"
1406 Find out whether you have ISA slots on your motherboard. ISA is the
1407 name of a bus system, i.e. the way the CPU talks to the other stuff
1408 inside your box. Other bus systems are PCI, EISA, MicroChannel
1409 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1410 newer boards don't support it. If you have ISA, say Y, otherwise N.
1412 # Select ISA DMA controller support
1417 # Select ISA DMA interface
1422 bool "PCI support" if MIGHT_HAVE_PCI
1424 Find out whether you have a PCI motherboard. PCI is the name of a
1425 bus system, i.e. the way the CPU talks to the other stuff inside
1426 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1427 VESA. If you have PCI, say Y, otherwise N.
1433 config PCI_NANOENGINE
1434 bool "BSE nanoEngine PCI support"
1435 depends on SA1100_NANOENGINE
1437 Enable PCI on the BSE nanoEngine board.
1442 # Select the host bridge type
1443 config PCI_HOST_VIA82C505
1445 depends on PCI && ARCH_SHARK
1448 config PCI_HOST_ITE8152
1450 depends on PCI && MACH_ARMCORE
1454 source "drivers/pci/Kconfig"
1456 source "drivers/pcmcia/Kconfig"
1460 menu "Kernel Features"
1465 This option should be selected by machines which have an SMP-
1468 The only effect of this option is to make the SMP-related
1469 options available to the user for configuration.
1472 bool "Symmetric Multi-Processing"
1473 depends on CPU_V6K || CPU_V7
1474 depends on GENERIC_CLOCKEVENTS
1477 select USE_GENERIC_SMP_HELPERS
1478 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1480 This enables support for systems with more than one CPU. If you have
1481 a system with only one CPU, like most personal computers, say N. If
1482 you have a system with more than one CPU, say Y.
1484 If you say N here, the kernel will run on single and multiprocessor
1485 machines, but will use only one CPU of a multiprocessor machine. If
1486 you say Y here, the kernel will run on many, but not all, single
1487 processor machines. On a single processor machine, the kernel will
1488 run faster if you say N here.
1490 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1491 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1492 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1494 If you don't know what to do here, say N.
1497 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1498 depends on EXPERIMENTAL
1499 depends on SMP && !XIP_KERNEL
1502 SMP kernels contain instructions which fail on non-SMP processors.
1503 Enabling this option allows the kernel to modify itself to make
1504 these instructions safe. Disabling it allows about 1K of space
1507 If you don't know what to do here, say Y.
1509 config ARM_CPU_TOPOLOGY
1510 bool "Support cpu topology definition"
1511 depends on SMP && CPU_V7
1514 Support ARM cpu topology definition. The MPIDR register defines
1515 affinity between processors which is then used to describe the cpu
1516 topology of an ARM System.
1519 bool "Multi-core scheduler support"
1520 depends on ARM_CPU_TOPOLOGY
1522 Multi-core scheduler support improves the CPU scheduler's decision
1523 making when dealing with multi-core CPU chips at a cost of slightly
1524 increased overhead in some places. If unsure say N here.
1527 bool "SMT scheduler support"
1528 depends on ARM_CPU_TOPOLOGY
1530 Improves the CPU scheduler's decision making when dealing with
1531 MultiThreading at a cost of slightly increased overhead in some
1532 places. If unsure say N here.
1537 This option enables support for the ARM system coherency unit
1544 This options enables support for the ARM timer and watchdog unit
1547 prompt "Memory split"
1550 Select the desired split between kernel and user memory.
1552 If you are not absolutely sure what you are doing, leave this
1556 bool "3G/1G user/kernel split"
1558 bool "2G/2G user/kernel split"
1560 bool "1G/3G user/kernel split"
1565 default 0x40000000 if VMSPLIT_1G
1566 default 0x80000000 if VMSPLIT_2G
1570 int "Maximum number of CPUs (2-32)"
1576 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1577 depends on SMP && HOTPLUG && EXPERIMENTAL
1579 Say Y here to experiment with turning CPUs off and on. CPUs
1580 can be controlled through /sys/devices/system/cpu.
1583 bool "Use local timer interrupts"
1586 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1588 Enable support for local timers on SMP platforms, rather then the
1589 legacy IPI broadcast method. Local timers allows the system
1590 accounting to be spread across the timer interval, preventing a
1591 "thundering herd" at every timer tick.
1595 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1596 default 355 if ARCH_U8500
1597 default 264 if MACH_H4700
1600 Maximum number of GPIOs in the system.
1602 If unsure, leave the default value.
1604 source kernel/Kconfig.preempt
1608 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1609 ARCH_S5PV210 || ARCH_EXYNOS4
1610 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1611 default AT91_TIMER_HZ if ARCH_AT91
1612 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1615 config THUMB2_KERNEL
1616 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1617 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1619 select ARM_ASM_UNIFIED
1622 By enabling this option, the kernel will be compiled in
1623 Thumb-2 mode. A compiler/assembler that understand the unified
1624 ARM-Thumb syntax is needed.
1628 config THUMB2_AVOID_R_ARM_THM_JUMP11
1629 bool "Work around buggy Thumb-2 short branch relocations in gas"
1630 depends on THUMB2_KERNEL && MODULES
1633 Various binutils versions can resolve Thumb-2 branches to
1634 locally-defined, preemptible global symbols as short-range "b.n"
1635 branch instructions.
1637 This is a problem, because there's no guarantee the final
1638 destination of the symbol, or any candidate locations for a
1639 trampoline, are within range of the branch. For this reason, the
1640 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1641 relocation in modules at all, and it makes little sense to add
1644 The symptom is that the kernel fails with an "unsupported
1645 relocation" error when loading some modules.
1647 Until fixed tools are available, passing
1648 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1649 code which hits this problem, at the cost of a bit of extra runtime
1650 stack usage in some cases.
1652 The problem is described in more detail at:
1653 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1655 Only Thumb-2 kernels are affected.
1657 Unless you are sure your tools don't have this problem, say Y.
1659 config ARM_ASM_UNIFIED
1663 bool "Use the ARM EABI to compile the kernel"
1665 This option allows for the kernel to be compiled using the latest
1666 ARM ABI (aka EABI). This is only useful if you are using a user
1667 space environment that is also compiled with EABI.
1669 Since there are major incompatibilities between the legacy ABI and
1670 EABI, especially with regard to structure member alignment, this
1671 option also changes the kernel syscall calling convention to
1672 disambiguate both ABIs and allow for backward compatibility support
1673 (selected with CONFIG_OABI_COMPAT).
1675 To use this you need GCC version 4.0.0 or later.
1678 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1679 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1682 This option preserves the old syscall interface along with the
1683 new (ARM EABI) one. It also provides a compatibility layer to
1684 intercept syscalls that have structure arguments which layout
1685 in memory differs between the legacy ABI and the new ARM EABI
1686 (only for non "thumb" binaries). This option adds a tiny
1687 overhead to all syscalls and produces a slightly larger kernel.
1688 If you know you'll be using only pure EABI user space then you
1689 can say N here. If this option is not selected and you attempt
1690 to execute a legacy ABI binary then the result will be
1691 UNPREDICTABLE (in fact it can be predicted that it won't work
1692 at all). If in doubt say Y.
1694 config ARCH_HAS_HOLES_MEMORYMODEL
1697 config ARCH_SPARSEMEM_ENABLE
1700 config ARCH_SPARSEMEM_DEFAULT
1701 def_bool ARCH_SPARSEMEM_ENABLE
1703 config ARCH_SELECT_MEMORY_MODEL
1704 def_bool ARCH_SPARSEMEM_ENABLE
1706 config HAVE_ARCH_PFN_VALID
1707 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1710 bool "High Memory Support"
1713 The address space of ARM processors is only 4 Gigabytes large
1714 and it has to accommodate user address space, kernel address
1715 space as well as some memory mapped IO. That means that, if you
1716 have a large amount of physical memory and/or IO, not all of the
1717 memory can be "permanently mapped" by the kernel. The physical
1718 memory that is not permanently mapped is called "high memory".
1720 Depending on the selected kernel/user memory split, minimum
1721 vmalloc space and actual amount of RAM, you may not need this
1722 option which should result in a slightly faster kernel.
1727 bool "Allocate 2nd-level pagetables from highmem"
1730 config HW_PERF_EVENTS
1731 bool "Enable hardware performance counter support for perf events"
1732 depends on PERF_EVENTS && CPU_HAS_PMU
1735 Enable hardware performance counter support for perf events. If
1736 disabled, perf events will use software events only.
1740 config FORCE_MAX_ZONEORDER
1741 int "Maximum zone order" if ARCH_SHMOBILE
1742 range 11 64 if ARCH_SHMOBILE
1743 default "9" if SA1111
1746 The kernel memory allocator divides physically contiguous memory
1747 blocks into "zones", where each zone is a power of two number of
1748 pages. This option selects the largest power of two that the kernel
1749 keeps in the memory allocator. If you need to allocate very large
1750 blocks of physically contiguous memory, then you may need to
1751 increase this value.
1753 This config option is actually maximum order plus one. For example,
1754 a value of 11 means that the largest free memory block is 2^10 pages.
1757 bool "Timer and CPU usage LEDs"
1758 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1759 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1760 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1761 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1762 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1763 ARCH_AT91 || ARCH_DAVINCI || \
1764 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1766 If you say Y here, the LEDs on your machine will be used
1767 to provide useful information about your current system status.
1769 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1770 be able to select which LEDs are active using the options below. If
1771 you are compiling a kernel for the EBSA-110 or the LART however, the
1772 red LED will simply flash regularly to indicate that the system is
1773 still functional. It is safe to say Y here if you have a CATS
1774 system, but the driver will do nothing.
1777 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1778 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1779 || MACH_OMAP_PERSEUS2
1781 depends on !GENERIC_CLOCKEVENTS
1782 default y if ARCH_EBSA110
1784 If you say Y here, one of the system LEDs (the green one on the
1785 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1786 will flash regularly to indicate that the system is still
1787 operational. This is mainly useful to kernel hackers who are
1788 debugging unstable kernels.
1790 The LART uses the same LED for both Timer LED and CPU usage LED
1791 functions. You may choose to use both, but the Timer LED function
1792 will overrule the CPU usage LED.
1795 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1797 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1798 || MACH_OMAP_PERSEUS2
1801 If you say Y here, the red LED will be used to give a good real
1802 time indication of CPU usage, by lighting whenever the idle task
1803 is not currently executing.
1805 The LART uses the same LED for both Timer LED and CPU usage LED
1806 functions. You may choose to use both, but the Timer LED function
1807 will overrule the CPU usage LED.
1809 config ALIGNMENT_TRAP
1811 depends on CPU_CP15_MMU
1812 default y if !ARCH_EBSA110
1813 select HAVE_PROC_CPU if PROC_FS
1815 ARM processors cannot fetch/store information which is not
1816 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1817 address divisible by 4. On 32-bit ARM processors, these non-aligned
1818 fetch/store instructions will be emulated in software if you say
1819 here, which has a severe performance impact. This is necessary for
1820 correct operation of some network protocols. With an IP-only
1821 configuration it is safe to say N, otherwise say Y.
1823 config UACCESS_WITH_MEMCPY
1824 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1825 depends on MMU && EXPERIMENTAL
1826 default y if CPU_FEROCEON
1828 Implement faster copy_to_user and clear_user methods for CPU
1829 cores where a 8-word STM instruction give significantly higher
1830 memory write throughput than a sequence of individual 32bit stores.
1832 A possible side effect is a slight increase in scheduling latency
1833 between threads sharing the same address space if they invoke
1834 such copy operations with large buffers.
1836 However, if the CPU data cache is using a write-allocate mode,
1837 this option is unlikely to provide any performance gain.
1841 prompt "Enable seccomp to safely compute untrusted bytecode"
1843 This kernel feature is useful for number crunching applications
1844 that may need to compute untrusted bytecode during their
1845 execution. By using pipes or other transports made available to
1846 the process as file descriptors supporting the read/write
1847 syscalls, it's possible to isolate those applications in
1848 their own address space using seccomp. Once seccomp is
1849 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1850 and the task is only allowed to execute a few safe syscalls
1851 defined by each seccomp mode.
1853 config CC_STACKPROTECTOR
1854 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1855 depends on EXPERIMENTAL
1857 This option turns on the -fstack-protector GCC feature. This
1858 feature puts, at the beginning of functions, a canary value on
1859 the stack just before the return address, and validates
1860 the value just before actually returning. Stack based buffer
1861 overflows (that need to overwrite this return address) now also
1862 overwrite the canary, which gets detected and the attack is then
1863 neutralized via a kernel panic.
1864 This feature requires gcc version 4.2 or above.
1866 config DEPRECATED_PARAM_STRUCT
1867 bool "Provide old way to pass kernel parameters"
1869 This was deprecated in 2001 and announced to live on for 5 years.
1870 Some old boot loaders still use this way.
1877 bool "Flattened Device Tree support"
1879 select OF_EARLY_FLATTREE
1882 Include support for flattened device tree machine descriptions.
1884 # Compressed boot loader in ROM. Yes, we really want to ask about
1885 # TEXT and BSS so we preserve their values in the config files.
1886 config ZBOOT_ROM_TEXT
1887 hex "Compressed ROM boot loader base address"
1890 The physical address at which the ROM-able zImage is to be
1891 placed in the target. Platforms which normally make use of
1892 ROM-able zImage formats normally set this to a suitable
1893 value in their defconfig file.
1895 If ZBOOT_ROM is not enabled, this has no effect.
1897 config ZBOOT_ROM_BSS
1898 hex "Compressed ROM boot loader BSS address"
1901 The base address of an area of read/write memory in the target
1902 for the ROM-able zImage which must be available while the
1903 decompressor is running. It must be large enough to hold the
1904 entire decompressed kernel plus an additional 128 KiB.
1905 Platforms which normally make use of ROM-able zImage formats
1906 normally set this to a suitable value in their defconfig file.
1908 If ZBOOT_ROM is not enabled, this has no effect.
1911 bool "Compressed boot loader in ROM/flash"
1912 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1914 Say Y here if you intend to execute your compressed kernel image
1915 (zImage) directly from ROM or flash. If unsure, say N.
1918 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1919 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1920 default ZBOOT_ROM_NONE
1922 Include experimental SD/MMC loading code in the ROM-able zImage.
1923 With this enabled it is possible to write the the ROM-able zImage
1924 kernel image to an MMC or SD card and boot the kernel straight
1925 from the reset vector. At reset the processor Mask ROM will load
1926 the first part of the the ROM-able zImage which in turn loads the
1927 rest the kernel image to RAM.
1929 config ZBOOT_ROM_NONE
1930 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1932 Do not load image from SD or MMC
1934 config ZBOOT_ROM_MMCIF
1935 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1937 Load image from MMCIF hardware block.
1939 config ZBOOT_ROM_SH_MOBILE_SDHI
1940 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1942 Load image from SDHI hardware block
1946 config ARM_APPENDED_DTB
1947 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1948 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1950 With this option, the boot code will look for a device tree binary
1951 (DTB) appended to zImage
1952 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1954 This is meant as a backward compatibility convenience for those
1955 systems with a bootloader that can't be upgraded to accommodate
1956 the documented boot protocol using a device tree.
1958 Beware that there is very little in terms of protection against
1959 this option being confused by leftover garbage in memory that might
1960 look like a DTB header after a reboot if no actual DTB is appended
1961 to zImage. Do not leave this option active in a production kernel
1962 if you don't intend to always append a DTB. Proper passing of the
1963 location into r2 of a bootloader provided DTB is always preferable
1966 config ARM_ATAG_DTB_COMPAT
1967 bool "Supplement the appended DTB with traditional ATAG information"
1968 depends on ARM_APPENDED_DTB
1970 Some old bootloaders can't be updated to a DTB capable one, yet
1971 they provide ATAGs with memory configuration, the ramdisk address,
1972 the kernel cmdline string, etc. Such information is dynamically
1973 provided by the bootloader and can't always be stored in a static
1974 DTB. To allow a device tree enabled kernel to be used with such
1975 bootloaders, this option allows zImage to extract the information
1976 from the ATAG list and store it at run time into the appended DTB.
1979 string "Default kernel command string"
1982 On some architectures (EBSA110 and CATS), there is currently no way
1983 for the boot loader to pass arguments to the kernel. For these
1984 architectures, you should supply some command-line options at build
1985 time by entering them here. As a minimum, you should specify the
1986 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1989 prompt "Kernel command line type" if CMDLINE != ""
1990 default CMDLINE_FROM_BOOTLOADER
1992 config CMDLINE_FROM_BOOTLOADER
1993 bool "Use bootloader kernel arguments if available"
1995 Uses the command-line options passed by the boot loader. If
1996 the boot loader doesn't provide any, the default kernel command
1997 string provided in CMDLINE will be used.
1999 config CMDLINE_EXTEND
2000 bool "Extend bootloader kernel arguments"
2002 The command-line arguments provided by the boot loader will be
2003 appended to the default kernel command string.
2005 config CMDLINE_FORCE
2006 bool "Always use the default kernel command string"
2008 Always use the default kernel command string, even if the boot
2009 loader passes other arguments to the kernel.
2010 This is useful if you cannot or don't want to change the
2011 command-line options your boot loader passes to the kernel.
2015 bool "Kernel Execute-In-Place from ROM"
2016 depends on !ZBOOT_ROM && !ARM_LPAE
2018 Execute-In-Place allows the kernel to run from non-volatile storage
2019 directly addressable by the CPU, such as NOR flash. This saves RAM
2020 space since the text section of the kernel is not loaded from flash
2021 to RAM. Read-write sections, such as the data section and stack,
2022 are still copied to RAM. The XIP kernel is not compressed since
2023 it has to run directly from flash, so it will take more space to
2024 store it. The flash address used to link the kernel object files,
2025 and for storing it, is configuration dependent. Therefore, if you
2026 say Y here, you must know the proper physical address where to
2027 store the kernel image depending on your own flash memory usage.
2029 Also note that the make target becomes "make xipImage" rather than
2030 "make zImage" or "make Image". The final kernel binary to put in
2031 ROM memory will be arch/arm/boot/xipImage.
2035 config XIP_PHYS_ADDR
2036 hex "XIP Kernel Physical Location"
2037 depends on XIP_KERNEL
2038 default "0x00080000"
2040 This is the physical address in your flash memory the kernel will
2041 be linked for and stored to. This address is dependent on your
2045 bool "Kexec system call (EXPERIMENTAL)"
2046 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2048 kexec is a system call that implements the ability to shutdown your
2049 current kernel, and to start another kernel. It is like a reboot
2050 but it is independent of the system firmware. And like a reboot
2051 you can start any kernel with it, not just Linux.
2053 It is an ongoing process to be certain the hardware in a machine
2054 is properly shutdown, so do not be surprised if this code does not
2055 initially work for you. It may help to enable device hotplugging
2059 bool "Export atags in procfs"
2063 Should the atags used to boot the kernel be exported in an "atags"
2064 file in procfs. Useful with kexec.
2067 bool "Build kdump crash kernel (EXPERIMENTAL)"
2068 depends on EXPERIMENTAL
2070 Generate crash dump after being started by kexec. This should
2071 be normally only set in special crash dump kernels which are
2072 loaded in the main kernel with kexec-tools into a specially
2073 reserved region and then later executed after a crash by
2074 kdump/kexec. The crash dump kernel must be compiled to a
2075 memory address not used by the main kernel
2077 For more details see Documentation/kdump/kdump.txt
2079 config AUTO_ZRELADDR
2080 bool "Auto calculation of the decompressed kernel image address"
2081 depends on !ZBOOT_ROM && !ARCH_U300
2083 ZRELADDR is the physical address where the decompressed kernel
2084 image will be placed. If AUTO_ZRELADDR is selected, the address
2085 will be determined at run-time by masking the current IP with
2086 0xf8000000. This assumes the zImage being placed in the first 128MB
2087 from start of memory.
2091 menu "CPU Power Management"
2095 source "drivers/cpufreq/Kconfig"
2098 tristate "CPUfreq driver for i.MX CPUs"
2099 depends on ARCH_MXC && CPU_FREQ
2101 This enables the CPUfreq driver for i.MX CPUs.
2103 config CPU_FREQ_SA1100
2106 config CPU_FREQ_SA1110
2109 config CPU_FREQ_INTEGRATOR
2110 tristate "CPUfreq driver for ARM Integrator CPUs"
2111 depends on ARCH_INTEGRATOR && CPU_FREQ
2114 This enables the CPUfreq driver for ARM Integrator CPUs.
2116 For details, take a look at <file:Documentation/cpu-freq>.
2122 depends on CPU_FREQ && ARCH_PXA && PXA25x
2124 select CPU_FREQ_TABLE
2125 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2130 Internal configuration node for common cpufreq on Samsung SoC
2132 config CPU_FREQ_S3C24XX
2133 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2134 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2137 This enables the CPUfreq driver for the Samsung S3C24XX family
2140 For details, take a look at <file:Documentation/cpu-freq>.
2144 config CPU_FREQ_S3C24XX_PLL
2145 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2146 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2148 Compile in support for changing the PLL frequency from the
2149 S3C24XX series CPUfreq driver. The PLL takes time to settle
2150 after a frequency change, so by default it is not enabled.
2152 This also means that the PLL tables for the selected CPU(s) will
2153 be built which may increase the size of the kernel image.
2155 config CPU_FREQ_S3C24XX_DEBUG
2156 bool "Debug CPUfreq Samsung driver core"
2157 depends on CPU_FREQ_S3C24XX
2159 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2161 config CPU_FREQ_S3C24XX_IODEBUG
2162 bool "Debug CPUfreq Samsung driver IO timing"
2163 depends on CPU_FREQ_S3C24XX
2165 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2167 config CPU_FREQ_S3C24XX_DEBUGFS
2168 bool "Export debugfs for CPUFreq"
2169 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2171 Export status information via debugfs.
2175 source "drivers/cpuidle/Kconfig"
2179 menu "Floating point emulation"
2181 comment "At least one emulation must be selected"
2184 bool "NWFPE math emulation"
2185 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2187 Say Y to include the NWFPE floating point emulator in the kernel.
2188 This is necessary to run most binaries. Linux does not currently
2189 support floating point hardware so you need to say Y here even if
2190 your machine has an FPA or floating point co-processor podule.
2192 You may say N here if you are going to load the Acorn FPEmulator
2193 early in the bootup.
2196 bool "Support extended precision"
2197 depends on FPE_NWFPE
2199 Say Y to include 80-bit support in the kernel floating-point
2200 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2201 Note that gcc does not generate 80-bit operations by default,
2202 so in most cases this option only enlarges the size of the
2203 floating point emulator without any good reason.
2205 You almost surely want to say N here.
2208 bool "FastFPE math emulation (EXPERIMENTAL)"
2209 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2211 Say Y here to include the FAST floating point emulator in the kernel.
2212 This is an experimental much faster emulator which now also has full
2213 precision for the mantissa. It does not support any exceptions.
2214 It is very simple, and approximately 3-6 times faster than NWFPE.
2216 It should be sufficient for most programs. It may be not suitable
2217 for scientific calculations, but you have to check this for yourself.
2218 If you do not feel you need a faster FP emulation you should better
2222 bool "VFP-format floating point maths"
2223 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2225 Say Y to include VFP support code in the kernel. This is needed
2226 if your hardware includes a VFP unit.
2228 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2229 release notes and additional status information.
2231 Say N if your target does not have VFP hardware.
2239 bool "Advanced SIMD (NEON) Extension support"
2240 depends on VFPv3 && CPU_V7
2242 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2247 menu "Userspace binary formats"
2249 source "fs/Kconfig.binfmt"
2252 tristate "RISC OS personality"
2255 Say Y here to include the kernel code necessary if you want to run
2256 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2257 experimental; if this sounds frightening, say N and sleep in peace.
2258 You can also say M here to compile this support as a module (which
2259 will be called arthur).
2263 menu "Power management options"
2265 source "kernel/power/Kconfig"
2267 config ARCH_SUSPEND_POSSIBLE
2268 depends on !ARCH_S5PC100
2269 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2270 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2273 config ARM_CPU_SUSPEND
2278 source "net/Kconfig"
2280 source "drivers/Kconfig"
2284 source "arch/arm/Kconfig.debug"
2286 source "security/Kconfig"
2288 source "crypto/Kconfig"
2290 source "lib/Kconfig"