4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAVE_CUSTOM_GPIO_H
7 select ARCH_SUPPORTS_ATOMIC_RMW
8 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
9 select ARCH_WANT_IPC_PARSE_VERSION
10 select BUILDTIME_EXTABLE_SORT if MMU
11 select CPU_PM if (SUSPEND || CPU_IDLE)
12 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN && MMU
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
15 select GENERIC_IRQ_PROBE
16 select GENERIC_IRQ_SHOW
17 select GENERIC_PCI_IOMAP
18 select GENERIC_SMP_IDLE_THREAD
19 select GENERIC_IDLE_POLL_SETUP
20 select GENERIC_STRNCPY_FROM_USER
21 select GENERIC_STRNLEN_USER
22 select HARDIRQS_SW_RESEND
23 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
25 select HAVE_ARCH_SECCOMP_FILTER
26 select HAVE_ARCH_TRACEHOOK
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_DEBUG_KMEMLEAK
30 select HAVE_DMA_API_DEBUG
32 select HAVE_DMA_CONTIGUOUS if MMU
33 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
34 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
35 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
36 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
37 select HAVE_GENERIC_DMA_COHERENT
38 select HAVE_GENERIC_HARDIRQS
39 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
40 select HAVE_IDE if PCI || ISA || PCMCIA
41 select HAVE_IRQ_TIME_ACCOUNTING
42 select HAVE_KERNEL_GZIP
43 select HAVE_KERNEL_LZMA
44 select HAVE_KERNEL_LZO
46 select HAVE_KPROBES if !XIP_KERNEL
47 select HAVE_KRETPROBES if (HAVE_KPROBES)
49 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
50 select HAVE_PERF_EVENTS
51 select HAVE_REGS_AND_STACK_ACCESS_API
52 select HAVE_SYSCALL_TRACEPOINTS
55 select PERF_USE_VMALLOC
57 select SYS_SUPPORTS_APM_EMULATION
58 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
59 select MODULES_USE_ELF_REL
60 select CLONE_BACKWARDS
61 select OLD_SIGSUSPEND3
63 select HAVE_CONTEXT_TRACKING
65 The ARM series is a line of low-power-consumption RISC chip designs
66 licensed by ARM Ltd and targeted at embedded applications and
67 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
68 manufactured, but legacy ARM-based PC hardware remains popular in
69 Europe. There is an ARM Linux project with a web page at
70 <http://www.arm.linux.org.uk/>.
72 config ARM_HAS_SG_CHAIN
75 config NEED_SG_DMA_LENGTH
78 config ARM_DMA_USE_IOMMU
80 select ARM_HAS_SG_CHAIN
81 select NEED_SG_DMA_LENGTH
85 config ARM_DMA_IOMMU_ALIGNMENT
86 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
90 DMA mapping framework by default aligns all buffers to the smallest
91 PAGE_SIZE order which is greater than or equal to the requested buffer
92 size. This works well for buffers up to a few hundreds kilobytes, but
93 for larger buffers it just a waste of address space. Drivers which has
94 relatively small addressing window (like 64Mib) might run out of
95 virtual space with just a few allocations.
97 With this parameter you can specify the maximum PAGE_SIZE order for
98 DMA IOMMU buffers. Larger buffers will be aligned only to this
99 specified order. The order is expressed as a power of two multiplied
107 config MIGHT_HAVE_PCI
110 config SYS_SUPPORTS_APM_EMULATION
115 select GENERIC_ALLOCATOR
126 The Extended Industry Standard Architecture (EISA) bus was
127 developed as an open alternative to the IBM MicroChannel bus.
129 The EISA bus provided some of the features of the IBM MicroChannel
130 bus while maintaining backward compatibility with cards made for
131 the older ISA bus. The EISA bus saw limited use between 1988 and
132 1995 when it was made obsolete by the PCI bus.
134 Say Y here if you are building a kernel for an EISA-based machine.
141 config STACKTRACE_SUPPORT
145 config HAVE_LATENCYTOP_SUPPORT
150 config LOCKDEP_SUPPORT
154 config TRACE_IRQFLAGS_SUPPORT
158 config RWSEM_GENERIC_SPINLOCK
162 config RWSEM_XCHGADD_ALGORITHM
165 config ARCH_HAS_ILOG2_U32
168 config ARCH_HAS_ILOG2_U64
171 config ARCH_HAS_CPUFREQ
174 Internal node to signify that the ARCH has CPUFREQ support
175 and that the relevant menu configurations are displayed for
178 config GENERIC_HWEIGHT
182 config GENERIC_CALIBRATE_DELAY
186 config ARCH_MAY_HAVE_PC_FDC
192 config NEED_DMA_MAP_STATE
195 config ARCH_HAS_DMA_SET_COHERENT_MASK
198 config GENERIC_ISA_DMA
204 config NEED_RET_TO_USER
212 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
213 default DRAM_BASE if REMAP_VECTORS_TO_RAM
216 The base address of exception vectors. This must be two pages
219 config ARM_PATCH_PHYS_VIRT
220 bool "Patch physical to virtual translations at runtime" if EMBEDDED
222 depends on !XIP_KERNEL && MMU
223 depends on !ARCH_REALVIEW || !SPARSEMEM
225 Patch phys-to-virt and virt-to-phys translation functions at
226 boot and module load time according to the position of the
227 kernel in system memory.
229 This can only be used with non-XIP MMU kernels where the base
230 of physical memory is at a 16MB boundary.
232 Only disable this option if you know that you do not require
233 this feature (eg, building a kernel for a single machine) and
234 you need to shrink the kernel to the minimal size.
236 config NEED_MACH_GPIO_H
239 Select this when mach/gpio.h is required to provide special
240 definitions for this platform. The need for mach/gpio.h should
241 be avoided when possible.
243 config NEED_MACH_IO_H
246 Select this when mach/io.h is required to provide special
247 definitions for this platform. The need for mach/io.h should
248 be avoided when possible.
250 config NEED_MACH_MEMORY_H
253 Select this when mach/memory.h is required to provide special
254 definitions for this platform. The need for mach/memory.h should
255 be avoided when possible.
258 hex "Physical address of main memory" if MMU
259 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
260 default DRAM_BASE if !MMU
262 Please provide the physical address corresponding to the
263 location of main memory in your system.
269 source "init/Kconfig"
271 source "kernel/Kconfig.freezer"
276 bool "MMU-based Paged Memory Management Support"
279 Select if you want MMU-based virtualised addressing space
280 support by paged memory management. If unsure, say 'Y'.
283 # The "ARM system type" choice list is ordered alphabetically by option
284 # text. Please add new entries in the option alphabetic order.
287 prompt "ARM system type"
288 default ARCH_VERSATILE if !MMU
289 default ARCH_MULTIPLATFORM if MMU
291 config ARCH_MULTIPLATFORM
292 bool "Allow multiple platforms to be selected"
294 select ARM_PATCH_PHYS_VIRT
297 select MULTI_IRQ_HANDLER
301 config ARCH_INTEGRATOR
302 bool "ARM Ltd. Integrator family"
303 select ARCH_HAS_CPUFREQ
306 select COMMON_CLK_VERSATILE
307 select GENERIC_CLOCKEVENTS
310 select MULTI_IRQ_HANDLER
311 select NEED_MACH_MEMORY_H
312 select PLAT_VERSATILE
314 select VERSATILE_FPGA_IRQ
316 Support for ARM's Integrator platform.
319 bool "ARM Ltd. RealView family"
320 select ARCH_WANT_OPTIONAL_GPIOLIB
322 select ARM_TIMER_SP804
324 select COMMON_CLK_VERSATILE
325 select GENERIC_CLOCKEVENTS
326 select GPIO_PL061 if GPIOLIB
328 select NEED_MACH_MEMORY_H
329 select PLAT_VERSATILE
330 select PLAT_VERSATILE_CLCD
332 This enables support for ARM Ltd RealView boards.
334 config ARCH_VERSATILE
335 bool "ARM Ltd. Versatile family"
336 select ARCH_WANT_OPTIONAL_GPIOLIB
338 select ARM_TIMER_SP804
341 select GENERIC_CLOCKEVENTS
342 select HAVE_MACH_CLKDEV
344 select PLAT_VERSATILE
345 select PLAT_VERSATILE_CLCD
346 select PLAT_VERSATILE_CLOCK
347 select VERSATILE_FPGA_IRQ
349 This enables support for ARM Ltd Versatile board.
353 select ARCH_REQUIRE_GPIOLIB
357 select NEED_MACH_GPIO_H
358 select NEED_MACH_IO_H if PCCARD
360 select PINCTRL_AT91 if USE_OF
362 This enables support for systems based on Atmel
363 AT91RM9200 and AT91SAM9* processors.
366 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
367 select ARCH_REQUIRE_GPIOLIB
372 select GENERIC_CLOCKEVENTS
373 select MULTI_IRQ_HANDLER
374 select NEED_MACH_MEMORY_H
377 Support for Cirrus Logic 711x/721x/731x based boards.
380 bool "Cortina Systems Gemini"
381 select ARCH_REQUIRE_GPIOLIB
382 select ARCH_USES_GETTIMEOFFSET
383 select NEED_MACH_GPIO_H
386 Support for the Cortina Systems Gemini family SoCs
390 select ARCH_USES_GETTIMEOFFSET
393 select NEED_MACH_IO_H
394 select NEED_MACH_MEMORY_H
397 This is an evaluation board for the StrongARM processor available
398 from Digital. It has limited hardware on-board, including an
399 Ethernet interface, two PCMCIA sockets, two serial ports and a
404 select ARCH_HAS_HOLES_MEMORYMODEL
405 select ARCH_REQUIRE_GPIOLIB
406 select ARCH_USES_GETTIMEOFFSET
411 select NEED_MACH_MEMORY_H
413 This enables support for the Cirrus EP93xx series of CPUs.
415 config ARCH_FOOTBRIDGE
419 select GENERIC_CLOCKEVENTS
421 select NEED_MACH_IO_H if !MMU
422 select NEED_MACH_MEMORY_H
424 Support for systems based on the DC21285 companion chip
425 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
428 bool "Hilscher NetX based"
432 select GENERIC_CLOCKEVENTS
434 This enables support for systems based on the Hilscher NetX Soc
439 select ARCH_SUPPORTS_MSI
441 select NEED_MACH_MEMORY_H
442 select NEED_RET_TO_USER
447 Support for Intel's IOP13XX (XScale) family of processors.
452 select ARCH_REQUIRE_GPIOLIB
454 select NEED_MACH_GPIO_H
455 select NEED_RET_TO_USER
459 Support for Intel's 80219 and IOP32X (XScale) family of
465 select ARCH_REQUIRE_GPIOLIB
467 select NEED_MACH_GPIO_H
468 select NEED_RET_TO_USER
472 Support for Intel's IOP33X (XScale) family of processors.
477 select ARCH_HAS_DMA_SET_COHERENT_MASK
478 select ARCH_SUPPORTS_BIG_ENDIAN
479 select ARCH_REQUIRE_GPIOLIB
482 select DMABOUNCE if PCI
483 select GENERIC_CLOCKEVENTS
484 select MIGHT_HAVE_PCI
485 select NEED_MACH_IO_H
486 select USB_EHCI_BIG_ENDIAN_MMIO
487 select USB_EHCI_BIG_ENDIAN_DESC
489 Support for Intel's IXP4XX (XScale) family of processors.
493 select ARCH_REQUIRE_GPIOLIB
495 select GENERIC_CLOCKEVENTS
496 select MIGHT_HAVE_PCI
499 select PLAT_ORION_LEGACY
500 select USB_ARCH_HAS_EHCI
503 Support for the Marvell Dove SoC 88AP510
506 bool "Marvell Kirkwood"
507 select ARCH_REQUIRE_GPIOLIB
509 select GENERIC_CLOCKEVENTS
513 select PINCTRL_KIRKWOOD
514 select PLAT_ORION_LEGACY
517 Support for the following Marvell Kirkwood series SoCs:
518 88F6180, 88F6192 and 88F6281.
521 bool "Marvell MV78xx0"
522 select ARCH_REQUIRE_GPIOLIB
524 select GENERIC_CLOCKEVENTS
526 select PLAT_ORION_LEGACY
529 Support for the following Marvell MV78xx0 series SoCs:
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
539 select PLAT_ORION_LEGACY
542 Support for the following Marvell Orion 5x series SoCs:
543 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
544 Orion-2 (5281), Orion-1-90 (6183).
547 bool "Marvell PXA168/910/MMP2"
549 select ARCH_REQUIRE_GPIOLIB
551 select GENERIC_ALLOCATOR
552 select GENERIC_CLOCKEVENTS
555 select NEED_MACH_GPIO_H
560 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
563 bool "Micrel/Kendin KS8695"
564 select ARCH_REQUIRE_GPIOLIB
567 select GENERIC_CLOCKEVENTS
568 select NEED_MACH_MEMORY_H
570 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571 System-on-Chip devices.
574 bool "Nuvoton W90X900 CPU"
575 select ARCH_REQUIRE_GPIOLIB
579 select GENERIC_CLOCKEVENTS
581 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582 At present, the w90x900 has been renamed nuc900, regarding
583 the ARM series product line, you can login the following
584 link address to know more.
586 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
591 select ARCH_REQUIRE_GPIOLIB
596 select GENERIC_CLOCKEVENTS
599 select USB_ARCH_HAS_OHCI
602 Support for the NXP LPC32XX family of processors
605 bool "PXA2xx/PXA3xx-based"
607 select ARCH_HAS_CPUFREQ
609 select ARCH_REQUIRE_GPIOLIB
610 select ARM_CPU_SUSPEND if PM
614 select GENERIC_CLOCKEVENTS
617 select MULTI_IRQ_HANDLER
618 select NEED_MACH_GPIO_H
622 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
626 select ARCH_REQUIRE_GPIOLIB
628 select GENERIC_CLOCKEVENTS
631 Support for Qualcomm MSM/QSD based systems. This runs on the
632 apps processor of the MSM/QSD and depends on a shared memory
633 interface to the modem processor which runs the baseband
634 stack and controls some vital subsystems
635 (clock and power control, etc).
638 bool "Renesas SH-Mobile / R-Mobile"
640 select GENERIC_CLOCKEVENTS
641 select HAVE_ARM_SCU if SMP
642 select HAVE_ARM_TWD if LOCAL_TIMERS
644 select HAVE_MACH_CLKDEV
646 select MIGHT_HAVE_CACHE_L2X0
647 select MULTI_IRQ_HANDLER
648 select NEED_MACH_MEMORY_H
650 select PINCTRL if ARCH_WANT_OPTIONAL_GPIOLIB
651 select PM_GENERIC_DOMAINS if PM
654 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
659 select ARCH_MAY_HAVE_PC_FDC
660 select ARCH_SPARSEMEM_ENABLE
661 select ARCH_USES_GETTIMEOFFSET
664 select HAVE_PATA_PLATFORM
666 select NEED_MACH_IO_H
667 select NEED_MACH_MEMORY_H
671 On the Acorn Risc-PC, Linux can support the internal IDE disk and
672 CD-ROM interface, serial and parallel port, and the floppy drive.
676 select ARCH_HAS_CPUFREQ
678 select ARCH_REQUIRE_GPIOLIB
679 select ARCH_SPARSEMEM_ENABLE
684 select GENERIC_CLOCKEVENTS
687 select NEED_MACH_GPIO_H
688 select NEED_MACH_MEMORY_H
691 Support for StrongARM 11x0 based boards.
694 bool "Samsung S3C24XX SoCs"
695 select ARCH_HAS_CPUFREQ
696 select ARCH_REQUIRE_GPIOLIB
699 select GENERIC_CLOCKEVENTS
701 select HAVE_S3C2410_I2C if I2C
702 select HAVE_S3C2410_WATCHDOG if WATCHDOG
703 select HAVE_S3C_RTC if RTC_CLASS
704 select MULTI_IRQ_HANDLER
705 select NEED_MACH_GPIO_H
706 select NEED_MACH_IO_H
708 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
709 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
710 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
711 Samsung SMDK2410 development board (and derivatives).
714 bool "Samsung S3C64XX"
715 select ARCH_HAS_CPUFREQ
716 select ARCH_REQUIRE_GPIOLIB
721 select GENERIC_CLOCKEVENTS
723 select HAVE_S3C2410_I2C if I2C
724 select HAVE_S3C2410_WATCHDOG if WATCHDOG
726 select NEED_MACH_GPIO_H
730 select S3C_GPIO_TRACK
731 select SAMSUNG_CLKSRC
732 select SAMSUNG_GPIOLIB_4BIT
733 select SAMSUNG_IRQ_VIC_TIMER
734 select USB_ARCH_HAS_OHCI
736 Samsung S3C64XX series based systems
739 bool "Samsung S5P6440 S5P6450"
743 select GENERIC_CLOCKEVENTS
745 select HAVE_S3C2410_I2C if I2C
746 select HAVE_S3C2410_WATCHDOG if WATCHDOG
747 select HAVE_S3C_RTC if RTC_CLASS
748 select NEED_MACH_GPIO_H
750 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
754 bool "Samsung S5PC100"
755 select ARCH_REQUIRE_GPIOLIB
759 select GENERIC_CLOCKEVENTS
761 select HAVE_S3C2410_I2C if I2C
762 select HAVE_S3C2410_WATCHDOG if WATCHDOG
763 select HAVE_S3C_RTC if RTC_CLASS
764 select NEED_MACH_GPIO_H
766 Samsung S5PC100 series based systems
769 bool "Samsung S5PV210/S5PC110"
770 select ARCH_HAS_CPUFREQ
771 select ARCH_HAS_HOLES_MEMORYMODEL
772 select ARCH_SPARSEMEM_ENABLE
776 select GENERIC_CLOCKEVENTS
778 select HAVE_S3C2410_I2C if I2C
779 select HAVE_S3C2410_WATCHDOG if WATCHDOG
780 select HAVE_S3C_RTC if RTC_CLASS
781 select NEED_MACH_GPIO_H
782 select NEED_MACH_MEMORY_H
784 Samsung S5PV210/S5PC110 series based systems
787 bool "Samsung EXYNOS"
788 select ARCH_HAS_CPUFREQ
789 select ARCH_HAS_HOLES_MEMORYMODEL
790 select ARCH_SPARSEMEM_ENABLE
794 select GENERIC_CLOCKEVENTS
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
798 select HAVE_S3C_RTC if RTC_CLASS
799 select NEED_MACH_GPIO_H
800 select NEED_MACH_MEMORY_H
802 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
806 select ARCH_USES_GETTIMEOFFSET
810 select NEED_MACH_MEMORY_H
815 Support for the StrongARM based Digital DNARD machine, also known
816 as "Shark" (<http://www.shark-linux.de/shark.html>).
819 bool "ST-Ericsson U300 Series"
821 select ARCH_REQUIRE_GPIOLIB
823 select ARM_PATCH_PHYS_VIRT
829 select GENERIC_CLOCKEVENTS
833 Support for ST-Ericsson U300 series mobile platforms.
837 select ARCH_HAS_HOLES_MEMORYMODEL
838 select ARCH_REQUIRE_GPIOLIB
840 select GENERIC_ALLOCATOR
841 select GENERIC_CLOCKEVENTS
842 select GENERIC_IRQ_CHIP
844 select NEED_MACH_GPIO_H
848 Support for TI's DaVinci platform.
853 select ARCH_HAS_CPUFREQ
854 select ARCH_HAS_HOLES_MEMORYMODEL
856 select ARCH_REQUIRE_GPIOLIB
859 select GENERIC_CLOCKEVENTS
860 select GENERIC_IRQ_CHIP
864 select NEED_MACH_IO_H if PCCARD
865 select NEED_MACH_MEMORY_H
867 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
870 bool "Spreadtrum SOC"
871 select ARCH_REQUIRE_GPIOLIB
873 select GENERIC_CLOCKEVENTS
874 select NEED_MACH_GPIO_H
877 Support for Spreadtrum sci based systems.
881 menu "Multiple platform selection"
882 depends on ARCH_MULTIPLATFORM
884 comment "CPU Core family selection"
887 bool "ARMv4 based platforms (FA526, StrongARM)"
888 depends on !ARCH_MULTI_V6_V7
889 select ARCH_MULTI_V4_V5
891 config ARCH_MULTI_V4T
892 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
893 depends on !ARCH_MULTI_V6_V7
894 select ARCH_MULTI_V4_V5
897 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
898 depends on !ARCH_MULTI_V6_V7
899 select ARCH_MULTI_V4_V5
901 config ARCH_MULTI_V4_V5
905 bool "ARMv6 based platforms (ARM11)"
906 select ARCH_MULTI_V6_V7
910 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
912 select ARCH_MULTI_V6_V7
915 config ARCH_MULTI_V6_V7
918 config ARCH_MULTI_CPU_AUTO
919 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
925 # This is sorted alphabetically by mach-* pathname. However, plat-*
926 # Kconfigs may be included either alphabetically (according to the
927 # plat- suffix) or along side the corresponding mach-* source.
929 source "arch/arm/mach-mvebu/Kconfig"
931 source "arch/arm/mach-at91/Kconfig"
933 source "arch/arm/mach-bcm/Kconfig"
935 source "arch/arm/mach-bcm2835/Kconfig"
937 source "arch/arm/mach-clps711x/Kconfig"
939 source "arch/arm/mach-cns3xxx/Kconfig"
941 source "arch/arm/mach-davinci/Kconfig"
943 source "arch/arm/mach-dove/Kconfig"
945 source "arch/arm/mach-ep93xx/Kconfig"
947 source "arch/arm/mach-footbridge/Kconfig"
949 source "arch/arm/mach-gemini/Kconfig"
951 source "arch/arm/mach-highbank/Kconfig"
953 source "arch/arm/mach-integrator/Kconfig"
955 source "arch/arm/mach-iop32x/Kconfig"
957 source "arch/arm/mach-iop33x/Kconfig"
959 source "arch/arm/mach-iop13xx/Kconfig"
961 source "arch/arm/mach-ixp4xx/Kconfig"
963 source "arch/arm/mach-kirkwood/Kconfig"
965 source "arch/arm/mach-ks8695/Kconfig"
967 source "arch/arm/mach-msm/Kconfig"
969 source "arch/arm/mach-mv78xx0/Kconfig"
971 source "arch/arm/mach-imx/Kconfig"
973 source "arch/arm/mach-mxs/Kconfig"
975 source "arch/arm/mach-netx/Kconfig"
977 source "arch/arm/mach-nomadik/Kconfig"
979 source "arch/arm/plat-omap/Kconfig"
981 source "arch/arm/mach-omap1/Kconfig"
983 source "arch/arm/mach-omap2/Kconfig"
985 source "arch/arm/mach-orion5x/Kconfig"
987 source "arch/arm/mach-picoxcell/Kconfig"
989 source "arch/arm/mach-pxa/Kconfig"
990 source "arch/arm/plat-pxa/Kconfig"
992 source "arch/arm/mach-mmp/Kconfig"
994 source "arch/arm/mach-realview/Kconfig"
996 source "arch/arm/mach-sa1100/Kconfig"
998 source "arch/arm/plat-samsung/Kconfig"
1000 source "arch/arm/mach-socfpga/Kconfig"
1002 source "arch/arm/mach-spear/Kconfig"
1004 source "arch/arm/mach-s3c24xx/Kconfig"
1007 source "arch/arm/mach-s3c64xx/Kconfig"
1010 source "arch/arm/mach-s5p64x0/Kconfig"
1012 source "arch/arm/mach-s5pc100/Kconfig"
1014 source "arch/arm/mach-s5pv210/Kconfig"
1016 source "arch/arm/mach-exynos/Kconfig"
1018 source "arch/arm/mach-shmobile/Kconfig"
1020 source "arch/arm/mach-sunxi/Kconfig"
1022 source "arch/arm/mach-prima2/Kconfig"
1024 source "arch/arm/mach-tegra/Kconfig"
1026 source "arch/arm/mach-u300/Kconfig"
1028 source "arch/arm/mach-ux500/Kconfig"
1030 source "arch/arm/mach-versatile/Kconfig"
1032 source "arch/arm/mach-vexpress/Kconfig"
1033 source "arch/arm/plat-versatile/Kconfig"
1035 source "arch/arm/mach-virt/Kconfig"
1037 source "arch/arm/mach-vt8500/Kconfig"
1039 source "arch/arm/mach-w90x900/Kconfig"
1041 source "arch/arm/mach-zynq/Kconfig"
1043 source "arch/arm/mach-sc/Kconfig"
1045 # Definitions to make life easier
1051 select GENERIC_CLOCKEVENTS
1057 select GENERIC_IRQ_CHIP
1060 config PLAT_ORION_LEGACY
1067 config PLAT_VERSATILE
1070 config ARM_TIMER_SP804
1073 select CLKSRC_OF if OF
1075 source arch/arm/mm/Kconfig
1079 default 16 if ARCH_EP93XX
1083 bool "Enable iWMMXt support" if !CPU_PJ4
1084 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1085 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1087 Enable support for iWMMXt context switching at run time if
1088 running on a CPU that supports it.
1092 depends on CPU_XSCALE
1095 config MULTI_IRQ_HANDLER
1098 Allow each machine to specify it's own IRQ handler at run time.
1101 source "arch/arm/Kconfig-nommu"
1104 config PJ4B_ERRATA_4742
1105 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1106 depends on CPU_PJ4B && MACH_ARMADA_370
1109 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1110 Event (WFE) IDLE states, a specific timing sensitivity exists between
1111 the retiring WFI/WFE instructions and the newly issued subsequent
1112 instructions. This sensitivity can result in a CPU hang scenario.
1114 The software must insert either a Data Synchronization Barrier (DSB)
1115 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1118 config ARM_ERRATA_326103
1119 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1122 Executing a SWP instruction to read-only memory does not set bit 11
1123 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1124 treat the access as a read, preventing a COW from occurring and
1125 causing the faulting task to livelock.
1127 config ARM_ERRATA_411920
1128 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1129 depends on CPU_V6 || CPU_V6K
1131 Invalidation of the Instruction Cache operation can
1132 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1133 It does not affect the MPCore. This option enables the ARM Ltd.
1134 recommended workaround.
1136 config ARM_ERRATA_430973
1137 bool "ARM errata: Stale prediction on replaced interworking branch"
1140 This option enables the workaround for the 430973 Cortex-A8
1141 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1142 interworking branch is replaced with another code sequence at the
1143 same virtual address, whether due to self-modifying code or virtual
1144 to physical address re-mapping, Cortex-A8 does not recover from the
1145 stale interworking branch prediction. This results in Cortex-A8
1146 executing the new code sequence in the incorrect ARM or Thumb state.
1147 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1148 and also flushes the branch target cache at every context switch.
1149 Note that setting specific bits in the ACTLR register may not be
1150 available in non-secure mode.
1152 config ARM_ERRATA_458693
1153 bool "ARM errata: Processor deadlock when a false hazard is created"
1155 depends on !ARCH_MULTIPLATFORM
1157 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1158 erratum. For very specific sequences of memory operations, it is
1159 possible for a hazard condition intended for a cache line to instead
1160 be incorrectly associated with a different cache line. This false
1161 hazard might then cause a processor deadlock. The workaround enables
1162 the L1 caching of the NEON accesses and disables the PLD instruction
1163 in the ACTLR register. Note that setting specific bits in the ACTLR
1164 register may not be available in non-secure mode.
1166 config ARM_ERRATA_460075
1167 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1169 depends on !ARCH_MULTIPLATFORM
1171 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1172 erratum. Any asynchronous access to the L2 cache may encounter a
1173 situation in which recent store transactions to the L2 cache are lost
1174 and overwritten with stale memory contents from external memory. The
1175 workaround disables the write-allocate mode for the L2 cache via the
1176 ACTLR register. Note that setting specific bits in the ACTLR register
1177 may not be available in non-secure mode.
1179 config ARM_ERRATA_742230
1180 bool "ARM errata: DMB operation may be faulty"
1181 depends on CPU_V7 && SMP
1182 depends on !ARCH_MULTIPLATFORM
1184 This option enables the workaround for the 742230 Cortex-A9
1185 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1186 between two write operations may not ensure the correct visibility
1187 ordering of the two writes. This workaround sets a specific bit in
1188 the diagnostic register of the Cortex-A9 which causes the DMB
1189 instruction to behave as a DSB, ensuring the correct behaviour of
1192 config ARM_ERRATA_742231
1193 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1194 depends on CPU_V7 && SMP
1195 depends on !ARCH_MULTIPLATFORM
1197 This option enables the workaround for the 742231 Cortex-A9
1198 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1199 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1200 accessing some data located in the same cache line, may get corrupted
1201 data due to bad handling of the address hazard when the line gets
1202 replaced from one of the CPUs at the same time as another CPU is
1203 accessing it. This workaround sets specific bits in the diagnostic
1204 register of the Cortex-A9 which reduces the linefill issuing
1205 capabilities of the processor.
1207 config PL310_ERRATA_588369
1208 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1209 depends on CACHE_L2X0
1211 The PL310 L2 cache controller implements three types of Clean &
1212 Invalidate maintenance operations: by Physical Address
1213 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1214 They are architecturally defined to behave as the execution of a
1215 clean operation followed immediately by an invalidate operation,
1216 both performing to the same memory location. This functionality
1217 is not correctly implemented in PL310 as clean lines are not
1218 invalidated as a result of these operations.
1220 config ARM_ERRATA_643719
1221 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1222 depends on CPU_V7 && SMP
1224 This option enables the workaround for the 643719 Cortex-A9 (prior to
1225 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1226 register returns zero when it should return one. The workaround
1227 corrects this value, ensuring cache maintenance operations which use
1228 it behave as intended and avoiding data corruption.
1230 config ARM_ERRATA_720789
1231 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1234 This option enables the workaround for the 720789 Cortex-A9 (prior to
1235 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1236 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1237 As a consequence of this erratum, some TLB entries which should be
1238 invalidated are not, resulting in an incoherency in the system page
1239 tables. The workaround changes the TLB flushing routines to invalidate
1240 entries regardless of the ASID.
1242 config PL310_ERRATA_727915
1243 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1244 depends on CACHE_L2X0
1246 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1247 operation (offset 0x7FC). This operation runs in background so that
1248 PL310 can handle normal accesses while it is in progress. Under very
1249 rare circumstances, due to this erratum, write data can be lost when
1250 PL310 treats a cacheable write transaction during a Clean &
1251 Invalidate by Way operation.
1253 config ARM_ERRATA_743622
1254 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1256 depends on !ARCH_MULTIPLATFORM
1258 This option enables the workaround for the 743622 Cortex-A9
1259 (r2p*) erratum. Under very rare conditions, a faulty
1260 optimisation in the Cortex-A9 Store Buffer may lead to data
1261 corruption. This workaround sets a specific bit in the diagnostic
1262 register of the Cortex-A9 which disables the Store Buffer
1263 optimisation, preventing the defect from occurring. This has no
1264 visible impact on the overall performance or power consumption of the
1267 config ARM_ERRATA_751472
1268 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1270 depends on !ARCH_MULTIPLATFORM
1272 This option enables the workaround for the 751472 Cortex-A9 (prior
1273 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1274 completion of a following broadcasted operation if the second
1275 operation is received by a CPU before the ICIALLUIS has completed,
1276 potentially leading to corrupted entries in the cache or TLB.
1278 config PL310_ERRATA_753970
1279 bool "PL310 errata: cache sync operation may be faulty"
1280 depends on CACHE_PL310
1282 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1284 Under some condition the effect of cache sync operation on
1285 the store buffer still remains when the operation completes.
1286 This means that the store buffer is always asked to drain and
1287 this prevents it from merging any further writes. The workaround
1288 is to replace the normal offset of cache sync operation (0x730)
1289 by another offset targeting an unmapped PL310 register 0x740.
1290 This has the same effect as the cache sync operation: store buffer
1291 drain and waiting for all buffers empty.
1293 config ARM_ERRATA_754322
1294 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1297 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1298 r3p*) erratum. A speculative memory access may cause a page table walk
1299 which starts prior to an ASID switch but completes afterwards. This
1300 can populate the micro-TLB with a stale entry which may be hit with
1301 the new ASID. This workaround places two dsb instructions in the mm
1302 switching code so that no page table walks can cross the ASID switch.
1304 config ARM_ERRATA_754327
1305 bool "ARM errata: no automatic Store Buffer drain"
1306 depends on CPU_V7 && SMP
1308 This option enables the workaround for the 754327 Cortex-A9 (prior to
1309 r2p0) erratum. The Store Buffer does not have any automatic draining
1310 mechanism and therefore a livelock may occur if an external agent
1311 continuously polls a memory location waiting to observe an update.
1312 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1313 written polling loops from denying visibility of updates to memory.
1315 config ARM_ERRATA_364296
1316 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1317 depends on CPU_V6 && !SMP
1319 This options enables the workaround for the 364296 ARM1136
1320 r0p2 erratum (possible cache data corruption with
1321 hit-under-miss enabled). It sets the undocumented bit 31 in
1322 the auxiliary control register and the FI bit in the control
1323 register, thus disabling hit-under-miss without putting the
1324 processor into full low interrupt latency mode. ARM11MPCore
1327 config ARM_ERRATA_764369
1328 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1329 depends on CPU_V7 && SMP
1331 This option enables the workaround for erratum 764369
1332 affecting Cortex-A9 MPCore with two or more processors (all
1333 current revisions). Under certain timing circumstances, a data
1334 cache line maintenance operation by MVA targeting an Inner
1335 Shareable memory region may fail to proceed up to either the
1336 Point of Coherency or to the Point of Unification of the
1337 system. This workaround adds a DSB instruction before the
1338 relevant cache maintenance functions and sets a specific bit
1339 in the diagnostic control register of the SCU.
1341 config PL310_ERRATA_769419
1342 bool "PL310 errata: no automatic Store Buffer drain"
1343 depends on CACHE_L2X0
1345 On revisions of the PL310 prior to r3p2, the Store Buffer does
1346 not automatically drain. This can cause normal, non-cacheable
1347 writes to be retained when the memory system is idle, leading
1348 to suboptimal I/O performance for drivers using coherent DMA.
1349 This option adds a write barrier to the cpu_idle loop so that,
1350 on systems with an outer cache, the store buffer is drained
1353 config ARM_ERRATA_775420
1354 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1357 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1358 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1359 operation aborts with MMU exception, it might cause the processor
1360 to deadlock. This workaround puts DSB before executing ISB if
1361 an abort may occur on cache maintenance.
1363 config ARM_ERRATA_798181
1364 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1365 depends on CPU_V7 && SMP
1367 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1368 adequately shooting down all use of the old entries. This
1369 option enables the Linux kernel workaround for this erratum
1370 which sends an IPI to the CPUs that are running the same ASID
1371 as the one being invalidated.
1375 source "arch/arm/common/Kconfig"
1385 Find out whether you have ISA slots on your motherboard. ISA is the
1386 name of a bus system, i.e. the way the CPU talks to the other stuff
1387 inside your box. Other bus systems are PCI, EISA, MicroChannel
1388 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1389 newer boards don't support it. If you have ISA, say Y, otherwise N.
1391 # Select ISA DMA controller support
1396 # Select ISA DMA interface
1401 bool "PCI support" if MIGHT_HAVE_PCI
1403 Find out whether you have a PCI motherboard. PCI is the name of a
1404 bus system, i.e. the way the CPU talks to the other stuff inside
1405 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1406 VESA. If you have PCI, say Y, otherwise N.
1412 config PCI_NANOENGINE
1413 bool "BSE nanoEngine PCI support"
1414 depends on SA1100_NANOENGINE
1416 Enable PCI on the BSE nanoEngine board.
1421 # Select the host bridge type
1422 config PCI_HOST_VIA82C505
1424 depends on PCI && ARCH_SHARK
1427 config PCI_HOST_ITE8152
1429 depends on PCI && MACH_ARMCORE
1433 source "drivers/pci/Kconfig"
1435 source "drivers/pcmcia/Kconfig"
1439 menu "Kernel Features"
1444 This option should be selected by machines which have an SMP-
1447 The only effect of this option is to make the SMP-related
1448 options available to the user for configuration.
1451 bool "Symmetric Multi-Processing"
1452 depends on CPU_V6K || CPU_V7
1453 depends on GENERIC_CLOCKEVENTS
1456 select USE_GENERIC_SMP_HELPERS
1458 This enables support for systems with more than one CPU. If you have
1459 a system with only one CPU, like most personal computers, say N. If
1460 you have a system with more than one CPU, say Y.
1462 If you say N here, the kernel will run on single and multiprocessor
1463 machines, but will use only one CPU of a multiprocessor machine. If
1464 you say Y here, the kernel will run on many, but not all, single
1465 processor machines. On a single processor machine, the kernel will
1466 run faster if you say N here.
1468 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1469 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1470 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1472 If you don't know what to do here, say N.
1475 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1476 depends on SMP && !XIP_KERNEL
1479 SMP kernels contain instructions which fail on non-SMP processors.
1480 Enabling this option allows the kernel to modify itself to make
1481 these instructions safe. Disabling it allows about 1K of space
1484 If you don't know what to do here, say Y.
1486 config ARM_CPU_TOPOLOGY
1487 bool "Support cpu topology definition"
1488 depends on SMP && CPU_V7
1491 Support ARM cpu topology definition. The MPIDR register defines
1492 affinity between processors which is then used to describe the cpu
1493 topology of an ARM System.
1496 bool "Multi-core scheduler support"
1497 depends on ARM_CPU_TOPOLOGY
1499 Multi-core scheduler support improves the CPU scheduler's decision
1500 making when dealing with multi-core CPU chips at a cost of slightly
1501 increased overhead in some places. If unsure say N here.
1504 bool "SMT scheduler support"
1505 depends on ARM_CPU_TOPOLOGY
1507 Improves the CPU scheduler's decision making when dealing with
1508 MultiThreading at a cost of slightly increased overhead in some
1509 places. If unsure say N here.
1511 config DISABLE_CPU_SCHED_DOMAIN_BALANCE
1512 bool "(EXPERIMENTAL) Disable CPU level scheduler load-balancing"
1514 Disables scheduler load-balancing at CPU sched domain level.
1517 bool "(EXPERIMENTAL) Heterogenous multiprocessor scheduling"
1518 depends on DISABLE_CPU_SCHED_DOMAIN_BALANCE && SCHED_MC && FAIR_GROUP_SCHED && !SCHED_AUTOGROUP
1520 Experimental scheduler optimizations for heterogeneous platforms.
1521 Attempts to introspectively select task affinity to optimize power
1522 and performance. Basic support for multiple (>2) cpu types is in place,
1523 but it has only been tested with two types of cpus.
1524 There is currently no support for migration of task groups, hence
1525 !SCHED_AUTOGROUP. Furthermore, normal load-balancing must be disabled
1526 between cpus of different type (DISABLE_CPU_SCHED_DOMAIN_BALANCE).
1527 When turned on, this option adds sys/kernel/hmp directory which
1528 contains the following files:
1529 up_threshold - the load average threshold used for up migration
1531 down_threshold - the load average threshold used for down migration
1533 hmp_domains - a list of cpumasks for the present HMP domains,
1534 starting with the 'biggest' and ending with the
1536 Note that both the threshold files can be written at runtime to
1537 control scheduler behaviour.
1539 config SCHED_HMP_PRIO_FILTER
1540 bool "(EXPERIMENTAL) Filter HMP migrations by task priority"
1541 depends on SCHED_HMP
1543 Enables task priority based HMP migration filter. Any task with
1544 a NICE value above the threshold will always be on low-power cpus
1545 with less compute capacity.
1547 config SCHED_HMP_PRIO_FILTER_VAL
1548 int "NICE priority threshold"
1550 depends on SCHED_HMP_PRIO_FILTER
1552 config HMP_FAST_CPU_MASK
1553 string "HMP scheduler fast CPU mask"
1554 depends on SCHED_HMP
1556 Leave empty to use device tree information.
1557 Specify the cpuids of the fast CPUs in the system as a list string,
1558 e.g. cpuid 0+1 should be specified as 0-1.
1560 config HMP_SLOW_CPU_MASK
1561 string "HMP scheduler slow CPU mask"
1562 depends on SCHED_HMP
1564 Leave empty to use device tree information.
1565 Specify the cpuids of the slow CPUs in the system as a list string,
1566 e.g. cpuid 0+1 should be specified as 0-1.
1568 config HMP_VARIABLE_SCALE
1569 bool "Allows changing the load tracking scale through sysfs"
1570 depends on SCHED_HMP
1572 When turned on, this option exports the load average period value
1573 for the load tracking patches through sysfs.
1574 The values can be modified to change the rate of load accumulation
1575 used for HMP migration. 'load_avg_period_ms' is the time in ms to
1576 reach a load average of 0.5 for an idle task of 0 load average
1577 ratio which becomes 100% busy.
1578 For example, with load_avg_period_ms = 128 and up_threshold = 512,
1579 a running task with a load of 0 will be migrated to a bigger CPU after
1580 128ms, because after 128ms its load_avg_ratio is 0.5 and the real
1581 up_threshold is 0.5.
1582 This patch has the same behavior as changing the Y of the load
1583 average computation to
1584 (1002/1024)^(LOAD_AVG_PERIOD/load_avg_period_ms)
1585 but removes intermediate overflows in computation.
1587 config HMP_FREQUENCY_INVARIANT_SCALE
1588 bool "(EXPERIMENTAL) Frequency-Invariant Tracked Load for HMP"
1589 depends on SCHED_HMP && CPU_FREQ
1591 Scales the current load contribution in line with the frequency
1592 of the CPU that the task was executed on.
1593 In this version, we use a simple linear scale derived from the
1594 maximum frequency reported by CPUFreq.
1595 Restricting tracked load to be scaled by the CPU's frequency
1596 represents the consumption of possible compute capacity
1597 (rather than consumption of actual instantaneous capacity as
1598 normal) and allows the HMP migration's simple threshold
1599 migration strategy to interact more predictably with CPUFreq's
1600 asynchronous compute capacity changes.
1602 config SCHED_HMP_LITTLE_PACKING
1603 bool "Small task packing for HMP"
1604 depends on SCHED_HMP
1607 Allows the HMP Scheduler to pack small tasks into CPUs in the
1608 smallest HMP domain.
1609 Controlled by two sysfs files in sys/kernel/hmp.
1610 packing_enable: 1 to enable, 0 to disable packing. Default 1.
1611 packing_limit: runqueue load ratio where a RQ is considered
1612 to be full. Default is NICE_0_LOAD * 9/8.
1617 This option enables support for the ARM system coherency unit
1619 config HAVE_ARM_ARCH_TIMER
1620 bool "Architected timer support"
1622 select ARM_ARCH_TIMER
1624 This option enables support for the ARM architected timer
1629 select CLKSRC_OF if OF
1631 This options enables support for the ARM timer and watchdog unit
1634 bool "Multi-Cluster Power Management"
1635 depends on CPU_V7 && SMP
1637 This option provides the common power management infrastructure
1638 for (multi-)cluster based systems, such as big.LITTLE based
1642 bool "big.LITTLE support (Experimental)"
1643 depends on CPU_V7 && SMP
1646 This option enables support for the big.LITTLE architecture.
1649 bool "big.LITTLE switcher support"
1650 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1652 select ARM_CPU_SUSPEND
1654 The big.LITTLE "switcher" provides the core functionality to
1655 transparently handle transition between a cluster of A15's
1656 and a cluster of A7's in a big.LITTLE system.
1658 config BL_SWITCHER_DUMMY_IF
1659 tristate "Simple big.LITTLE switcher user interface"
1660 depends on BL_SWITCHER && DEBUG_KERNEL
1662 This is a simple and dummy char dev interface to control
1663 the big.LITTLE switcher core code. It is meant for
1664 debugging purposes only.
1667 prompt "Memory split"
1670 Select the desired split between kernel and user memory.
1672 If you are not absolutely sure what you are doing, leave this
1676 bool "3G/1G user/kernel split"
1678 bool "2G/2G user/kernel split"
1680 bool "1G/3G user/kernel split"
1685 default 0x40000000 if VMSPLIT_1G
1686 default 0x80000000 if VMSPLIT_2G
1690 int "Maximum number of CPUs (2-32)"
1696 bool "Support for hot-pluggable CPUs"
1697 depends on SMP && HOTPLUG
1699 Say Y here to experiment with turning CPUs off and on. CPUs
1700 can be controlled through /sys/devices/system/cpu.
1703 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1706 Say Y here if you want Linux to communicate with system firmware
1707 implementing the PSCI specification for CPU-centric power
1708 management operations described in ARM document number ARM DEN
1709 0022A ("Power State Coordination Interface System Software on
1713 bool "Use local timer interrupts"
1717 Enable support for local timers on SMP platforms, rather then the
1718 legacy IPI broadcast method. Local timers allows the system
1719 accounting to be spread across the timer interval, preventing a
1720 "thundering herd" at every timer tick.
1722 # The GPIO number here must be sorted by descending number. In case of
1723 # a multiplatform kernel, we just want the highest value required by the
1724 # selected platforms.
1727 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1728 default 512 if SOC_OMAP5
1729 default 392 if ARCH_U8500
1730 default 352 if ARCH_VT8500
1731 default 288 if ARCH_SUNXI
1732 default 264 if MACH_H4700
1735 Maximum number of GPIOs in the system.
1737 If unsure, leave the default value.
1739 source kernel/Kconfig.preempt
1743 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1744 ARCH_S5PV210 || ARCH_EXYNOS4
1745 default AT91_TIMER_HZ if ARCH_AT91
1746 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1750 def_bool HIGH_RES_TIMERS
1752 config THUMB2_KERNEL
1753 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1754 depends on CPU_V7 && !CPU_V6 && !CPU_V6K
1755 default y if CPU_THUMBONLY
1757 select ARM_ASM_UNIFIED
1760 By enabling this option, the kernel will be compiled in
1761 Thumb-2 mode. A compiler/assembler that understand the unified
1762 ARM-Thumb syntax is needed.
1766 config THUMB2_AVOID_R_ARM_THM_JUMP11
1767 bool "Work around buggy Thumb-2 short branch relocations in gas"
1768 depends on THUMB2_KERNEL && MODULES
1771 Various binutils versions can resolve Thumb-2 branches to
1772 locally-defined, preemptible global symbols as short-range "b.n"
1773 branch instructions.
1775 This is a problem, because there's no guarantee the final
1776 destination of the symbol, or any candidate locations for a
1777 trampoline, are within range of the branch. For this reason, the
1778 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1779 relocation in modules at all, and it makes little sense to add
1782 The symptom is that the kernel fails with an "unsupported
1783 relocation" error when loading some modules.
1785 Until fixed tools are available, passing
1786 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1787 code which hits this problem, at the cost of a bit of extra runtime
1788 stack usage in some cases.
1790 The problem is described in more detail at:
1791 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1793 Only Thumb-2 kernels are affected.
1795 Unless you are sure your tools don't have this problem, say Y.
1797 config ARM_ASM_UNIFIED
1801 bool "Use the ARM EABI to compile the kernel"
1803 This option allows for the kernel to be compiled using the latest
1804 ARM ABI (aka EABI). This is only useful if you are using a user
1805 space environment that is also compiled with EABI.
1807 Since there are major incompatibilities between the legacy ABI and
1808 EABI, especially with regard to structure member alignment, this
1809 option also changes the kernel syscall calling convention to
1810 disambiguate both ABIs and allow for backward compatibility support
1811 (selected with CONFIG_OABI_COMPAT).
1813 To use this you need GCC version 4.0.0 or later.
1816 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1817 depends on AEABI && !THUMB2_KERNEL
1820 This option preserves the old syscall interface along with the
1821 new (ARM EABI) one. It also provides a compatibility layer to
1822 intercept syscalls that have structure arguments which layout
1823 in memory differs between the legacy ABI and the new ARM EABI
1824 (only for non "thumb" binaries). This option adds a tiny
1825 overhead to all syscalls and produces a slightly larger kernel.
1826 If you know you'll be using only pure EABI user space then you
1827 can say N here. If this option is not selected and you attempt
1828 to execute a legacy ABI binary then the result will be
1829 UNPREDICTABLE (in fact it can be predicted that it won't work
1830 at all). If in doubt say Y.
1832 config ARCH_HAS_HOLES_MEMORYMODEL
1835 config ARCH_SPARSEMEM_ENABLE
1838 config ARCH_SPARSEMEM_DEFAULT
1839 def_bool ARCH_SPARSEMEM_ENABLE
1841 config ARCH_SELECT_MEMORY_MODEL
1842 def_bool ARCH_SPARSEMEM_ENABLE
1844 config HAVE_ARCH_PFN_VALID
1845 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1848 bool "High Memory Support"
1851 The address space of ARM processors is only 4 Gigabytes large
1852 and it has to accommodate user address space, kernel address
1853 space as well as some memory mapped IO. That means that, if you
1854 have a large amount of physical memory and/or IO, not all of the
1855 memory can be "permanently mapped" by the kernel. The physical
1856 memory that is not permanently mapped is called "high memory".
1858 Depending on the selected kernel/user memory split, minimum
1859 vmalloc space and actual amount of RAM, you may not need this
1860 option which should result in a slightly faster kernel.
1865 bool "Allocate 2nd-level pagetables from highmem"
1868 config HW_PERF_EVENTS
1869 bool "Enable hardware performance counter support for perf events"
1870 depends on PERF_EVENTS
1873 Enable hardware performance counter support for perf events. If
1874 disabled, perf events will use software events only.
1876 config SYS_SUPPORTS_HUGETLBFS
1880 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1886 config FORCE_MAX_ZONEORDER
1887 int "Maximum zone order" if ARCH_SHMOBILE
1888 range 11 64 if ARCH_SHMOBILE
1889 default "12" if SOC_AM33XX
1890 default "9" if SA1111
1893 The kernel memory allocator divides physically contiguous memory
1894 blocks into "zones", where each zone is a power of two number of
1895 pages. This option selects the largest power of two that the kernel
1896 keeps in the memory allocator. If you need to allocate very large
1897 blocks of physically contiguous memory, then you may need to
1898 increase this value.
1900 This config option is actually maximum order plus one. For example,
1901 a value of 11 means that the largest free memory block is 2^10 pages.
1903 config ALIGNMENT_TRAP
1905 depends on CPU_CP15_MMU
1906 default y if !ARCH_EBSA110
1907 select HAVE_PROC_CPU if PROC_FS
1909 ARM processors cannot fetch/store information which is not
1910 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1911 address divisible by 4. On 32-bit ARM processors, these non-aligned
1912 fetch/store instructions will be emulated in software if you say
1913 here, which has a severe performance impact. This is necessary for
1914 correct operation of some network protocols. With an IP-only
1915 configuration it is safe to say N, otherwise say Y.
1917 config UACCESS_WITH_MEMCPY
1918 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1920 default y if CPU_FEROCEON
1922 Implement faster copy_to_user and clear_user methods for CPU
1923 cores where a 8-word STM instruction give significantly higher
1924 memory write throughput than a sequence of individual 32bit stores.
1926 A possible side effect is a slight increase in scheduling latency
1927 between threads sharing the same address space if they invoke
1928 such copy operations with large buffers.
1930 However, if the CPU data cache is using a write-allocate mode,
1931 this option is unlikely to provide any performance gain.
1935 prompt "Enable seccomp to safely compute untrusted bytecode"
1937 This kernel feature is useful for number crunching applications
1938 that may need to compute untrusted bytecode during their
1939 execution. By using pipes or other transports made available to
1940 the process as file descriptors supporting the read/write
1941 syscalls, it's possible to isolate those applications in
1942 their own address space using seccomp. Once seccomp is
1943 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1944 and the task is only allowed to execute a few safe syscalls
1945 defined by each seccomp mode.
1947 config CC_STACKPROTECTOR
1948 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1950 This option turns on the -fstack-protector GCC feature. This
1951 feature puts, at the beginning of functions, a canary value on
1952 the stack just before the return address, and validates
1953 the value just before actually returning. Stack based buffer
1954 overflows (that need to overwrite this return address) now also
1955 overwrite the canary, which gets detected and the attack is then
1956 neutralized via a kernel panic.
1957 This feature requires gcc version 4.2 or above.
1964 bool "Xen guest support on ARM (EXPERIMENTAL)"
1965 depends on ARM && AEABI && OF
1966 depends on CPU_V7 && !CPU_V6
1967 depends on !GENERIC_ATOMIC64
1970 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1972 config ARM_FLUSH_CONSOLE_ON_RESTART
1973 bool "Force flush the console on restart"
1975 If the console is locked while the system is rebooted, the messages
1976 in the temporary logbuffer would not have propogated to all the
1977 console drivers. This option forces the console lock to be
1978 released if it failed to be acquired, which will cause all the
1979 pending messages to be flushed.
1986 bool "Flattened Device Tree support"
1989 select OF_EARLY_FLATTREE
1991 Include support for flattened device tree machine descriptions.
1994 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1997 This is the traditional way of passing data to the kernel at boot
1998 time. If you are solely relying on the flattened device tree (or
1999 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
2000 to remove ATAGS support from your kernel binary. If unsure,
2003 config DEPRECATED_PARAM_STRUCT
2004 bool "Provide old way to pass kernel parameters"
2007 This was deprecated in 2001 and announced to live on for 5 years.
2008 Some old boot loaders still use this way.
2010 config BUILD_ARM_APPENDED_DTB_IMAGE
2011 bool "Build a concatenated zImage/dtb by default"
2014 Enabling this option will cause a concatenated zImage and DTB to
2015 be built by default (instead of a standalone zImage.) The image
2016 will built in arch/arm/boot/zImage-dtb.<dtb name>
2018 config BUILD_ARM_APPENDED_DTB_IMAGE_NAME
2019 string "Default dtb name"
2020 depends on BUILD_ARM_APPENDED_DTB_IMAGE
2022 name of the dtb to append when building a concatenated
2025 # Compressed boot loader in ROM. Yes, we really want to ask about
2026 # TEXT and BSS so we preserve their values in the config files.
2027 config ZBOOT_ROM_TEXT
2028 hex "Compressed ROM boot loader base address"
2031 The physical address at which the ROM-able zImage is to be
2032 placed in the target. Platforms which normally make use of
2033 ROM-able zImage formats normally set this to a suitable
2034 value in their defconfig file.
2036 If ZBOOT_ROM is not enabled, this has no effect.
2038 config ZBOOT_ROM_BSS
2039 hex "Compressed ROM boot loader BSS address"
2042 The base address of an area of read/write memory in the target
2043 for the ROM-able zImage which must be available while the
2044 decompressor is running. It must be large enough to hold the
2045 entire decompressed kernel plus an additional 128 KiB.
2046 Platforms which normally make use of ROM-able zImage formats
2047 normally set this to a suitable value in their defconfig file.
2049 If ZBOOT_ROM is not enabled, this has no effect.
2052 bool "Compressed boot loader in ROM/flash"
2053 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
2055 Say Y here if you intend to execute your compressed kernel image
2056 (zImage) directly from ROM or flash. If unsure, say N.
2059 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
2060 depends on ZBOOT_ROM && ARCH_SH7372
2061 default ZBOOT_ROM_NONE
2063 Include experimental SD/MMC loading code in the ROM-able zImage.
2064 With this enabled it is possible to write the ROM-able zImage
2065 kernel image to an MMC or SD card and boot the kernel straight
2066 from the reset vector. At reset the processor Mask ROM will load
2067 the first part of the ROM-able zImage which in turn loads the
2068 rest the kernel image to RAM.
2070 config ZBOOT_ROM_NONE
2071 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
2073 Do not load image from SD or MMC
2075 config ZBOOT_ROM_MMCIF
2076 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
2078 Load image from MMCIF hardware block.
2080 config ZBOOT_ROM_SH_MOBILE_SDHI
2081 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
2083 Load image from SDHI hardware block
2087 config ARM_APPENDED_DTB
2088 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
2089 depends on OF && !ZBOOT_ROM
2091 With this option, the boot code will look for a device tree binary
2092 (DTB) appended to zImage
2093 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
2095 This is meant as a backward compatibility convenience for those
2096 systems with a bootloader that can't be upgraded to accommodate
2097 the documented boot protocol using a device tree.
2099 Beware that there is very little in terms of protection against
2100 this option being confused by leftover garbage in memory that might
2101 look like a DTB header after a reboot if no actual DTB is appended
2102 to zImage. Do not leave this option active in a production kernel
2103 if you don't intend to always append a DTB. Proper passing of the
2104 location into r2 of a bootloader provided DTB is always preferable
2107 config ARM_ATAG_DTB_COMPAT
2108 bool "Supplement the appended DTB with traditional ATAG information"
2109 depends on ARM_APPENDED_DTB
2111 Some old bootloaders can't be updated to a DTB capable one, yet
2112 they provide ATAGs with memory configuration, the ramdisk address,
2113 the kernel cmdline string, etc. Such information is dynamically
2114 provided by the bootloader and can't always be stored in a static
2115 DTB. To allow a device tree enabled kernel to be used with such
2116 bootloaders, this option allows zImage to extract the information
2117 from the ATAG list and store it at run time into the appended DTB.
2120 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2121 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2123 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2124 bool "Use bootloader kernel arguments if available"
2126 Uses the command-line options passed by the boot loader instead of
2127 the device tree bootargs property. If the boot loader doesn't provide
2128 any, the device tree bootargs property will be used.
2130 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2131 bool "Extend with bootloader kernel arguments"
2133 The command-line arguments provided by the boot loader will be
2134 appended to the the device tree bootargs property.
2139 string "Default kernel command string"
2142 On some architectures (EBSA110 and CATS), there is currently no way
2143 for the boot loader to pass arguments to the kernel. For these
2144 architectures, you should supply some command-line options at build
2145 time by entering them here. As a minimum, you should specify the
2146 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2149 prompt "Kernel command line type" if CMDLINE != ""
2150 default CMDLINE_FROM_BOOTLOADER
2153 config CMDLINE_FROM_BOOTLOADER
2154 bool "Use bootloader kernel arguments if available"
2156 Uses the command-line options passed by the boot loader. If
2157 the boot loader doesn't provide any, the default kernel command
2158 string provided in CMDLINE will be used.
2160 config CMDLINE_EXTEND
2161 bool "Extend bootloader kernel arguments"
2163 The command-line arguments provided by the boot loader will be
2164 appended to the default kernel command string.
2166 config CMDLINE_FORCE
2167 bool "Always use the default kernel command string"
2169 Always use the default kernel command string, even if the boot
2170 loader passes other arguments to the kernel.
2171 This is useful if you cannot or don't want to change the
2172 command-line options your boot loader passes to the kernel.
2176 bool "Kernel Execute-In-Place from ROM"
2177 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2179 Execute-In-Place allows the kernel to run from non-volatile storage
2180 directly addressable by the CPU, such as NOR flash. This saves RAM
2181 space since the text section of the kernel is not loaded from flash
2182 to RAM. Read-write sections, such as the data section and stack,
2183 are still copied to RAM. The XIP kernel is not compressed since
2184 it has to run directly from flash, so it will take more space to
2185 store it. The flash address used to link the kernel object files,
2186 and for storing it, is configuration dependent. Therefore, if you
2187 say Y here, you must know the proper physical address where to
2188 store the kernel image depending on your own flash memory usage.
2190 Also note that the make target becomes "make xipImage" rather than
2191 "make zImage" or "make Image". The final kernel binary to put in
2192 ROM memory will be arch/arm/boot/xipImage.
2196 config XIP_PHYS_ADDR
2197 hex "XIP Kernel Physical Location"
2198 depends on XIP_KERNEL
2199 default "0x00080000"
2201 This is the physical address in your flash memory the kernel will
2202 be linked for and stored to. This address is dependent on your
2206 bool "Kexec system call (EXPERIMENTAL)"
2207 depends on (!SMP || PM_SLEEP_SMP)
2209 kexec is a system call that implements the ability to shutdown your
2210 current kernel, and to start another kernel. It is like a reboot
2211 but it is independent of the system firmware. And like a reboot
2212 you can start any kernel with it, not just Linux.
2214 It is an ongoing process to be certain the hardware in a machine
2215 is properly shutdown, so do not be surprised if this code does not
2216 initially work for you. It may help to enable device hotplugging
2220 bool "Export atags in procfs"
2221 depends on ATAGS && KEXEC
2224 Should the atags used to boot the kernel be exported in an "atags"
2225 file in procfs. Useful with kexec.
2228 bool "Build kdump crash kernel (EXPERIMENTAL)"
2230 Generate crash dump after being started by kexec. This should
2231 be normally only set in special crash dump kernels which are
2232 loaded in the main kernel with kexec-tools into a specially
2233 reserved region and then later executed after a crash by
2234 kdump/kexec. The crash dump kernel must be compiled to a
2235 memory address not used by the main kernel
2237 For more details see Documentation/kdump/kdump.txt
2239 config AUTO_ZRELADDR
2240 bool "Auto calculation of the decompressed kernel image address"
2241 depends on !ZBOOT_ROM && !ARCH_U300
2243 ZRELADDR is the physical address where the decompressed kernel
2244 image will be placed. If AUTO_ZRELADDR is selected, the address
2245 will be determined at run-time by masking the current IP with
2246 0xf8000000. This assumes the zImage being placed in the first 128MB
2247 from start of memory.
2251 menu "CPU Power Management"
2254 source "drivers/cpufreq/Kconfig"
2259 Internal configuration node for common cpufreq on Samsung SoC
2261 config CPU_FREQ_S3C24XX
2262 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2263 depends on ARCH_S3C24XX && CPU_FREQ
2266 This enables the CPUfreq driver for the Samsung S3C24XX family
2269 For details, take a look at <file:Documentation/cpu-freq>.
2273 config CPU_FREQ_S3C24XX_PLL
2274 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2275 depends on CPU_FREQ_S3C24XX
2277 Compile in support for changing the PLL frequency from the
2278 S3C24XX series CPUfreq driver. The PLL takes time to settle
2279 after a frequency change, so by default it is not enabled.
2281 This also means that the PLL tables for the selected CPU(s) will
2282 be built which may increase the size of the kernel image.
2284 config CPU_FREQ_S3C24XX_DEBUG
2285 bool "Debug CPUfreq Samsung driver core"
2286 depends on CPU_FREQ_S3C24XX
2288 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2290 config CPU_FREQ_S3C24XX_IODEBUG
2291 bool "Debug CPUfreq Samsung driver IO timing"
2292 depends on CPU_FREQ_S3C24XX
2294 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2296 config CPU_FREQ_S3C24XX_DEBUGFS
2297 bool "Export debugfs for CPUFreq"
2298 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2300 Export status information via debugfs.
2304 source "drivers/cpuidle/Kconfig"
2308 menu "Floating point emulation"
2310 comment "At least one emulation must be selected"
2313 bool "NWFPE math emulation"
2314 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2316 Say Y to include the NWFPE floating point emulator in the kernel.
2317 This is necessary to run most binaries. Linux does not currently
2318 support floating point hardware so you need to say Y here even if
2319 your machine has an FPA or floating point co-processor podule.
2321 You may say N here if you are going to load the Acorn FPEmulator
2322 early in the bootup.
2325 bool "Support extended precision"
2326 depends on FPE_NWFPE
2328 Say Y to include 80-bit support in the kernel floating-point
2329 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2330 Note that gcc does not generate 80-bit operations by default,
2331 so in most cases this option only enlarges the size of the
2332 floating point emulator without any good reason.
2334 You almost surely want to say N here.
2337 bool "FastFPE math emulation (EXPERIMENTAL)"
2338 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2340 Say Y here to include the FAST floating point emulator in the kernel.
2341 This is an experimental much faster emulator which now also has full
2342 precision for the mantissa. It does not support any exceptions.
2343 It is very simple, and approximately 3-6 times faster than NWFPE.
2345 It should be sufficient for most programs. It may be not suitable
2346 for scientific calculations, but you have to check this for yourself.
2347 If you do not feel you need a faster FP emulation you should better
2351 bool "VFP-format floating point maths"
2352 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2354 Say Y to include VFP support code in the kernel. This is needed
2355 if your hardware includes a VFP unit.
2357 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2358 release notes and additional status information.
2360 Say N if your target does not have VFP hardware.
2368 bool "Advanced SIMD (NEON) Extension support"
2369 depends on VFPv3 && CPU_V7
2371 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2376 menu "Userspace binary formats"
2378 source "fs/Kconfig.binfmt"
2381 tristate "RISC OS personality"
2384 Say Y here to include the kernel code necessary if you want to run
2385 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2386 experimental; if this sounds frightening, say N and sleep in peace.
2387 You can also say M here to compile this support as a module (which
2388 will be called arthur).
2392 menu "Power management options"
2394 source "kernel/power/Kconfig"
2396 config ARCH_SUSPEND_POSSIBLE
2397 depends on !ARCH_S5PC100
2398 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2399 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2402 config ARM_CPU_SUSPEND
2407 source "net/Kconfig"
2409 source "drivers/Kconfig"
2413 source "arch/arm/Kconfig.debug"
2415 source "security/Kconfig"
2417 source "crypto/Kconfig"
2419 source "lib/Kconfig"
2421 source "arch/arm/kvm/Kconfig"