4 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
5 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
6 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
7 select ARCH_HAVE_CUSTOM_GPIO_H
8 select ARCH_MIGHT_HAVE_PC_PARPORT
9 select ARCH_USE_BUILTIN_BSWAP
10 select ARCH_USE_CMPXCHG_LOCKREF
11 select ARCH_WANT_IPC_PARSE_VERSION
12 select BUILDTIME_EXTABLE_SORT if MMU
13 select CLONE_BACKWARDS
14 select CPU_PM if (SUSPEND || CPU_IDLE)
15 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
16 select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
17 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
18 select GENERIC_IDLE_POLL_SETUP
19 select GENERIC_IRQ_PROBE
20 select GENERIC_IRQ_SHOW
21 select GENERIC_PCI_IOMAP
22 select GENERIC_SCHED_CLOCK
23 select GENERIC_SMP_IDLE_THREAD
24 select GENERIC_STRNCPY_FROM_USER
25 select GENERIC_STRNLEN_USER
26 select HARDIRQS_SW_RESEND
27 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
29 select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
30 select HAVE_ARCH_TRACEHOOK
32 select HAVE_CONTEXT_TRACKING
33 select HAVE_C_RECORDMCOUNT
34 select HAVE_DEBUG_KMEMLEAK
35 select HAVE_DMA_API_DEBUG
37 select HAVE_DMA_CONTIGUOUS if MMU
38 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
39 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
40 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
41 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
42 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
43 select HAVE_GENERIC_DMA_COHERENT
44 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
45 select HAVE_IDE if PCI || ISA || PCMCIA
46 select HAVE_IRQ_TIME_ACCOUNTING
47 select HAVE_KERNEL_GZIP
48 select HAVE_KERNEL_LZ4
49 select HAVE_KERNEL_LZMA
50 select HAVE_KERNEL_LZO
52 select HAVE_KPROBES if !XIP_KERNEL
53 select HAVE_KRETPROBES if (HAVE_KPROBES)
55 select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
56 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
57 select HAVE_PERF_EVENTS
59 select HAVE_PERF_USER_STACK_DUMP
60 select HAVE_REGS_AND_STACK_ACCESS_API
61 select HAVE_SYSCALL_TRACEPOINTS
63 select HAVE_VIRT_CPU_ACCOUNTING_GEN
64 select IRQ_FORCED_THREADING
66 select MODULES_USE_ELF_REL
68 select OLD_SIGSUSPEND3
69 select PERF_USE_VMALLOC
71 select SYS_SUPPORTS_APM_EMULATION
72 # Above selects are sorted alphabetically; please add new ones
73 # according to that. Thanks.
75 The ARM series is a line of low-power-consumption RISC chip designs
76 licensed by ARM Ltd and targeted at embedded applications and
77 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
78 manufactured, but legacy ARM-based PC hardware remains popular in
79 Europe. There is an ARM Linux project with a web page at
80 <http://www.arm.linux.org.uk/>.
82 config ARM_HAS_SG_CHAIN
85 config NEED_SG_DMA_LENGTH
88 config ARM_DMA_USE_IOMMU
90 select ARM_HAS_SG_CHAIN
91 select NEED_SG_DMA_LENGTH
95 config ARM_DMA_IOMMU_ALIGNMENT
96 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
100 DMA mapping framework by default aligns all buffers to the smallest
101 PAGE_SIZE order which is greater than or equal to the requested buffer
102 size. This works well for buffers up to a few hundreds kilobytes, but
103 for larger buffers it just a waste of address space. Drivers which has
104 relatively small addressing window (like 64Mib) might run out of
105 virtual space with just a few allocations.
107 With this parameter you can specify the maximum PAGE_SIZE order for
108 DMA IOMMU buffers. Larger buffers will be aligned only to this
109 specified order. The order is expressed as a power of two multiplied
117 config MIGHT_HAVE_PCI
120 config SYS_SUPPORTS_APM_EMULATION
125 select GENERIC_ALLOCATOR
136 The Extended Industry Standard Architecture (EISA) bus was
137 developed as an open alternative to the IBM MicroChannel bus.
139 The EISA bus provided some of the features of the IBM MicroChannel
140 bus while maintaining backward compatibility with cards made for
141 the older ISA bus. The EISA bus saw limited use between 1988 and
142 1995 when it was made obsolete by the PCI bus.
144 Say Y here if you are building a kernel for an EISA-based machine.
151 config STACKTRACE_SUPPORT
155 config HAVE_LATENCYTOP_SUPPORT
160 config LOCKDEP_SUPPORT
164 config TRACE_IRQFLAGS_SUPPORT
168 config RWSEM_GENERIC_SPINLOCK
172 config RWSEM_XCHGADD_ALGORITHM
175 config ARCH_HAS_ILOG2_U32
178 config ARCH_HAS_ILOG2_U64
181 config ARCH_HAS_CPUFREQ
184 Internal node to signify that the ARCH has CPUFREQ support
185 and that the relevant menu configurations are displayed for
188 config ARCH_HAS_BANDGAP
191 config GENERIC_HWEIGHT
195 config GENERIC_CALIBRATE_DELAY
199 config ARCH_MAY_HAVE_PC_FDC
205 config NEED_DMA_MAP_STATE
208 config ARCH_HAS_DMA_SET_COHERENT_MASK
211 config GENERIC_ISA_DMA
217 config NEED_RET_TO_USER
225 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
226 default DRAM_BASE if REMAP_VECTORS_TO_RAM
229 The base address of exception vectors. This must be two pages
232 config ARM_PATCH_PHYS_VIRT
233 bool "Patch physical to virtual translations at runtime" if EMBEDDED
235 depends on !XIP_KERNEL && MMU
236 depends on !ARCH_REALVIEW || !SPARSEMEM
238 Patch phys-to-virt and virt-to-phys translation functions at
239 boot and module load time according to the position of the
240 kernel in system memory.
242 This can only be used with non-XIP MMU kernels where the base
243 of physical memory is at a 16MB boundary.
245 Only disable this option if you know that you do not require
246 this feature (eg, building a kernel for a single machine) and
247 you need to shrink the kernel to the minimal size.
249 config NEED_MACH_GPIO_H
252 Select this when mach/gpio.h is required to provide special
253 definitions for this platform. The need for mach/gpio.h should
254 be avoided when possible.
256 config NEED_MACH_IO_H
259 Select this when mach/io.h is required to provide special
260 definitions for this platform. The need for mach/io.h should
261 be avoided when possible.
263 config NEED_MACH_MEMORY_H
266 Select this when mach/memory.h is required to provide special
267 definitions for this platform. The need for mach/memory.h should
268 be avoided when possible.
271 hex "Physical address of main memory" if MMU
272 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
273 default DRAM_BASE if !MMU
275 Please provide the physical address corresponding to the
276 location of main memory in your system.
282 source "init/Kconfig"
284 source "kernel/Kconfig.freezer"
289 bool "MMU-based Paged Memory Management Support"
292 Select if you want MMU-based virtualised addressing space
293 support by paged memory management. If unsure, say 'Y'.
296 # The "ARM system type" choice list is ordered alphabetically by option
297 # text. Please add new entries in the option alphabetic order.
300 prompt "ARM system type"
301 default ARCH_VERSATILE if !MMU
302 default ARCH_MULTIPLATFORM if MMU
304 config ARCH_MULTIPLATFORM
305 bool "Allow multiple platforms to be selected"
307 select ARM_PATCH_PHYS_VIRT
310 select MULTI_IRQ_HANDLER
314 config ARCH_INTEGRATOR
315 bool "ARM Ltd. Integrator family"
316 select ARCH_HAS_CPUFREQ
319 select COMMON_CLK_VERSATILE
320 select GENERIC_CLOCKEVENTS
323 select MULTI_IRQ_HANDLER
324 select NEED_MACH_MEMORY_H
325 select PLAT_VERSATILE
328 select VERSATILE_FPGA_IRQ
330 Support for ARM's Integrator platform.
333 bool "ARM Ltd. RealView family"
334 select ARCH_WANT_OPTIONAL_GPIOLIB
336 select ARM_TIMER_SP804
338 select COMMON_CLK_VERSATILE
339 select GENERIC_CLOCKEVENTS
340 select GPIO_PL061 if GPIOLIB
342 select NEED_MACH_MEMORY_H
343 select PLAT_VERSATILE
344 select PLAT_VERSATILE_CLCD
346 This enables support for ARM Ltd RealView boards.
348 config ARCH_VERSATILE
349 bool "ARM Ltd. Versatile family"
350 select ARCH_WANT_OPTIONAL_GPIOLIB
352 select ARM_TIMER_SP804
355 select GENERIC_CLOCKEVENTS
356 select HAVE_MACH_CLKDEV
358 select PLAT_VERSATILE
359 select PLAT_VERSATILE_CLCD
360 select PLAT_VERSATILE_CLOCK
361 select VERSATILE_FPGA_IRQ
363 This enables support for ARM Ltd Versatile board.
367 select ARCH_REQUIRE_GPIOLIB
370 select NEED_MACH_GPIO_H
371 select NEED_MACH_IO_H if PCCARD
373 select PINCTRL_AT91 if USE_OF
375 This enables support for systems based on Atmel
376 AT91RM9200 and AT91SAM9* processors.
379 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
380 select ARCH_REQUIRE_GPIOLIB
385 select GENERIC_CLOCKEVENTS
387 select MULTI_IRQ_HANDLER
390 Support for Cirrus Logic 711x/721x/731x based boards.
393 bool "Cortina Systems Gemini"
394 select ARCH_REQUIRE_GPIOLIB
397 select GENERIC_CLOCKEVENTS
399 Support for the Cortina Systems Gemini family SoCs
403 select ARCH_USES_GETTIMEOFFSET
406 select NEED_MACH_IO_H
407 select NEED_MACH_MEMORY_H
410 This is an evaluation board for the StrongARM processor available
411 from Digital. It has limited hardware on-board, including an
412 Ethernet interface, two PCMCIA sockets, two serial ports and a
417 select ARCH_HAS_HOLES_MEMORYMODEL
418 select ARCH_REQUIRE_GPIOLIB
419 select ARCH_USES_GETTIMEOFFSET
424 select NEED_MACH_MEMORY_H
426 This enables support for the Cirrus EP93xx series of CPUs.
428 config ARCH_FOOTBRIDGE
432 select GENERIC_CLOCKEVENTS
434 select NEED_MACH_IO_H if !MMU
435 select NEED_MACH_MEMORY_H
437 Support for systems based on the DC21285 companion chip
438 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
441 bool "Hilscher NetX based"
445 select GENERIC_CLOCKEVENTS
447 This enables support for systems based on the Hilscher NetX Soc
453 select NEED_MACH_MEMORY_H
454 select NEED_RET_TO_USER
459 Support for Intel's IOP13XX (XScale) family of processors.
464 select ARCH_REQUIRE_GPIOLIB
467 select NEED_RET_TO_USER
471 Support for Intel's 80219 and IOP32X (XScale) family of
477 select ARCH_REQUIRE_GPIOLIB
480 select NEED_RET_TO_USER
484 Support for Intel's IOP33X (XScale) family of processors.
489 select ARCH_HAS_DMA_SET_COHERENT_MASK
490 select ARCH_SUPPORTS_BIG_ENDIAN
491 select ARCH_REQUIRE_GPIOLIB
494 select DMABOUNCE if PCI
495 select GENERIC_CLOCKEVENTS
496 select MIGHT_HAVE_PCI
497 select NEED_MACH_IO_H
498 select USB_EHCI_BIG_ENDIAN_DESC
499 select USB_EHCI_BIG_ENDIAN_MMIO
501 Support for Intel's IXP4XX (XScale) family of processors.
505 select ARCH_REQUIRE_GPIOLIB
507 select GENERIC_CLOCKEVENTS
508 select MIGHT_HAVE_PCI
512 select PLAT_ORION_LEGACY
513 select USB_ARCH_HAS_EHCI
515 Support for the Marvell Dove SoC 88AP510
518 bool "Marvell Kirkwood"
519 select ARCH_HAS_CPUFREQ
520 select ARCH_REQUIRE_GPIOLIB
522 select GENERIC_CLOCKEVENTS
527 select PINCTRL_KIRKWOOD
528 select PLAT_ORION_LEGACY
530 Support for the following Marvell Kirkwood series SoCs:
531 88F6180, 88F6192 and 88F6281.
534 bool "Marvell MV78xx0"
535 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
540 select PLAT_ORION_LEGACY
542 Support for the following Marvell MV78xx0 series SoCs:
548 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
553 select PLAT_ORION_LEGACY
555 Support for the following Marvell Orion 5x series SoCs:
556 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
557 Orion-2 (5281), Orion-1-90 (6183).
560 bool "Marvell PXA168/910/MMP2"
562 select ARCH_REQUIRE_GPIOLIB
564 select GENERIC_ALLOCATOR
565 select GENERIC_CLOCKEVENTS
568 select MULTI_IRQ_HANDLER
573 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
576 bool "Micrel/Kendin KS8695"
577 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
581 select NEED_MACH_MEMORY_H
583 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
584 System-on-Chip devices.
587 bool "Nuvoton W90X900 CPU"
588 select ARCH_REQUIRE_GPIOLIB
592 select GENERIC_CLOCKEVENTS
594 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
595 At present, the w90x900 has been renamed nuc900, regarding
596 the ARM series product line, you can login the following
597 link address to know more.
599 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
600 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
604 select ARCH_REQUIRE_GPIOLIB
609 select GENERIC_CLOCKEVENTS
612 select USB_ARCH_HAS_OHCI
615 Support for the NXP LPC32XX family of processors
618 bool "PXA2xx/PXA3xx-based"
620 select ARCH_HAS_CPUFREQ
622 select ARCH_REQUIRE_GPIOLIB
623 select ARM_CPU_SUSPEND if PM
627 select GENERIC_CLOCKEVENTS
630 select MULTI_IRQ_HANDLER
634 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
638 select ARCH_REQUIRE_GPIOLIB
639 select CLKSRC_OF if OF
641 select GENERIC_CLOCKEVENTS
643 Support for Qualcomm MSM/QSD based systems. This runs on the
644 apps processor of the MSM/QSD and depends on a shared memory
645 interface to the modem processor which runs the baseband
646 stack and controls some vital subsystems
647 (clock and power control, etc).
650 bool "Renesas SH-Mobile / R-Mobile"
651 select ARM_PATCH_PHYS_VIRT
653 select GENERIC_CLOCKEVENTS
654 select HAVE_ARM_SCU if SMP
655 select HAVE_ARM_TWD if SMP
656 select HAVE_MACH_CLKDEV
658 select MIGHT_HAVE_CACHE_L2X0
659 select MULTI_IRQ_HANDLER
662 select PM_GENERIC_DOMAINS if PM
665 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
670 select ARCH_MAY_HAVE_PC_FDC
671 select ARCH_SPARSEMEM_ENABLE
672 select ARCH_USES_GETTIMEOFFSET
675 select HAVE_PATA_PLATFORM
677 select NEED_MACH_IO_H
678 select NEED_MACH_MEMORY_H
682 On the Acorn Risc-PC, Linux can support the internal IDE disk and
683 CD-ROM interface, serial and parallel port, and the floppy drive.
687 select ARCH_HAS_CPUFREQ
689 select ARCH_REQUIRE_GPIOLIB
690 select ARCH_SPARSEMEM_ENABLE
695 select GENERIC_CLOCKEVENTS
698 select NEED_MACH_MEMORY_H
701 Support for StrongARM 11x0 based boards.
704 bool "Samsung S3C24XX SoCs"
705 select ARCH_HAS_CPUFREQ
706 select ARCH_REQUIRE_GPIOLIB
708 select CLKSRC_SAMSUNG_PWM
709 select GENERIC_CLOCKEVENTS
711 select HAVE_S3C2410_I2C if I2C
712 select HAVE_S3C2410_WATCHDOG if WATCHDOG
713 select HAVE_S3C_RTC if RTC_CLASS
714 select MULTI_IRQ_HANDLER
715 select NEED_MACH_GPIO_H
716 select NEED_MACH_IO_H
719 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
720 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
721 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
722 Samsung SMDK2410 development board (and derivatives).
725 bool "Samsung S3C64XX"
726 select ARCH_HAS_CPUFREQ
727 select ARCH_REQUIRE_GPIOLIB
730 select CLKSRC_SAMSUNG_PWM
733 select GENERIC_CLOCKEVENTS
735 select HAVE_S3C2410_I2C if I2C
736 select HAVE_S3C2410_WATCHDOG if WATCHDOG
738 select NEED_MACH_GPIO_H
741 select PM_GENERIC_DOMAINS
743 select S3C_GPIO_TRACK
745 select SAMSUNG_GPIOLIB_4BIT
746 select SAMSUNG_WAKEMASK
747 select SAMSUNG_WDT_RESET
748 select USB_ARCH_HAS_OHCI
750 Samsung S3C64XX series based systems
753 bool "Samsung S5P6440 S5P6450"
755 select CLKSRC_SAMSUNG_PWM
757 select GENERIC_CLOCKEVENTS
759 select HAVE_S3C2410_I2C if I2C
760 select HAVE_S3C2410_WATCHDOG if WATCHDOG
761 select HAVE_S3C_RTC if RTC_CLASS
762 select NEED_MACH_GPIO_H
764 select SAMSUNG_WDT_RESET
766 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
770 bool "Samsung S5PC100"
771 select ARCH_REQUIRE_GPIOLIB
773 select CLKSRC_SAMSUNG_PWM
775 select GENERIC_CLOCKEVENTS
777 select HAVE_S3C2410_I2C if I2C
778 select HAVE_S3C2410_WATCHDOG if WATCHDOG
779 select HAVE_S3C_RTC if RTC_CLASS
780 select NEED_MACH_GPIO_H
782 select SAMSUNG_WDT_RESET
784 Samsung S5PC100 series based systems
787 bool "Samsung S5PV210/S5PC110"
788 select ARCH_HAS_CPUFREQ
789 select ARCH_HAS_HOLES_MEMORYMODEL
790 select ARCH_SPARSEMEM_ENABLE
792 select CLKSRC_SAMSUNG_PWM
794 select GENERIC_CLOCKEVENTS
796 select HAVE_S3C2410_I2C if I2C
797 select HAVE_S3C2410_WATCHDOG if WATCHDOG
798 select HAVE_S3C_RTC if RTC_CLASS
799 select NEED_MACH_GPIO_H
800 select NEED_MACH_MEMORY_H
803 Samsung S5PV210/S5PC110 series based systems
806 bool "Samsung EXYNOS"
807 select ARCH_HAS_CPUFREQ
808 select ARCH_HAS_HOLES_MEMORYMODEL
809 select ARCH_REQUIRE_GPIOLIB
810 select ARCH_SPARSEMEM_ENABLE
814 select GENERIC_CLOCKEVENTS
815 select HAVE_S3C2410_I2C if I2C
816 select HAVE_S3C2410_WATCHDOG if WATCHDOG
817 select HAVE_S3C_RTC if RTC_CLASS
818 select NEED_MACH_MEMORY_H
822 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
826 select ARCH_HAS_HOLES_MEMORYMODEL
827 select ARCH_REQUIRE_GPIOLIB
829 select GENERIC_ALLOCATOR
830 select GENERIC_CLOCKEVENTS
831 select GENERIC_IRQ_CHIP
837 Support for TI's DaVinci platform.
842 select ARCH_HAS_CPUFREQ
843 select ARCH_HAS_HOLES_MEMORYMODEL
845 select ARCH_REQUIRE_GPIOLIB
848 select GENERIC_CLOCKEVENTS
849 select GENERIC_IRQ_CHIP
852 select NEED_MACH_IO_H if PCCARD
853 select NEED_MACH_MEMORY_H
855 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
859 menu "Multiple platform selection"
860 depends on ARCH_MULTIPLATFORM
862 comment "CPU Core family selection"
864 config ARCH_MULTI_V4T
865 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
866 depends on !ARCH_MULTI_V6_V7
867 select ARCH_MULTI_V4_V5
868 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
869 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
870 CPU_ARM925T || CPU_ARM940T)
873 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
874 depends on !ARCH_MULTI_V6_V7
875 select ARCH_MULTI_V4_V5
876 select CPU_ARM926T if (!CPU_ARM946E || CPU_ARM1020 || \
877 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
878 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
880 config ARCH_MULTI_V4_V5
884 bool "ARMv6 based platforms (ARM11)"
885 select ARCH_MULTI_V6_V7
889 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
891 select ARCH_MULTI_V6_V7
894 config ARCH_MULTI_V6_V7
897 config ARCH_MULTI_CPU_AUTO
898 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
904 # This is sorted alphabetically by mach-* pathname. However, plat-*
905 # Kconfigs may be included either alphabetically (according to the
906 # plat- suffix) or along side the corresponding mach-* source.
908 source "arch/arm/mach-mvebu/Kconfig"
910 source "arch/arm/mach-at91/Kconfig"
912 source "arch/arm/mach-bcm/Kconfig"
914 source "arch/arm/mach-bcm2835/Kconfig"
916 source "arch/arm/mach-clps711x/Kconfig"
918 source "arch/arm/mach-cns3xxx/Kconfig"
920 source "arch/arm/mach-davinci/Kconfig"
922 source "arch/arm/mach-dove/Kconfig"
924 source "arch/arm/mach-ep93xx/Kconfig"
926 source "arch/arm/mach-footbridge/Kconfig"
928 source "arch/arm/mach-gemini/Kconfig"
930 source "arch/arm/mach-highbank/Kconfig"
932 source "arch/arm/mach-integrator/Kconfig"
934 source "arch/arm/mach-iop32x/Kconfig"
936 source "arch/arm/mach-iop33x/Kconfig"
938 source "arch/arm/mach-iop13xx/Kconfig"
940 source "arch/arm/mach-ixp4xx/Kconfig"
942 source "arch/arm/mach-keystone/Kconfig"
944 source "arch/arm/mach-kirkwood/Kconfig"
946 source "arch/arm/mach-ks8695/Kconfig"
948 source "arch/arm/mach-msm/Kconfig"
950 source "arch/arm/mach-mv78xx0/Kconfig"
952 source "arch/arm/mach-imx/Kconfig"
954 source "arch/arm/mach-mxs/Kconfig"
956 source "arch/arm/mach-netx/Kconfig"
958 source "arch/arm/mach-nomadik/Kconfig"
960 source "arch/arm/mach-nspire/Kconfig"
962 source "arch/arm/plat-omap/Kconfig"
964 source "arch/arm/mach-omap1/Kconfig"
966 source "arch/arm/mach-omap2/Kconfig"
968 source "arch/arm/mach-orion5x/Kconfig"
970 source "arch/arm/mach-picoxcell/Kconfig"
972 source "arch/arm/mach-pxa/Kconfig"
973 source "arch/arm/plat-pxa/Kconfig"
975 source "arch/arm/mach-mmp/Kconfig"
977 source "arch/arm/mach-realview/Kconfig"
979 source "arch/arm/mach-rockchip/Kconfig"
981 source "arch/arm/mach-sa1100/Kconfig"
983 source "arch/arm/plat-samsung/Kconfig"
985 source "arch/arm/mach-socfpga/Kconfig"
987 source "arch/arm/mach-spear/Kconfig"
989 source "arch/arm/mach-sti/Kconfig"
991 source "arch/arm/mach-s3c24xx/Kconfig"
993 source "arch/arm/mach-s3c64xx/Kconfig"
995 source "arch/arm/mach-s5p64x0/Kconfig"
997 source "arch/arm/mach-s5pc100/Kconfig"
999 source "arch/arm/mach-s5pv210/Kconfig"
1001 source "arch/arm/mach-exynos/Kconfig"
1003 source "arch/arm/mach-shmobile/Kconfig"
1005 source "arch/arm/mach-sunxi/Kconfig"
1007 source "arch/arm/mach-prima2/Kconfig"
1009 source "arch/arm/mach-tegra/Kconfig"
1011 source "arch/arm/mach-u300/Kconfig"
1013 source "arch/arm/mach-ux500/Kconfig"
1015 source "arch/arm/mach-versatile/Kconfig"
1017 source "arch/arm/mach-vexpress/Kconfig"
1018 source "arch/arm/plat-versatile/Kconfig"
1020 source "arch/arm/mach-virt/Kconfig"
1022 source "arch/arm/mach-vt8500/Kconfig"
1024 source "arch/arm/mach-w90x900/Kconfig"
1026 source "arch/arm/mach-zynq/Kconfig"
1028 # Definitions to make life easier
1034 select GENERIC_CLOCKEVENTS
1040 select GENERIC_IRQ_CHIP
1043 config PLAT_ORION_LEGACY
1050 config PLAT_VERSATILE
1053 config ARM_TIMER_SP804
1056 select CLKSRC_OF if OF
1058 source arch/arm/mm/Kconfig
1062 default 16 if ARCH_EP93XX
1066 bool "Enable iWMMXt support" if !CPU_PJ4
1067 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1068 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4
1070 Enable support for iWMMXt context switching at run time if
1071 running on a CPU that supports it.
1073 config MULTI_IRQ_HANDLER
1076 Allow each machine to specify it's own IRQ handler at run time.
1079 source "arch/arm/Kconfig-nommu"
1082 config PJ4B_ERRATA_4742
1083 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1084 depends on CPU_PJ4B && MACH_ARMADA_370
1087 When coming out of either a Wait for Interrupt (WFI) or a Wait for
1088 Event (WFE) IDLE states, a specific timing sensitivity exists between
1089 the retiring WFI/WFE instructions and the newly issued subsequent
1090 instructions. This sensitivity can result in a CPU hang scenario.
1092 The software must insert either a Data Synchronization Barrier (DSB)
1093 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1096 config ARM_ERRATA_326103
1097 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1100 Executing a SWP instruction to read-only memory does not set bit 11
1101 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1102 treat the access as a read, preventing a COW from occurring and
1103 causing the faulting task to livelock.
1105 config ARM_ERRATA_411920
1106 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1107 depends on CPU_V6 || CPU_V6K
1109 Invalidation of the Instruction Cache operation can
1110 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1111 It does not affect the MPCore. This option enables the ARM Ltd.
1112 recommended workaround.
1114 config ARM_ERRATA_430973
1115 bool "ARM errata: Stale prediction on replaced interworking branch"
1118 This option enables the workaround for the 430973 Cortex-A8
1119 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1120 interworking branch is replaced with another code sequence at the
1121 same virtual address, whether due to self-modifying code or virtual
1122 to physical address re-mapping, Cortex-A8 does not recover from the
1123 stale interworking branch prediction. This results in Cortex-A8
1124 executing the new code sequence in the incorrect ARM or Thumb state.
1125 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1126 and also flushes the branch target cache at every context switch.
1127 Note that setting specific bits in the ACTLR register may not be
1128 available in non-secure mode.
1130 config ARM_ERRATA_458693
1131 bool "ARM errata: Processor deadlock when a false hazard is created"
1133 depends on !ARCH_MULTIPLATFORM
1135 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1136 erratum. For very specific sequences of memory operations, it is
1137 possible for a hazard condition intended for a cache line to instead
1138 be incorrectly associated with a different cache line. This false
1139 hazard might then cause a processor deadlock. The workaround enables
1140 the L1 caching of the NEON accesses and disables the PLD instruction
1141 in the ACTLR register. Note that setting specific bits in the ACTLR
1142 register may not be available in non-secure mode.
1144 config ARM_ERRATA_460075
1145 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1147 depends on !ARCH_MULTIPLATFORM
1149 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1150 erratum. Any asynchronous access to the L2 cache may encounter a
1151 situation in which recent store transactions to the L2 cache are lost
1152 and overwritten with stale memory contents from external memory. The
1153 workaround disables the write-allocate mode for the L2 cache via the
1154 ACTLR register. Note that setting specific bits in the ACTLR register
1155 may not be available in non-secure mode.
1157 config ARM_ERRATA_742230
1158 bool "ARM errata: DMB operation may be faulty"
1159 depends on CPU_V7 && SMP
1160 depends on !ARCH_MULTIPLATFORM
1162 This option enables the workaround for the 742230 Cortex-A9
1163 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1164 between two write operations may not ensure the correct visibility
1165 ordering of the two writes. This workaround sets a specific bit in
1166 the diagnostic register of the Cortex-A9 which causes the DMB
1167 instruction to behave as a DSB, ensuring the correct behaviour of
1170 config ARM_ERRATA_742231
1171 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1172 depends on CPU_V7 && SMP
1173 depends on !ARCH_MULTIPLATFORM
1175 This option enables the workaround for the 742231 Cortex-A9
1176 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1177 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1178 accessing some data located in the same cache line, may get corrupted
1179 data due to bad handling of the address hazard when the line gets
1180 replaced from one of the CPUs at the same time as another CPU is
1181 accessing it. This workaround sets specific bits in the diagnostic
1182 register of the Cortex-A9 which reduces the linefill issuing
1183 capabilities of the processor.
1185 config PL310_ERRATA_588369
1186 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1187 depends on CACHE_L2X0
1189 The PL310 L2 cache controller implements three types of Clean &
1190 Invalidate maintenance operations: by Physical Address
1191 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1192 They are architecturally defined to behave as the execution of a
1193 clean operation followed immediately by an invalidate operation,
1194 both performing to the same memory location. This functionality
1195 is not correctly implemented in PL310 as clean lines are not
1196 invalidated as a result of these operations.
1198 config ARM_ERRATA_643719
1199 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1200 depends on CPU_V7 && SMP
1202 This option enables the workaround for the 643719 Cortex-A9 (prior to
1203 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1204 register returns zero when it should return one. The workaround
1205 corrects this value, ensuring cache maintenance operations which use
1206 it behave as intended and avoiding data corruption.
1208 config ARM_ERRATA_720789
1209 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1212 This option enables the workaround for the 720789 Cortex-A9 (prior to
1213 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1214 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1215 As a consequence of this erratum, some TLB entries which should be
1216 invalidated are not, resulting in an incoherency in the system page
1217 tables. The workaround changes the TLB flushing routines to invalidate
1218 entries regardless of the ASID.
1220 config PL310_ERRATA_727915
1221 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1222 depends on CACHE_L2X0
1224 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1225 operation (offset 0x7FC). This operation runs in background so that
1226 PL310 can handle normal accesses while it is in progress. Under very
1227 rare circumstances, due to this erratum, write data can be lost when
1228 PL310 treats a cacheable write transaction during a Clean &
1229 Invalidate by Way operation.
1231 config ARM_ERRATA_743622
1232 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1234 depends on !ARCH_MULTIPLATFORM
1236 This option enables the workaround for the 743622 Cortex-A9
1237 (r2p*) erratum. Under very rare conditions, a faulty
1238 optimisation in the Cortex-A9 Store Buffer may lead to data
1239 corruption. This workaround sets a specific bit in the diagnostic
1240 register of the Cortex-A9 which disables the Store Buffer
1241 optimisation, preventing the defect from occurring. This has no
1242 visible impact on the overall performance or power consumption of the
1245 config ARM_ERRATA_751472
1246 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1248 depends on !ARCH_MULTIPLATFORM
1250 This option enables the workaround for the 751472 Cortex-A9 (prior
1251 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1252 completion of a following broadcasted operation if the second
1253 operation is received by a CPU before the ICIALLUIS has completed,
1254 potentially leading to corrupted entries in the cache or TLB.
1256 config PL310_ERRATA_753970
1257 bool "PL310 errata: cache sync operation may be faulty"
1258 depends on CACHE_PL310
1260 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1262 Under some condition the effect of cache sync operation on
1263 the store buffer still remains when the operation completes.
1264 This means that the store buffer is always asked to drain and
1265 this prevents it from merging any further writes. The workaround
1266 is to replace the normal offset of cache sync operation (0x730)
1267 by another offset targeting an unmapped PL310 register 0x740.
1268 This has the same effect as the cache sync operation: store buffer
1269 drain and waiting for all buffers empty.
1271 config ARM_ERRATA_754322
1272 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1275 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1276 r3p*) erratum. A speculative memory access may cause a page table walk
1277 which starts prior to an ASID switch but completes afterwards. This
1278 can populate the micro-TLB with a stale entry which may be hit with
1279 the new ASID. This workaround places two dsb instructions in the mm
1280 switching code so that no page table walks can cross the ASID switch.
1282 config ARM_ERRATA_754327
1283 bool "ARM errata: no automatic Store Buffer drain"
1284 depends on CPU_V7 && SMP
1286 This option enables the workaround for the 754327 Cortex-A9 (prior to
1287 r2p0) erratum. The Store Buffer does not have any automatic draining
1288 mechanism and therefore a livelock may occur if an external agent
1289 continuously polls a memory location waiting to observe an update.
1290 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1291 written polling loops from denying visibility of updates to memory.
1293 config ARM_ERRATA_364296
1294 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1297 This options enables the workaround for the 364296 ARM1136
1298 r0p2 erratum (possible cache data corruption with
1299 hit-under-miss enabled). It sets the undocumented bit 31 in
1300 the auxiliary control register and the FI bit in the control
1301 register, thus disabling hit-under-miss without putting the
1302 processor into full low interrupt latency mode. ARM11MPCore
1305 config ARM_ERRATA_764369
1306 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1307 depends on CPU_V7 && SMP
1309 This option enables the workaround for erratum 764369
1310 affecting Cortex-A9 MPCore with two or more processors (all
1311 current revisions). Under certain timing circumstances, a data
1312 cache line maintenance operation by MVA targeting an Inner
1313 Shareable memory region may fail to proceed up to either the
1314 Point of Coherency or to the Point of Unification of the
1315 system. This workaround adds a DSB instruction before the
1316 relevant cache maintenance functions and sets a specific bit
1317 in the diagnostic control register of the SCU.
1319 config PL310_ERRATA_769419
1320 bool "PL310 errata: no automatic Store Buffer drain"
1321 depends on CACHE_L2X0
1323 On revisions of the PL310 prior to r3p2, the Store Buffer does
1324 not automatically drain. This can cause normal, non-cacheable
1325 writes to be retained when the memory system is idle, leading
1326 to suboptimal I/O performance for drivers using coherent DMA.
1327 This option adds a write barrier to the cpu_idle loop so that,
1328 on systems with an outer cache, the store buffer is drained
1331 config ARM_ERRATA_775420
1332 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1335 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1336 r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1337 operation aborts with MMU exception, it might cause the processor
1338 to deadlock. This workaround puts DSB before executing ISB if
1339 an abort may occur on cache maintenance.
1341 config ARM_ERRATA_798181
1342 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1343 depends on CPU_V7 && SMP
1345 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1346 adequately shooting down all use of the old entries. This
1347 option enables the Linux kernel workaround for this erratum
1348 which sends an IPI to the CPUs that are running the same ASID
1349 as the one being invalidated.
1351 config ARM_ERRATA_773022
1352 bool "ARM errata: incorrect instructions may be executed from loop buffer"
1355 This option enables the workaround for the 773022 Cortex-A15
1356 (up to r0p4) erratum. In certain rare sequences of code, the
1357 loop buffer may deliver incorrect instructions. This
1358 workaround disables the loop buffer to avoid the erratum.
1362 source "arch/arm/common/Kconfig"
1372 Find out whether you have ISA slots on your motherboard. ISA is the
1373 name of a bus system, i.e. the way the CPU talks to the other stuff
1374 inside your box. Other bus systems are PCI, EISA, MicroChannel
1375 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1376 newer boards don't support it. If you have ISA, say Y, otherwise N.
1378 # Select ISA DMA controller support
1383 # Select ISA DMA interface
1388 bool "PCI support" if MIGHT_HAVE_PCI
1390 Find out whether you have a PCI motherboard. PCI is the name of a
1391 bus system, i.e. the way the CPU talks to the other stuff inside
1392 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1393 VESA. If you have PCI, say Y, otherwise N.
1399 config PCI_NANOENGINE
1400 bool "BSE nanoEngine PCI support"
1401 depends on SA1100_NANOENGINE
1403 Enable PCI on the BSE nanoEngine board.
1408 config PCI_HOST_ITE8152
1410 depends on PCI && MACH_ARMCORE
1414 source "drivers/pci/Kconfig"
1415 source "drivers/pci/pcie/Kconfig"
1417 source "drivers/pcmcia/Kconfig"
1421 menu "Kernel Features"
1426 This option should be selected by machines which have an SMP-
1429 The only effect of this option is to make the SMP-related
1430 options available to the user for configuration.
1433 bool "Symmetric Multi-Processing"
1434 depends on CPU_V6K || CPU_V7
1435 depends on GENERIC_CLOCKEVENTS
1437 depends on MMU || ARM_MPU
1439 This enables support for systems with more than one CPU. If you have
1440 a system with only one CPU, like most personal computers, say N. If
1441 you have a system with more than one CPU, say Y.
1443 If you say N here, the kernel will run on single and multiprocessor
1444 machines, but will use only one CPU of a multiprocessor machine. If
1445 you say Y here, the kernel will run on many, but not all, single
1446 processor machines. On a single processor machine, the kernel will
1447 run faster if you say N here.
1449 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1450 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1451 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1453 If you don't know what to do here, say N.
1456 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1457 depends on SMP && !XIP_KERNEL && MMU
1460 SMP kernels contain instructions which fail on non-SMP processors.
1461 Enabling this option allows the kernel to modify itself to make
1462 these instructions safe. Disabling it allows about 1K of space
1465 If you don't know what to do here, say Y.
1467 config ARM_CPU_TOPOLOGY
1468 bool "Support cpu topology definition"
1469 depends on SMP && CPU_V7
1472 Support ARM cpu topology definition. The MPIDR register defines
1473 affinity between processors which is then used to describe the cpu
1474 topology of an ARM System.
1477 bool "Multi-core scheduler support"
1478 depends on ARM_CPU_TOPOLOGY
1480 Multi-core scheduler support improves the CPU scheduler's decision
1481 making when dealing with multi-core CPU chips at a cost of slightly
1482 increased overhead in some places. If unsure say N here.
1485 bool "SMT scheduler support"
1486 depends on ARM_CPU_TOPOLOGY
1488 Improves the CPU scheduler's decision making when dealing with
1489 MultiThreading at a cost of slightly increased overhead in some
1490 places. If unsure say N here.
1495 This option enables support for the ARM system coherency unit
1497 config HAVE_ARM_ARCH_TIMER
1498 bool "Architected timer support"
1500 select ARM_ARCH_TIMER
1501 select GENERIC_CLOCKEVENTS
1503 This option enables support for the ARM architected timer
1508 select CLKSRC_OF if OF
1510 This options enables support for the ARM timer and watchdog unit
1513 bool "Multi-Cluster Power Management"
1514 depends on CPU_V7 && SMP
1516 This option provides the common power management infrastructure
1517 for (multi-)cluster based systems, such as big.LITTLE based
1521 bool "big.LITTLE support (Experimental)"
1522 depends on CPU_V7 && SMP
1525 This option enables support selections for the big.LITTLE
1526 system architecture.
1529 bool "big.LITTLE switcher support"
1530 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1532 select ARM_CPU_SUSPEND
1534 The big.LITTLE "switcher" provides the core functionality to
1535 transparently handle transition between a cluster of A15's
1536 and a cluster of A7's in a big.LITTLE system.
1538 config BL_SWITCHER_DUMMY_IF
1539 tristate "Simple big.LITTLE switcher user interface"
1540 depends on BL_SWITCHER && DEBUG_KERNEL
1542 This is a simple and dummy char dev interface to control
1543 the big.LITTLE switcher core code. It is meant for
1544 debugging purposes only.
1547 prompt "Memory split"
1550 Select the desired split between kernel and user memory.
1552 If you are not absolutely sure what you are doing, leave this
1556 bool "3G/1G user/kernel split"
1558 bool "2G/2G user/kernel split"
1560 bool "1G/3G user/kernel split"
1565 default 0x40000000 if VMSPLIT_1G
1566 default 0x80000000 if VMSPLIT_2G
1570 int "Maximum number of CPUs (2-32)"
1576 bool "Support for hot-pluggable CPUs"
1579 Say Y here to experiment with turning CPUs off and on. CPUs
1580 can be controlled through /sys/devices/system/cpu.
1583 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1586 Say Y here if you want Linux to communicate with system firmware
1587 implementing the PSCI specification for CPU-centric power
1588 management operations described in ARM document number ARM DEN
1589 0022A ("Power State Coordination Interface System Software on
1592 # The GPIO number here must be sorted by descending number. In case of
1593 # a multiplatform kernel, we just want the highest value required by the
1594 # selected platforms.
1597 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1598 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || SOC_DRA7XX
1599 default 392 if ARCH_U8500
1600 default 352 if ARCH_VT8500
1601 default 288 if ARCH_SUNXI
1602 default 264 if MACH_H4700
1605 Maximum number of GPIOs in the system.
1607 If unsure, leave the default value.
1609 source kernel/Kconfig.preempt
1613 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1614 ARCH_S5PV210 || ARCH_EXYNOS4
1615 default AT91_TIMER_HZ if ARCH_AT91
1616 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1620 depends on HZ_FIXED = 0
1621 prompt "Timer frequency"
1645 default HZ_FIXED if HZ_FIXED != 0
1646 default 100 if HZ_100
1647 default 200 if HZ_200
1648 default 250 if HZ_250
1649 default 300 if HZ_300
1650 default 500 if HZ_500
1654 def_bool HIGH_RES_TIMERS
1656 config THUMB2_KERNEL
1657 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1658 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1659 default y if CPU_THUMBONLY
1661 select ARM_ASM_UNIFIED
1664 By enabling this option, the kernel will be compiled in
1665 Thumb-2 mode. A compiler/assembler that understand the unified
1666 ARM-Thumb syntax is needed.
1670 config THUMB2_AVOID_R_ARM_THM_JUMP11
1671 bool "Work around buggy Thumb-2 short branch relocations in gas"
1672 depends on THUMB2_KERNEL && MODULES
1675 Various binutils versions can resolve Thumb-2 branches to
1676 locally-defined, preemptible global symbols as short-range "b.n"
1677 branch instructions.
1679 This is a problem, because there's no guarantee the final
1680 destination of the symbol, or any candidate locations for a
1681 trampoline, are within range of the branch. For this reason, the
1682 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1683 relocation in modules at all, and it makes little sense to add
1686 The symptom is that the kernel fails with an "unsupported
1687 relocation" error when loading some modules.
1689 Until fixed tools are available, passing
1690 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1691 code which hits this problem, at the cost of a bit of extra runtime
1692 stack usage in some cases.
1694 The problem is described in more detail at:
1695 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1697 Only Thumb-2 kernels are affected.
1699 Unless you are sure your tools don't have this problem, say Y.
1701 config ARM_ASM_UNIFIED
1705 bool "Use the ARM EABI to compile the kernel"
1707 This option allows for the kernel to be compiled using the latest
1708 ARM ABI (aka EABI). This is only useful if you are using a user
1709 space environment that is also compiled with EABI.
1711 Since there are major incompatibilities between the legacy ABI and
1712 EABI, especially with regard to structure member alignment, this
1713 option also changes the kernel syscall calling convention to
1714 disambiguate both ABIs and allow for backward compatibility support
1715 (selected with CONFIG_OABI_COMPAT).
1717 To use this you need GCC version 4.0.0 or later.
1720 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1721 depends on AEABI && !THUMB2_KERNEL
1723 This option preserves the old syscall interface along with the
1724 new (ARM EABI) one. It also provides a compatibility layer to
1725 intercept syscalls that have structure arguments which layout
1726 in memory differs between the legacy ABI and the new ARM EABI
1727 (only for non "thumb" binaries). This option adds a tiny
1728 overhead to all syscalls and produces a slightly larger kernel.
1730 The seccomp filter system will not be available when this is
1731 selected, since there is no way yet to sensibly distinguish
1732 between calling conventions during filtering.
1734 If you know you'll be using only pure EABI user space then you
1735 can say N here. If this option is not selected and you attempt
1736 to execute a legacy ABI binary then the result will be
1737 UNPREDICTABLE (in fact it can be predicted that it won't work
1738 at all). If in doubt say N.
1740 config ARCH_HAS_HOLES_MEMORYMODEL
1743 config ARCH_SPARSEMEM_ENABLE
1746 config ARCH_SPARSEMEM_DEFAULT
1747 def_bool ARCH_SPARSEMEM_ENABLE
1749 config ARCH_SELECT_MEMORY_MODEL
1750 def_bool ARCH_SPARSEMEM_ENABLE
1752 config HAVE_ARCH_PFN_VALID
1753 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1756 bool "High Memory Support"
1759 The address space of ARM processors is only 4 Gigabytes large
1760 and it has to accommodate user address space, kernel address
1761 space as well as some memory mapped IO. That means that, if you
1762 have a large amount of physical memory and/or IO, not all of the
1763 memory can be "permanently mapped" by the kernel. The physical
1764 memory that is not permanently mapped is called "high memory".
1766 Depending on the selected kernel/user memory split, minimum
1767 vmalloc space and actual amount of RAM, you may not need this
1768 option which should result in a slightly faster kernel.
1773 bool "Allocate 2nd-level pagetables from highmem"
1776 config HW_PERF_EVENTS
1777 bool "Enable hardware performance counter support for perf events"
1778 depends on PERF_EVENTS
1781 Enable hardware performance counter support for perf events. If
1782 disabled, perf events will use software events only.
1784 config SYS_SUPPORTS_HUGETLBFS
1788 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1792 config ARCH_WANT_GENERAL_HUGETLB
1797 config FORCE_MAX_ZONEORDER
1798 int "Maximum zone order" if ARCH_SHMOBILE
1799 range 11 64 if ARCH_SHMOBILE
1800 default "12" if SOC_AM33XX
1801 default "9" if SA1111
1804 The kernel memory allocator divides physically contiguous memory
1805 blocks into "zones", where each zone is a power of two number of
1806 pages. This option selects the largest power of two that the kernel
1807 keeps in the memory allocator. If you need to allocate very large
1808 blocks of physically contiguous memory, then you may need to
1809 increase this value.
1811 This config option is actually maximum order plus one. For example,
1812 a value of 11 means that the largest free memory block is 2^10 pages.
1814 config ALIGNMENT_TRAP
1816 depends on CPU_CP15_MMU
1817 default y if !ARCH_EBSA110
1818 select HAVE_PROC_CPU if PROC_FS
1820 ARM processors cannot fetch/store information which is not
1821 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1822 address divisible by 4. On 32-bit ARM processors, these non-aligned
1823 fetch/store instructions will be emulated in software if you say
1824 here, which has a severe performance impact. This is necessary for
1825 correct operation of some network protocols. With an IP-only
1826 configuration it is safe to say N, otherwise say Y.
1828 config UACCESS_WITH_MEMCPY
1829 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1831 default y if CPU_FEROCEON
1833 Implement faster copy_to_user and clear_user methods for CPU
1834 cores where a 8-word STM instruction give significantly higher
1835 memory write throughput than a sequence of individual 32bit stores.
1837 A possible side effect is a slight increase in scheduling latency
1838 between threads sharing the same address space if they invoke
1839 such copy operations with large buffers.
1841 However, if the CPU data cache is using a write-allocate mode,
1842 this option is unlikely to provide any performance gain.
1846 prompt "Enable seccomp to safely compute untrusted bytecode"
1848 This kernel feature is useful for number crunching applications
1849 that may need to compute untrusted bytecode during their
1850 execution. By using pipes or other transports made available to
1851 the process as file descriptors supporting the read/write
1852 syscalls, it's possible to isolate those applications in
1853 their own address space using seccomp. Once seccomp is
1854 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1855 and the task is only allowed to execute a few safe syscalls
1856 defined by each seccomp mode.
1858 config CC_STACKPROTECTOR
1859 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1861 This option turns on the -fstack-protector GCC feature. This
1862 feature puts, at the beginning of functions, a canary value on
1863 the stack just before the return address, and validates
1864 the value just before actually returning. Stack based buffer
1865 overflows (that need to overwrite this return address) now also
1866 overwrite the canary, which gets detected and the attack is then
1867 neutralized via a kernel panic.
1868 This feature requires gcc version 4.2 or above.
1881 bool "Xen guest support on ARM (EXPERIMENTAL)"
1882 depends on ARM && AEABI && OF
1883 depends on CPU_V7 && !CPU_V6
1884 depends on !GENERIC_ATOMIC64
1888 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1895 bool "Flattened Device Tree support"
1898 select OF_EARLY_FLATTREE
1900 Include support for flattened device tree machine descriptions.
1903 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1906 This is the traditional way of passing data to the kernel at boot
1907 time. If you are solely relying on the flattened device tree (or
1908 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1909 to remove ATAGS support from your kernel binary. If unsure,
1912 config DEPRECATED_PARAM_STRUCT
1913 bool "Provide old way to pass kernel parameters"
1916 This was deprecated in 2001 and announced to live on for 5 years.
1917 Some old boot loaders still use this way.
1919 # Compressed boot loader in ROM. Yes, we really want to ask about
1920 # TEXT and BSS so we preserve their values in the config files.
1921 config ZBOOT_ROM_TEXT
1922 hex "Compressed ROM boot loader base address"
1925 The physical address at which the ROM-able zImage is to be
1926 placed in the target. Platforms which normally make use of
1927 ROM-able zImage formats normally set this to a suitable
1928 value in their defconfig file.
1930 If ZBOOT_ROM is not enabled, this has no effect.
1932 config ZBOOT_ROM_BSS
1933 hex "Compressed ROM boot loader BSS address"
1936 The base address of an area of read/write memory in the target
1937 for the ROM-able zImage which must be available while the
1938 decompressor is running. It must be large enough to hold the
1939 entire decompressed kernel plus an additional 128 KiB.
1940 Platforms which normally make use of ROM-able zImage formats
1941 normally set this to a suitable value in their defconfig file.
1943 If ZBOOT_ROM is not enabled, this has no effect.
1946 bool "Compressed boot loader in ROM/flash"
1947 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1949 Say Y here if you intend to execute your compressed kernel image
1950 (zImage) directly from ROM or flash. If unsure, say N.
1953 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1954 depends on ZBOOT_ROM && ARCH_SH7372
1955 default ZBOOT_ROM_NONE
1957 Include experimental SD/MMC loading code in the ROM-able zImage.
1958 With this enabled it is possible to write the ROM-able zImage
1959 kernel image to an MMC or SD card and boot the kernel straight
1960 from the reset vector. At reset the processor Mask ROM will load
1961 the first part of the ROM-able zImage which in turn loads the
1962 rest the kernel image to RAM.
1964 config ZBOOT_ROM_NONE
1965 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1967 Do not load image from SD or MMC
1969 config ZBOOT_ROM_MMCIF
1970 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1972 Load image from MMCIF hardware block.
1974 config ZBOOT_ROM_SH_MOBILE_SDHI
1975 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1977 Load image from SDHI hardware block
1981 config ARM_APPENDED_DTB
1982 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1983 depends on OF && !ZBOOT_ROM
1985 With this option, the boot code will look for a device tree binary
1986 (DTB) appended to zImage
1987 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1989 This is meant as a backward compatibility convenience for those
1990 systems with a bootloader that can't be upgraded to accommodate
1991 the documented boot protocol using a device tree.
1993 Beware that there is very little in terms of protection against
1994 this option being confused by leftover garbage in memory that might
1995 look like a DTB header after a reboot if no actual DTB is appended
1996 to zImage. Do not leave this option active in a production kernel
1997 if you don't intend to always append a DTB. Proper passing of the
1998 location into r2 of a bootloader provided DTB is always preferable
2001 config ARM_ATAG_DTB_COMPAT
2002 bool "Supplement the appended DTB with traditional ATAG information"
2003 depends on ARM_APPENDED_DTB
2005 Some old bootloaders can't be updated to a DTB capable one, yet
2006 they provide ATAGs with memory configuration, the ramdisk address,
2007 the kernel cmdline string, etc. Such information is dynamically
2008 provided by the bootloader and can't always be stored in a static
2009 DTB. To allow a device tree enabled kernel to be used with such
2010 bootloaders, this option allows zImage to extract the information
2011 from the ATAG list and store it at run time into the appended DTB.
2014 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2015 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2017 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2018 bool "Use bootloader kernel arguments if available"
2020 Uses the command-line options passed by the boot loader instead of
2021 the device tree bootargs property. If the boot loader doesn't provide
2022 any, the device tree bootargs property will be used.
2024 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2025 bool "Extend with bootloader kernel arguments"
2027 The command-line arguments provided by the boot loader will be
2028 appended to the the device tree bootargs property.
2033 string "Default kernel command string"
2036 On some architectures (EBSA110 and CATS), there is currently no way
2037 for the boot loader to pass arguments to the kernel. For these
2038 architectures, you should supply some command-line options at build
2039 time by entering them here. As a minimum, you should specify the
2040 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2043 prompt "Kernel command line type" if CMDLINE != ""
2044 default CMDLINE_FROM_BOOTLOADER
2047 config CMDLINE_FROM_BOOTLOADER
2048 bool "Use bootloader kernel arguments if available"
2050 Uses the command-line options passed by the boot loader. If
2051 the boot loader doesn't provide any, the default kernel command
2052 string provided in CMDLINE will be used.
2054 config CMDLINE_EXTEND
2055 bool "Extend bootloader kernel arguments"
2057 The command-line arguments provided by the boot loader will be
2058 appended to the default kernel command string.
2060 config CMDLINE_FORCE
2061 bool "Always use the default kernel command string"
2063 Always use the default kernel command string, even if the boot
2064 loader passes other arguments to the kernel.
2065 This is useful if you cannot or don't want to change the
2066 command-line options your boot loader passes to the kernel.
2070 bool "Kernel Execute-In-Place from ROM"
2071 depends on !ZBOOT_ROM && !ARM_LPAE && !ARCH_MULTIPLATFORM
2073 Execute-In-Place allows the kernel to run from non-volatile storage
2074 directly addressable by the CPU, such as NOR flash. This saves RAM
2075 space since the text section of the kernel is not loaded from flash
2076 to RAM. Read-write sections, such as the data section and stack,
2077 are still copied to RAM. The XIP kernel is not compressed since
2078 it has to run directly from flash, so it will take more space to
2079 store it. The flash address used to link the kernel object files,
2080 and for storing it, is configuration dependent. Therefore, if you
2081 say Y here, you must know the proper physical address where to
2082 store the kernel image depending on your own flash memory usage.
2084 Also note that the make target becomes "make xipImage" rather than
2085 "make zImage" or "make Image". The final kernel binary to put in
2086 ROM memory will be arch/arm/boot/xipImage.
2090 config XIP_PHYS_ADDR
2091 hex "XIP Kernel Physical Location"
2092 depends on XIP_KERNEL
2093 default "0x00080000"
2095 This is the physical address in your flash memory the kernel will
2096 be linked for and stored to. This address is dependent on your
2100 bool "Kexec system call (EXPERIMENTAL)"
2101 depends on (!SMP || PM_SLEEP_SMP)
2103 kexec is a system call that implements the ability to shutdown your
2104 current kernel, and to start another kernel. It is like a reboot
2105 but it is independent of the system firmware. And like a reboot
2106 you can start any kernel with it, not just Linux.
2108 It is an ongoing process to be certain the hardware in a machine
2109 is properly shutdown, so do not be surprised if this code does not
2110 initially work for you.
2113 bool "Export atags in procfs"
2114 depends on ATAGS && KEXEC
2117 Should the atags used to boot the kernel be exported in an "atags"
2118 file in procfs. Useful with kexec.
2121 bool "Build kdump crash kernel (EXPERIMENTAL)"
2123 Generate crash dump after being started by kexec. This should
2124 be normally only set in special crash dump kernels which are
2125 loaded in the main kernel with kexec-tools into a specially
2126 reserved region and then later executed after a crash by
2127 kdump/kexec. The crash dump kernel must be compiled to a
2128 memory address not used by the main kernel
2130 For more details see Documentation/kdump/kdump.txt
2132 config AUTO_ZRELADDR
2133 bool "Auto calculation of the decompressed kernel image address"
2134 depends on !ZBOOT_ROM
2136 ZRELADDR is the physical address where the decompressed kernel
2137 image will be placed. If AUTO_ZRELADDR is selected, the address
2138 will be determined at run-time by masking the current IP with
2139 0xf8000000. This assumes the zImage being placed in the first 128MB
2140 from start of memory.
2144 menu "CPU Power Management"
2147 source "drivers/cpufreq/Kconfig"
2150 source "drivers/cpuidle/Kconfig"
2154 menu "Floating point emulation"
2156 comment "At least one emulation must be selected"
2159 bool "NWFPE math emulation"
2160 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2162 Say Y to include the NWFPE floating point emulator in the kernel.
2163 This is necessary to run most binaries. Linux does not currently
2164 support floating point hardware so you need to say Y here even if
2165 your machine has an FPA or floating point co-processor podule.
2167 You may say N here if you are going to load the Acorn FPEmulator
2168 early in the bootup.
2171 bool "Support extended precision"
2172 depends on FPE_NWFPE
2174 Say Y to include 80-bit support in the kernel floating-point
2175 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2176 Note that gcc does not generate 80-bit operations by default,
2177 so in most cases this option only enlarges the size of the
2178 floating point emulator without any good reason.
2180 You almost surely want to say N here.
2183 bool "FastFPE math emulation (EXPERIMENTAL)"
2184 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2186 Say Y here to include the FAST floating point emulator in the kernel.
2187 This is an experimental much faster emulator which now also has full
2188 precision for the mantissa. It does not support any exceptions.
2189 It is very simple, and approximately 3-6 times faster than NWFPE.
2191 It should be sufficient for most programs. It may be not suitable
2192 for scientific calculations, but you have to check this for yourself.
2193 If you do not feel you need a faster FP emulation you should better
2197 bool "VFP-format floating point maths"
2198 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2200 Say Y to include VFP support code in the kernel. This is needed
2201 if your hardware includes a VFP unit.
2203 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2204 release notes and additional status information.
2206 Say N if your target does not have VFP hardware.
2214 bool "Advanced SIMD (NEON) Extension support"
2215 depends on VFPv3 && CPU_V7
2217 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2220 config KERNEL_MODE_NEON
2221 bool "Support for NEON in kernel mode"
2222 depends on NEON && AEABI
2224 Say Y to include support for NEON in kernel mode.
2228 menu "Userspace binary formats"
2230 source "fs/Kconfig.binfmt"
2233 tristate "RISC OS personality"
2236 Say Y here to include the kernel code necessary if you want to run
2237 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2238 experimental; if this sounds frightening, say N and sleep in peace.
2239 You can also say M here to compile this support as a module (which
2240 will be called arthur).
2244 menu "Power management options"
2246 source "kernel/power/Kconfig"
2248 config ARCH_SUSPEND_POSSIBLE
2249 depends on !ARCH_S5PC100
2250 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2251 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2254 config ARM_CPU_SUSPEND
2259 source "net/Kconfig"
2261 source "drivers/Kconfig"
2265 source "arch/arm/Kconfig.debug"
2267 source "security/Kconfig"
2269 source "crypto/Kconfig"
2271 source "lib/Kconfig"
2273 source "arch/arm/kvm/Kconfig"