4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_IO_H
208 Select this when mach/io.h is required to provide special
209 definitions for this platform. The need for mach/io.h should
210 be avoided when possible.
212 config NEED_MACH_MEMORY_H
215 Select this when mach/memory.h is required to provide special
216 definitions for this platform. The need for mach/memory.h should
217 be avoided when possible.
220 hex "Physical address of main memory" if MMU
221 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
222 default DRAM_BASE if !MMU
224 Please provide the physical address corresponding to the
225 location of main memory in your system.
231 source "init/Kconfig"
233 source "kernel/Kconfig.freezer"
238 bool "MMU-based Paged Memory Management Support"
241 Select if you want MMU-based virtualised addressing space
242 support by paged memory management. If unsure, say 'Y'.
245 # The "ARM system type" choice list is ordered alphabetically by option
246 # text. Please add new entries in the option alphabetic order.
249 prompt "ARM system type"
250 default ARCH_VERSATILE
253 bool "Altera SOCFPGA family"
254 select ARCH_WANT_OPTIONAL_GPIOLIB
262 select DW_APB_TIMER_OF
263 select GENERIC_CLOCKEVENTS
264 select GPIO_PL061 if GPIOLIB
269 This enables support for Altera SOCFPGA Cyclone V platform
271 config ARCH_INTEGRATOR
272 bool "ARM Ltd. Integrator family"
274 select ARCH_HAS_CPUFREQ
276 select COMMON_CLK_VERSATILE
279 select GENERIC_CLOCKEVENTS
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_FPGA_IRQ
282 select NEED_MACH_MEMORY_H
284 select MULTI_IRQ_HANDLER
286 Support for ARM's Integrator platform.
289 bool "ARM Ltd. RealView family"
292 select COMMON_CLK_VERSATILE
294 select GENERIC_CLOCKEVENTS
295 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select PLAT_VERSATILE
297 select PLAT_VERSATILE_CLCD
298 select ARM_TIMER_SP804
299 select GPIO_PL061 if GPIOLIB
300 select NEED_MACH_MEMORY_H
302 This enables support for ARM Ltd RealView boards.
304 config ARCH_VERSATILE
305 bool "ARM Ltd. Versatile family"
309 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select PLAT_VERSATILE
314 select PLAT_VERSATILE_CLOCK
315 select PLAT_VERSATILE_CLCD
316 select PLAT_VERSATILE_FPGA_IRQ
317 select ARM_TIMER_SP804
319 This enables support for ARM Ltd Versatile board.
322 bool "ARM Ltd. Versatile Express family"
323 select ARCH_WANT_OPTIONAL_GPIOLIB
325 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
330 select HAVE_PATA_PLATFORM
333 select PLAT_VERSATILE
334 select PLAT_VERSATILE_CLCD
335 select REGULATOR_FIXED_VOLTAGE if REGULATOR
337 This enables support for the ARM Ltd Versatile Express boards.
341 select ARCH_REQUIRE_GPIOLIB
345 select NEED_MACH_IO_H if PCCARD
347 This enables support for systems based on Atmel
348 AT91RM9200 and AT91SAM9* processors.
351 bool "Broadcom BCMRING"
355 select ARM_TIMER_SP804
357 select GENERIC_CLOCKEVENTS
358 select ARCH_WANT_OPTIONAL_GPIOLIB
360 Support for Broadcom's BCMRing platform.
363 bool "Calxeda Highbank-based"
364 select ARCH_WANT_OPTIONAL_GPIOLIB
367 select ARM_TIMER_SP804
372 select GENERIC_CLOCKEVENTS
378 Support for the Calxeda Highbank SoC based boards.
381 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
383 select ARCH_USES_GETTIMEOFFSET
384 select NEED_MACH_MEMORY_H
386 Support for Cirrus Logic 711x/721x/731x based boards.
389 bool "Cavium Networks CNS3XXX family"
391 select GENERIC_CLOCKEVENTS
393 select MIGHT_HAVE_CACHE_L2X0
394 select MIGHT_HAVE_PCI
395 select PCI_DOMAINS if PCI
397 Support for Cavium Networks CNS3XXX platform.
400 bool "Cortina Systems Gemini"
402 select ARCH_REQUIRE_GPIOLIB
403 select ARCH_USES_GETTIMEOFFSET
405 Support for the Cortina Systems Gemini family SoCs
410 select ARCH_REQUIRE_GPIOLIB
411 select GENERIC_CLOCKEVENTS
413 select GENERIC_IRQ_CHIP
414 select MIGHT_HAVE_CACHE_L2X0
419 Support for CSR SiRFprimaII/Marco/Polo platforms
426 select ARCH_USES_GETTIMEOFFSET
427 select NEED_MACH_IO_H
428 select NEED_MACH_MEMORY_H
430 This is an evaluation board for the StrongARM processor available
431 from Digital. It has limited hardware on-board, including an
432 Ethernet interface, two PCMCIA sockets, two serial ports and a
441 select ARCH_REQUIRE_GPIOLIB
442 select ARCH_HAS_HOLES_MEMORYMODEL
443 select ARCH_USES_GETTIMEOFFSET
444 select NEED_MACH_MEMORY_H
446 This enables support for the Cirrus EP93xx series of CPUs.
448 config ARCH_FOOTBRIDGE
452 select GENERIC_CLOCKEVENTS
454 select NEED_MACH_IO_H if !MMU
455 select NEED_MACH_MEMORY_H
457 Support for systems based on the DC21285 companion chip
458 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
461 bool "Freescale MXC/iMX-based"
462 select GENERIC_CLOCKEVENTS
463 select ARCH_REQUIRE_GPIOLIB
466 select GENERIC_IRQ_CHIP
467 select MULTI_IRQ_HANDLER
471 Support for Freescale MXC/iMX-based family of processors
474 bool "Freescale MXS-based"
475 select GENERIC_CLOCKEVENTS
476 select ARCH_REQUIRE_GPIOLIB
480 select HAVE_CLK_PREPARE
484 Support for Freescale MXS-based family of processors
487 bool "Hilscher NetX based"
491 select GENERIC_CLOCKEVENTS
493 This enables support for systems based on the Hilscher NetX Soc
496 bool "Hynix HMS720x-based"
499 select ARCH_USES_GETTIMEOFFSET
501 This enables support for systems based on the Hynix HMS720x
509 select ARCH_SUPPORTS_MSI
511 select NEED_MACH_MEMORY_H
512 select NEED_RET_TO_USER
514 Support for Intel's IOP13XX (XScale) family of processors.
520 select NEED_RET_TO_USER
523 select ARCH_REQUIRE_GPIOLIB
525 Support for Intel's 80219 and IOP32X (XScale) family of
532 select NEED_RET_TO_USER
535 select ARCH_REQUIRE_GPIOLIB
537 Support for Intel's IOP33X (XScale) family of processors.
542 select ARCH_HAS_DMA_SET_COHERENT_MASK
545 select ARCH_REQUIRE_GPIOLIB
546 select GENERIC_CLOCKEVENTS
547 select MIGHT_HAVE_PCI
548 select NEED_MACH_IO_H
549 select DMABOUNCE if PCI
551 Support for Intel's IXP4XX (XScale) family of processors.
554 bool "Marvell SOCs with Device Tree support"
555 select GENERIC_CLOCKEVENTS
556 select MULTI_IRQ_HANDLER
559 select GENERIC_IRQ_CHIP
563 Support for the Marvell SoC Family with device tree support
569 select ARCH_REQUIRE_GPIOLIB
570 select GENERIC_CLOCKEVENTS
573 Support for the Marvell Dove SoC 88AP510
576 bool "Marvell Kirkwood"
579 select ARCH_REQUIRE_GPIOLIB
580 select GENERIC_CLOCKEVENTS
583 Support for the following Marvell Kirkwood series SoCs:
584 88F6180, 88F6192 and 88F6281.
590 select ARCH_REQUIRE_GPIOLIB
593 select USB_ARCH_HAS_OHCI
595 select GENERIC_CLOCKEVENTS
599 Support for the NXP LPC32XX family of processors
602 bool "Marvell MV78xx0"
605 select ARCH_REQUIRE_GPIOLIB
606 select GENERIC_CLOCKEVENTS
609 Support for the following Marvell MV78xx0 series SoCs:
617 select ARCH_REQUIRE_GPIOLIB
618 select GENERIC_CLOCKEVENTS
621 Support for the following Marvell Orion 5x series SoCs:
622 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
623 Orion-2 (5281), Orion-1-90 (6183).
626 bool "Marvell PXA168/910/MMP2"
628 select ARCH_REQUIRE_GPIOLIB
630 select GENERIC_CLOCKEVENTS
635 select GENERIC_ALLOCATOR
637 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
640 bool "Micrel/Kendin KS8695"
642 select ARCH_REQUIRE_GPIOLIB
643 select NEED_MACH_MEMORY_H
645 select GENERIC_CLOCKEVENTS
647 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
648 System-on-Chip devices.
651 bool "Nuvoton W90X900 CPU"
653 select ARCH_REQUIRE_GPIOLIB
656 select GENERIC_CLOCKEVENTS
658 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
659 At present, the w90x900 has been renamed nuc900, regarding
660 the ARM series product line, you can login the following
661 link address to know more.
663 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
664 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
670 select GENERIC_CLOCKEVENTS
674 select MIGHT_HAVE_CACHE_L2X0
675 select ARCH_HAS_CPUFREQ
678 This enables support for NVIDIA Tegra based systems (Tegra APX,
679 Tegra 6xx and Tegra 2 series).
681 config ARCH_PICOXCELL
682 bool "Picochip picoXcell"
683 select ARCH_REQUIRE_GPIOLIB
684 select ARM_PATCH_PHYS_VIRT
688 select DW_APB_TIMER_OF
689 select GENERIC_CLOCKEVENTS
696 This enables support for systems based on the Picochip picoXcell
697 family of Femtocell devices. The picoxcell support requires device tree
701 bool "PXA2xx/PXA3xx-based"
704 select ARCH_HAS_CPUFREQ
707 select ARCH_REQUIRE_GPIOLIB
708 select GENERIC_CLOCKEVENTS
713 select MULTI_IRQ_HANDLER
714 select ARM_CPU_SUSPEND if PM
717 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
722 select GENERIC_CLOCKEVENTS
723 select ARCH_REQUIRE_GPIOLIB
726 Support for Qualcomm MSM/QSD based systems. This runs on the
727 apps processor of the MSM/QSD and depends on a shared memory
728 interface to the modem processor which runs the baseband
729 stack and controls some vital subsystems
730 (clock and power control, etc).
733 bool "Renesas SH-Mobile / R-Mobile"
736 select HAVE_MACH_CLKDEV
738 select GENERIC_CLOCKEVENTS
739 select MIGHT_HAVE_CACHE_L2X0
742 select MULTI_IRQ_HANDLER
743 select PM_GENERIC_DOMAINS if PM
744 select NEED_MACH_MEMORY_H
746 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
752 select ARCH_MAY_HAVE_PC_FDC
753 select HAVE_PATA_PLATFORM
756 select ARCH_SPARSEMEM_ENABLE
757 select ARCH_USES_GETTIMEOFFSET
759 select NEED_MACH_IO_H
760 select NEED_MACH_MEMORY_H
762 On the Acorn Risc-PC, Linux can support the internal IDE disk and
763 CD-ROM interface, serial and parallel port, and the floppy drive.
770 select ARCH_SPARSEMEM_ENABLE
772 select ARCH_HAS_CPUFREQ
774 select GENERIC_CLOCKEVENTS
776 select ARCH_REQUIRE_GPIOLIB
778 select NEED_MACH_MEMORY_H
781 Support for StrongARM 11x0 based boards.
784 bool "Samsung S3C24XX SoCs"
786 select ARCH_HAS_CPUFREQ
789 select ARCH_USES_GETTIMEOFFSET
790 select HAVE_S3C2410_I2C if I2C
791 select HAVE_S3C_RTC if RTC_CLASS
792 select HAVE_S3C2410_WATCHDOG if WATCHDOG
793 select NEED_MACH_IO_H
795 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
796 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
797 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
798 Samsung SMDK2410 development board (and derivatives).
801 bool "Samsung S3C64XX"
809 select ARCH_USES_GETTIMEOFFSET
810 select ARCH_HAS_CPUFREQ
811 select ARCH_REQUIRE_GPIOLIB
812 select SAMSUNG_CLKSRC
813 select SAMSUNG_IRQ_VIC_TIMER
814 select S3C_GPIO_TRACK
816 select USB_ARCH_HAS_OHCI
817 select SAMSUNG_GPIOLIB_4BIT
818 select HAVE_S3C2410_I2C if I2C
819 select HAVE_S3C2410_WATCHDOG if WATCHDOG
821 Samsung S3C64XX series based systems
824 bool "Samsung S5P6440 S5P6450"
830 select HAVE_S3C2410_WATCHDOG if WATCHDOG
831 select GENERIC_CLOCKEVENTS
832 select HAVE_S3C2410_I2C if I2C
833 select HAVE_S3C_RTC if RTC_CLASS
835 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
839 bool "Samsung S5PC100"
844 select ARCH_USES_GETTIMEOFFSET
845 select HAVE_S3C2410_I2C if I2C
846 select HAVE_S3C_RTC if RTC_CLASS
847 select HAVE_S3C2410_WATCHDOG if WATCHDOG
849 Samsung S5PC100 series based systems
852 bool "Samsung S5PV210/S5PC110"
854 select ARCH_SPARSEMEM_ENABLE
855 select ARCH_HAS_HOLES_MEMORYMODEL
860 select ARCH_HAS_CPUFREQ
861 select GENERIC_CLOCKEVENTS
862 select HAVE_S3C2410_I2C if I2C
863 select HAVE_S3C_RTC if RTC_CLASS
864 select HAVE_S3C2410_WATCHDOG if WATCHDOG
865 select NEED_MACH_MEMORY_H
867 Samsung S5PV210/S5PC110 series based systems
870 bool "SAMSUNG EXYNOS"
872 select ARCH_SPARSEMEM_ENABLE
873 select ARCH_HAS_HOLES_MEMORYMODEL
877 select ARCH_HAS_CPUFREQ
878 select GENERIC_CLOCKEVENTS
879 select HAVE_S3C_RTC if RTC_CLASS
880 select HAVE_S3C2410_I2C if I2C
881 select HAVE_S3C2410_WATCHDOG if WATCHDOG
882 select NEED_MACH_MEMORY_H
884 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
893 select ARCH_USES_GETTIMEOFFSET
894 select NEED_MACH_MEMORY_H
896 Support for the StrongARM based Digital DNARD machine, also known
897 as "Shark" (<http://www.shark-linux.de/shark.html>).
900 bool "ST-Ericsson U300 Series"
906 select ARM_PATCH_PHYS_VIRT
908 select GENERIC_CLOCKEVENTS
912 select ARCH_REQUIRE_GPIOLIB
915 Support for ST-Ericsson U300 series mobile platforms.
918 bool "ST-Ericsson U8500 Series"
922 select GENERIC_CLOCKEVENTS
924 select ARCH_REQUIRE_GPIOLIB
925 select ARCH_HAS_CPUFREQ
927 select MIGHT_HAVE_CACHE_L2X0
929 Support for ST-Ericsson's Ux500 architecture
932 bool "STMicroelectronics Nomadik"
937 select GENERIC_CLOCKEVENTS
939 select MIGHT_HAVE_CACHE_L2X0
940 select ARCH_REQUIRE_GPIOLIB
942 Support for the Nomadik platform by ST-Ericsson
946 select GENERIC_CLOCKEVENTS
947 select ARCH_REQUIRE_GPIOLIB
951 select GENERIC_ALLOCATOR
952 select GENERIC_IRQ_CHIP
953 select ARCH_HAS_HOLES_MEMORYMODEL
955 Support for TI's DaVinci platform.
961 select ARCH_REQUIRE_GPIOLIB
962 select ARCH_HAS_CPUFREQ
964 select GENERIC_CLOCKEVENTS
965 select ARCH_HAS_HOLES_MEMORYMODEL
967 Support for TI's OMAP platform (OMAP1/2/3/4).
972 select ARCH_REQUIRE_GPIOLIB
976 select GENERIC_CLOCKEVENTS
979 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
982 bool "VIA/WonderMedia 85xx"
985 select ARCH_HAS_CPUFREQ
986 select GENERIC_CLOCKEVENTS
987 select ARCH_REQUIRE_GPIOLIB
989 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
992 bool "Xilinx Zynq ARM Cortex A9 Platform"
994 select GENERIC_CLOCKEVENTS
999 select MIGHT_HAVE_CACHE_L2X0
1002 Support for Xilinx Zynq ARM Cortex A9 Platform
1006 # This is sorted alphabetically by mach-* pathname. However, plat-*
1007 # Kconfigs may be included either alphabetically (according to the
1008 # plat- suffix) or along side the corresponding mach-* source.
1010 source "arch/arm/mach-mvebu/Kconfig"
1012 source "arch/arm/mach-at91/Kconfig"
1014 source "arch/arm/mach-bcmring/Kconfig"
1016 source "arch/arm/mach-clps711x/Kconfig"
1018 source "arch/arm/mach-cns3xxx/Kconfig"
1020 source "arch/arm/mach-davinci/Kconfig"
1022 source "arch/arm/mach-dove/Kconfig"
1024 source "arch/arm/mach-ep93xx/Kconfig"
1026 source "arch/arm/mach-footbridge/Kconfig"
1028 source "arch/arm/mach-gemini/Kconfig"
1030 source "arch/arm/mach-h720x/Kconfig"
1032 source "arch/arm/mach-integrator/Kconfig"
1034 source "arch/arm/mach-iop32x/Kconfig"
1036 source "arch/arm/mach-iop33x/Kconfig"
1038 source "arch/arm/mach-iop13xx/Kconfig"
1040 source "arch/arm/mach-ixp4xx/Kconfig"
1042 source "arch/arm/mach-kirkwood/Kconfig"
1044 source "arch/arm/mach-ks8695/Kconfig"
1046 source "arch/arm/mach-msm/Kconfig"
1048 source "arch/arm/mach-mv78xx0/Kconfig"
1050 source "arch/arm/plat-mxc/Kconfig"
1052 source "arch/arm/mach-mxs/Kconfig"
1054 source "arch/arm/mach-netx/Kconfig"
1056 source "arch/arm/mach-nomadik/Kconfig"
1057 source "arch/arm/plat-nomadik/Kconfig"
1059 source "arch/arm/plat-omap/Kconfig"
1061 source "arch/arm/mach-omap1/Kconfig"
1063 source "arch/arm/mach-omap2/Kconfig"
1065 source "arch/arm/mach-orion5x/Kconfig"
1067 source "arch/arm/mach-pxa/Kconfig"
1068 source "arch/arm/plat-pxa/Kconfig"
1070 source "arch/arm/mach-mmp/Kconfig"
1072 source "arch/arm/mach-realview/Kconfig"
1074 source "arch/arm/mach-sa1100/Kconfig"
1076 source "arch/arm/plat-samsung/Kconfig"
1077 source "arch/arm/plat-s3c24xx/Kconfig"
1079 source "arch/arm/plat-spear/Kconfig"
1081 source "arch/arm/mach-s3c24xx/Kconfig"
1083 source "arch/arm/mach-s3c2412/Kconfig"
1084 source "arch/arm/mach-s3c2440/Kconfig"
1088 source "arch/arm/mach-s3c64xx/Kconfig"
1091 source "arch/arm/mach-s5p64x0/Kconfig"
1093 source "arch/arm/mach-s5pc100/Kconfig"
1095 source "arch/arm/mach-s5pv210/Kconfig"
1097 source "arch/arm/mach-exynos/Kconfig"
1099 source "arch/arm/mach-shmobile/Kconfig"
1101 source "arch/arm/mach-prima2/Kconfig"
1103 source "arch/arm/mach-tegra/Kconfig"
1105 source "arch/arm/mach-u300/Kconfig"
1107 source "arch/arm/mach-ux500/Kconfig"
1109 source "arch/arm/mach-versatile/Kconfig"
1111 source "arch/arm/mach-vexpress/Kconfig"
1112 source "arch/arm/plat-versatile/Kconfig"
1114 source "arch/arm/mach-vt8500/Kconfig"
1116 source "arch/arm/mach-w90x900/Kconfig"
1118 # Definitions to make life easier
1124 select GENERIC_CLOCKEVENTS
1129 select GENERIC_IRQ_CHIP
1136 config PLAT_VERSATILE
1139 config ARM_TIMER_SP804
1142 select HAVE_SCHED_CLOCK
1144 source arch/arm/mm/Kconfig
1148 default 16 if ARCH_EP93XX
1152 bool "Enable iWMMXt support"
1153 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1154 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1156 Enable support for iWMMXt context switching at run time if
1157 running on a CPU that supports it.
1161 depends on CPU_XSCALE
1164 config MULTI_IRQ_HANDLER
1167 Allow each machine to specify it's own IRQ handler at run time.
1170 source "arch/arm/Kconfig-nommu"
1173 config ARM_ERRATA_326103
1174 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1177 Executing a SWP instruction to read-only memory does not set bit 11
1178 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1179 treat the access as a read, preventing a COW from occurring and
1180 causing the faulting task to livelock.
1182 config ARM_ERRATA_411920
1183 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1184 depends on CPU_V6 || CPU_V6K
1186 Invalidation of the Instruction Cache operation can
1187 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1188 It does not affect the MPCore. This option enables the ARM Ltd.
1189 recommended workaround.
1191 config ARM_ERRATA_430973
1192 bool "ARM errata: Stale prediction on replaced interworking branch"
1195 This option enables the workaround for the 430973 Cortex-A8
1196 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1197 interworking branch is replaced with another code sequence at the
1198 same virtual address, whether due to self-modifying code or virtual
1199 to physical address re-mapping, Cortex-A8 does not recover from the
1200 stale interworking branch prediction. This results in Cortex-A8
1201 executing the new code sequence in the incorrect ARM or Thumb state.
1202 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1203 and also flushes the branch target cache at every context switch.
1204 Note that setting specific bits in the ACTLR register may not be
1205 available in non-secure mode.
1207 config ARM_ERRATA_458693
1208 bool "ARM errata: Processor deadlock when a false hazard is created"
1211 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1212 erratum. For very specific sequences of memory operations, it is
1213 possible for a hazard condition intended for a cache line to instead
1214 be incorrectly associated with a different cache line. This false
1215 hazard might then cause a processor deadlock. The workaround enables
1216 the L1 caching of the NEON accesses and disables the PLD instruction
1217 in the ACTLR register. Note that setting specific bits in the ACTLR
1218 register may not be available in non-secure mode.
1220 config ARM_ERRATA_460075
1221 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1224 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1225 erratum. Any asynchronous access to the L2 cache may encounter a
1226 situation in which recent store transactions to the L2 cache are lost
1227 and overwritten with stale memory contents from external memory. The
1228 workaround disables the write-allocate mode for the L2 cache via the
1229 ACTLR register. Note that setting specific bits in the ACTLR register
1230 may not be available in non-secure mode.
1232 config ARM_ERRATA_742230
1233 bool "ARM errata: DMB operation may be faulty"
1234 depends on CPU_V7 && SMP
1236 This option enables the workaround for the 742230 Cortex-A9
1237 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1238 between two write operations may not ensure the correct visibility
1239 ordering of the two writes. This workaround sets a specific bit in
1240 the diagnostic register of the Cortex-A9 which causes the DMB
1241 instruction to behave as a DSB, ensuring the correct behaviour of
1244 config ARM_ERRATA_742231
1245 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1246 depends on CPU_V7 && SMP
1248 This option enables the workaround for the 742231 Cortex-A9
1249 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1250 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1251 accessing some data located in the same cache line, may get corrupted
1252 data due to bad handling of the address hazard when the line gets
1253 replaced from one of the CPUs at the same time as another CPU is
1254 accessing it. This workaround sets specific bits in the diagnostic
1255 register of the Cortex-A9 which reduces the linefill issuing
1256 capabilities of the processor.
1258 config PL310_ERRATA_588369
1259 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1260 depends on CACHE_L2X0
1262 The PL310 L2 cache controller implements three types of Clean &
1263 Invalidate maintenance operations: by Physical Address
1264 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1265 They are architecturally defined to behave as the execution of a
1266 clean operation followed immediately by an invalidate operation,
1267 both performing to the same memory location. This functionality
1268 is not correctly implemented in PL310 as clean lines are not
1269 invalidated as a result of these operations.
1271 config ARM_ERRATA_720789
1272 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1275 This option enables the workaround for the 720789 Cortex-A9 (prior to
1276 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1277 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1278 As a consequence of this erratum, some TLB entries which should be
1279 invalidated are not, resulting in an incoherency in the system page
1280 tables. The workaround changes the TLB flushing routines to invalidate
1281 entries regardless of the ASID.
1283 config PL310_ERRATA_727915
1284 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1285 depends on CACHE_L2X0
1287 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1288 operation (offset 0x7FC). This operation runs in background so that
1289 PL310 can handle normal accesses while it is in progress. Under very
1290 rare circumstances, due to this erratum, write data can be lost when
1291 PL310 treats a cacheable write transaction during a Clean &
1292 Invalidate by Way operation.
1294 config ARM_ERRATA_743622
1295 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1298 This option enables the workaround for the 743622 Cortex-A9
1299 (r2p*) erratum. Under very rare conditions, a faulty
1300 optimisation in the Cortex-A9 Store Buffer may lead to data
1301 corruption. This workaround sets a specific bit in the diagnostic
1302 register of the Cortex-A9 which disables the Store Buffer
1303 optimisation, preventing the defect from occurring. This has no
1304 visible impact on the overall performance or power consumption of the
1307 config ARM_ERRATA_751472
1308 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1311 This option enables the workaround for the 751472 Cortex-A9 (prior
1312 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1313 completion of a following broadcasted operation if the second
1314 operation is received by a CPU before the ICIALLUIS has completed,
1315 potentially leading to corrupted entries in the cache or TLB.
1317 config PL310_ERRATA_753970
1318 bool "PL310 errata: cache sync operation may be faulty"
1319 depends on CACHE_PL310
1321 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1323 Under some condition the effect of cache sync operation on
1324 the store buffer still remains when the operation completes.
1325 This means that the store buffer is always asked to drain and
1326 this prevents it from merging any further writes. The workaround
1327 is to replace the normal offset of cache sync operation (0x730)
1328 by another offset targeting an unmapped PL310 register 0x740.
1329 This has the same effect as the cache sync operation: store buffer
1330 drain and waiting for all buffers empty.
1332 config ARM_ERRATA_754322
1333 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1336 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1337 r3p*) erratum. A speculative memory access may cause a page table walk
1338 which starts prior to an ASID switch but completes afterwards. This
1339 can populate the micro-TLB with a stale entry which may be hit with
1340 the new ASID. This workaround places two dsb instructions in the mm
1341 switching code so that no page table walks can cross the ASID switch.
1343 config ARM_ERRATA_754327
1344 bool "ARM errata: no automatic Store Buffer drain"
1345 depends on CPU_V7 && SMP
1347 This option enables the workaround for the 754327 Cortex-A9 (prior to
1348 r2p0) erratum. The Store Buffer does not have any automatic draining
1349 mechanism and therefore a livelock may occur if an external agent
1350 continuously polls a memory location waiting to observe an update.
1351 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1352 written polling loops from denying visibility of updates to memory.
1354 config ARM_ERRATA_364296
1355 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1356 depends on CPU_V6 && !SMP
1358 This options enables the workaround for the 364296 ARM1136
1359 r0p2 erratum (possible cache data corruption with
1360 hit-under-miss enabled). It sets the undocumented bit 31 in
1361 the auxiliary control register and the FI bit in the control
1362 register, thus disabling hit-under-miss without putting the
1363 processor into full low interrupt latency mode. ARM11MPCore
1366 config ARM_ERRATA_764369
1367 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1368 depends on CPU_V7 && SMP
1370 This option enables the workaround for erratum 764369
1371 affecting Cortex-A9 MPCore with two or more processors (all
1372 current revisions). Under certain timing circumstances, a data
1373 cache line maintenance operation by MVA targeting an Inner
1374 Shareable memory region may fail to proceed up to either the
1375 Point of Coherency or to the Point of Unification of the
1376 system. This workaround adds a DSB instruction before the
1377 relevant cache maintenance functions and sets a specific bit
1378 in the diagnostic control register of the SCU.
1380 config PL310_ERRATA_769419
1381 bool "PL310 errata: no automatic Store Buffer drain"
1382 depends on CACHE_L2X0
1384 On revisions of the PL310 prior to r3p2, the Store Buffer does
1385 not automatically drain. This can cause normal, non-cacheable
1386 writes to be retained when the memory system is idle, leading
1387 to suboptimal I/O performance for drivers using coherent DMA.
1388 This option adds a write barrier to the cpu_idle loop so that,
1389 on systems with an outer cache, the store buffer is drained
1394 source "arch/arm/common/Kconfig"
1404 Find out whether you have ISA slots on your motherboard. ISA is the
1405 name of a bus system, i.e. the way the CPU talks to the other stuff
1406 inside your box. Other bus systems are PCI, EISA, MicroChannel
1407 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1408 newer boards don't support it. If you have ISA, say Y, otherwise N.
1410 # Select ISA DMA controller support
1415 # Select ISA DMA interface
1420 bool "PCI support" if MIGHT_HAVE_PCI
1422 Find out whether you have a PCI motherboard. PCI is the name of a
1423 bus system, i.e. the way the CPU talks to the other stuff inside
1424 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1425 VESA. If you have PCI, say Y, otherwise N.
1431 config PCI_NANOENGINE
1432 bool "BSE nanoEngine PCI support"
1433 depends on SA1100_NANOENGINE
1435 Enable PCI on the BSE nanoEngine board.
1440 # Select the host bridge type
1441 config PCI_HOST_VIA82C505
1443 depends on PCI && ARCH_SHARK
1446 config PCI_HOST_ITE8152
1448 depends on PCI && MACH_ARMCORE
1452 source "drivers/pci/Kconfig"
1454 source "drivers/pcmcia/Kconfig"
1458 menu "Kernel Features"
1463 This option should be selected by machines which have an SMP-
1466 The only effect of this option is to make the SMP-related
1467 options available to the user for configuration.
1470 bool "Symmetric Multi-Processing"
1471 depends on CPU_V6K || CPU_V7
1472 depends on GENERIC_CLOCKEVENTS
1475 select USE_GENERIC_SMP_HELPERS
1476 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1478 This enables support for systems with more than one CPU. If you have
1479 a system with only one CPU, like most personal computers, say N. If
1480 you have a system with more than one CPU, say Y.
1482 If you say N here, the kernel will run on single and multiprocessor
1483 machines, but will use only one CPU of a multiprocessor machine. If
1484 you say Y here, the kernel will run on many, but not all, single
1485 processor machines. On a single processor machine, the kernel will
1486 run faster if you say N here.
1488 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1489 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1490 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1492 If you don't know what to do here, say N.
1495 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1496 depends on EXPERIMENTAL
1497 depends on SMP && !XIP_KERNEL
1500 SMP kernels contain instructions which fail on non-SMP processors.
1501 Enabling this option allows the kernel to modify itself to make
1502 these instructions safe. Disabling it allows about 1K of space
1505 If you don't know what to do here, say Y.
1507 config ARM_CPU_TOPOLOGY
1508 bool "Support cpu topology definition"
1509 depends on SMP && CPU_V7
1512 Support ARM cpu topology definition. The MPIDR register defines
1513 affinity between processors which is then used to describe the cpu
1514 topology of an ARM System.
1517 bool "Multi-core scheduler support"
1518 depends on ARM_CPU_TOPOLOGY
1520 Multi-core scheduler support improves the CPU scheduler's decision
1521 making when dealing with multi-core CPU chips at a cost of slightly
1522 increased overhead in some places. If unsure say N here.
1525 bool "SMT scheduler support"
1526 depends on ARM_CPU_TOPOLOGY
1528 Improves the CPU scheduler's decision making when dealing with
1529 MultiThreading at a cost of slightly increased overhead in some
1530 places. If unsure say N here.
1535 This option enables support for the ARM system coherency unit
1537 config ARM_ARCH_TIMER
1538 bool "Architected timer support"
1541 This option enables support for the ARM architected timer
1547 This options enables support for the ARM timer and watchdog unit
1550 prompt "Memory split"
1553 Select the desired split between kernel and user memory.
1555 If you are not absolutely sure what you are doing, leave this
1559 bool "3G/1G user/kernel split"
1561 bool "2G/2G user/kernel split"
1563 bool "1G/3G user/kernel split"
1568 default 0x40000000 if VMSPLIT_1G
1569 default 0x80000000 if VMSPLIT_2G
1573 int "Maximum number of CPUs (2-32)"
1579 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1580 depends on SMP && HOTPLUG && EXPERIMENTAL
1582 Say Y here to experiment with turning CPUs off and on. CPUs
1583 can be controlled through /sys/devices/system/cpu.
1586 bool "Use local timer interrupts"
1589 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1591 Enable support for local timers on SMP platforms, rather then the
1592 legacy IPI broadcast method. Local timers allows the system
1593 accounting to be spread across the timer interval, preventing a
1594 "thundering herd" at every timer tick.
1598 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1599 default 355 if ARCH_U8500
1600 default 264 if MACH_H4700
1601 default 512 if SOC_OMAP5
1604 Maximum number of GPIOs in the system.
1606 If unsure, leave the default value.
1608 source kernel/Kconfig.preempt
1612 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1613 ARCH_S5PV210 || ARCH_EXYNOS4
1614 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1615 default AT91_TIMER_HZ if ARCH_AT91
1616 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1619 config THUMB2_KERNEL
1620 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1621 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1623 select ARM_ASM_UNIFIED
1626 By enabling this option, the kernel will be compiled in
1627 Thumb-2 mode. A compiler/assembler that understand the unified
1628 ARM-Thumb syntax is needed.
1632 config THUMB2_AVOID_R_ARM_THM_JUMP11
1633 bool "Work around buggy Thumb-2 short branch relocations in gas"
1634 depends on THUMB2_KERNEL && MODULES
1637 Various binutils versions can resolve Thumb-2 branches to
1638 locally-defined, preemptible global symbols as short-range "b.n"
1639 branch instructions.
1641 This is a problem, because there's no guarantee the final
1642 destination of the symbol, or any candidate locations for a
1643 trampoline, are within range of the branch. For this reason, the
1644 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1645 relocation in modules at all, and it makes little sense to add
1648 The symptom is that the kernel fails with an "unsupported
1649 relocation" error when loading some modules.
1651 Until fixed tools are available, passing
1652 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1653 code which hits this problem, at the cost of a bit of extra runtime
1654 stack usage in some cases.
1656 The problem is described in more detail at:
1657 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1659 Only Thumb-2 kernels are affected.
1661 Unless you are sure your tools don't have this problem, say Y.
1663 config ARM_ASM_UNIFIED
1667 bool "Use the ARM EABI to compile the kernel"
1669 This option allows for the kernel to be compiled using the latest
1670 ARM ABI (aka EABI). This is only useful if you are using a user
1671 space environment that is also compiled with EABI.
1673 Since there are major incompatibilities between the legacy ABI and
1674 EABI, especially with regard to structure member alignment, this
1675 option also changes the kernel syscall calling convention to
1676 disambiguate both ABIs and allow for backward compatibility support
1677 (selected with CONFIG_OABI_COMPAT).
1679 To use this you need GCC version 4.0.0 or later.
1682 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1683 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1686 This option preserves the old syscall interface along with the
1687 new (ARM EABI) one. It also provides a compatibility layer to
1688 intercept syscalls that have structure arguments which layout
1689 in memory differs between the legacy ABI and the new ARM EABI
1690 (only for non "thumb" binaries). This option adds a tiny
1691 overhead to all syscalls and produces a slightly larger kernel.
1692 If you know you'll be using only pure EABI user space then you
1693 can say N here. If this option is not selected and you attempt
1694 to execute a legacy ABI binary then the result will be
1695 UNPREDICTABLE (in fact it can be predicted that it won't work
1696 at all). If in doubt say Y.
1698 config ARCH_HAS_HOLES_MEMORYMODEL
1701 config ARCH_SPARSEMEM_ENABLE
1704 config ARCH_SPARSEMEM_DEFAULT
1705 def_bool ARCH_SPARSEMEM_ENABLE
1707 config ARCH_SELECT_MEMORY_MODEL
1708 def_bool ARCH_SPARSEMEM_ENABLE
1710 config HAVE_ARCH_PFN_VALID
1711 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1714 bool "High Memory Support"
1717 The address space of ARM processors is only 4 Gigabytes large
1718 and it has to accommodate user address space, kernel address
1719 space as well as some memory mapped IO. That means that, if you
1720 have a large amount of physical memory and/or IO, not all of the
1721 memory can be "permanently mapped" by the kernel. The physical
1722 memory that is not permanently mapped is called "high memory".
1724 Depending on the selected kernel/user memory split, minimum
1725 vmalloc space and actual amount of RAM, you may not need this
1726 option which should result in a slightly faster kernel.
1731 bool "Allocate 2nd-level pagetables from highmem"
1734 config HW_PERF_EVENTS
1735 bool "Enable hardware performance counter support for perf events"
1736 depends on PERF_EVENTS
1739 Enable hardware performance counter support for perf events. If
1740 disabled, perf events will use software events only.
1744 config FORCE_MAX_ZONEORDER
1745 int "Maximum zone order" if ARCH_SHMOBILE
1746 range 11 64 if ARCH_SHMOBILE
1747 default "9" if SA1111
1750 The kernel memory allocator divides physically contiguous memory
1751 blocks into "zones", where each zone is a power of two number of
1752 pages. This option selects the largest power of two that the kernel
1753 keeps in the memory allocator. If you need to allocate very large
1754 blocks of physically contiguous memory, then you may need to
1755 increase this value.
1757 This config option is actually maximum order plus one. For example,
1758 a value of 11 means that the largest free memory block is 2^10 pages.
1761 bool "Timer and CPU usage LEDs"
1762 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1763 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1764 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1765 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1766 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1767 ARCH_AT91 || ARCH_DAVINCI || \
1768 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1770 If you say Y here, the LEDs on your machine will be used
1771 to provide useful information about your current system status.
1773 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1774 be able to select which LEDs are active using the options below. If
1775 you are compiling a kernel for the EBSA-110 or the LART however, the
1776 red LED will simply flash regularly to indicate that the system is
1777 still functional. It is safe to say Y here if you have a CATS
1778 system, but the driver will do nothing.
1781 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1782 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1783 || MACH_OMAP_PERSEUS2
1785 depends on !GENERIC_CLOCKEVENTS
1786 default y if ARCH_EBSA110
1788 If you say Y here, one of the system LEDs (the green one on the
1789 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1790 will flash regularly to indicate that the system is still
1791 operational. This is mainly useful to kernel hackers who are
1792 debugging unstable kernels.
1794 The LART uses the same LED for both Timer LED and CPU usage LED
1795 functions. You may choose to use both, but the Timer LED function
1796 will overrule the CPU usage LED.
1799 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1801 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1802 || MACH_OMAP_PERSEUS2
1805 If you say Y here, the red LED will be used to give a good real
1806 time indication of CPU usage, by lighting whenever the idle task
1807 is not currently executing.
1809 The LART uses the same LED for both Timer LED and CPU usage LED
1810 functions. You may choose to use both, but the Timer LED function
1811 will overrule the CPU usage LED.
1813 config ALIGNMENT_TRAP
1815 depends on CPU_CP15_MMU
1816 default y if !ARCH_EBSA110
1817 select HAVE_PROC_CPU if PROC_FS
1819 ARM processors cannot fetch/store information which is not
1820 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1821 address divisible by 4. On 32-bit ARM processors, these non-aligned
1822 fetch/store instructions will be emulated in software if you say
1823 here, which has a severe performance impact. This is necessary for
1824 correct operation of some network protocols. With an IP-only
1825 configuration it is safe to say N, otherwise say Y.
1827 config UACCESS_WITH_MEMCPY
1828 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1829 depends on MMU && EXPERIMENTAL
1830 default y if CPU_FEROCEON
1832 Implement faster copy_to_user and clear_user methods for CPU
1833 cores where a 8-word STM instruction give significantly higher
1834 memory write throughput than a sequence of individual 32bit stores.
1836 A possible side effect is a slight increase in scheduling latency
1837 between threads sharing the same address space if they invoke
1838 such copy operations with large buffers.
1840 However, if the CPU data cache is using a write-allocate mode,
1841 this option is unlikely to provide any performance gain.
1845 prompt "Enable seccomp to safely compute untrusted bytecode"
1847 This kernel feature is useful for number crunching applications
1848 that may need to compute untrusted bytecode during their
1849 execution. By using pipes or other transports made available to
1850 the process as file descriptors supporting the read/write
1851 syscalls, it's possible to isolate those applications in
1852 their own address space using seccomp. Once seccomp is
1853 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1854 and the task is only allowed to execute a few safe syscalls
1855 defined by each seccomp mode.
1857 config CC_STACKPROTECTOR
1858 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1859 depends on EXPERIMENTAL
1861 This option turns on the -fstack-protector GCC feature. This
1862 feature puts, at the beginning of functions, a canary value on
1863 the stack just before the return address, and validates
1864 the value just before actually returning. Stack based buffer
1865 overflows (that need to overwrite this return address) now also
1866 overwrite the canary, which gets detected and the attack is then
1867 neutralized via a kernel panic.
1868 This feature requires gcc version 4.2 or above.
1870 config DEPRECATED_PARAM_STRUCT
1871 bool "Provide old way to pass kernel parameters"
1873 This was deprecated in 2001 and announced to live on for 5 years.
1874 Some old boot loaders still use this way.
1881 bool "Flattened Device Tree support"
1883 select OF_EARLY_FLATTREE
1886 Include support for flattened device tree machine descriptions.
1888 # Compressed boot loader in ROM. Yes, we really want to ask about
1889 # TEXT and BSS so we preserve their values in the config files.
1890 config ZBOOT_ROM_TEXT
1891 hex "Compressed ROM boot loader base address"
1894 The physical address at which the ROM-able zImage is to be
1895 placed in the target. Platforms which normally make use of
1896 ROM-able zImage formats normally set this to a suitable
1897 value in their defconfig file.
1899 If ZBOOT_ROM is not enabled, this has no effect.
1901 config ZBOOT_ROM_BSS
1902 hex "Compressed ROM boot loader BSS address"
1905 The base address of an area of read/write memory in the target
1906 for the ROM-able zImage which must be available while the
1907 decompressor is running. It must be large enough to hold the
1908 entire decompressed kernel plus an additional 128 KiB.
1909 Platforms which normally make use of ROM-able zImage formats
1910 normally set this to a suitable value in their defconfig file.
1912 If ZBOOT_ROM is not enabled, this has no effect.
1915 bool "Compressed boot loader in ROM/flash"
1916 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1918 Say Y here if you intend to execute your compressed kernel image
1919 (zImage) directly from ROM or flash. If unsure, say N.
1922 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1923 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1924 default ZBOOT_ROM_NONE
1926 Include experimental SD/MMC loading code in the ROM-able zImage.
1927 With this enabled it is possible to write the ROM-able zImage
1928 kernel image to an MMC or SD card and boot the kernel straight
1929 from the reset vector. At reset the processor Mask ROM will load
1930 the first part of the ROM-able zImage which in turn loads the
1931 rest the kernel image to RAM.
1933 config ZBOOT_ROM_NONE
1934 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1936 Do not load image from SD or MMC
1938 config ZBOOT_ROM_MMCIF
1939 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1941 Load image from MMCIF hardware block.
1943 config ZBOOT_ROM_SH_MOBILE_SDHI
1944 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1946 Load image from SDHI hardware block
1950 config ARM_APPENDED_DTB
1951 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1952 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1954 With this option, the boot code will look for a device tree binary
1955 (DTB) appended to zImage
1956 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1958 This is meant as a backward compatibility convenience for those
1959 systems with a bootloader that can't be upgraded to accommodate
1960 the documented boot protocol using a device tree.
1962 Beware that there is very little in terms of protection against
1963 this option being confused by leftover garbage in memory that might
1964 look like a DTB header after a reboot if no actual DTB is appended
1965 to zImage. Do not leave this option active in a production kernel
1966 if you don't intend to always append a DTB. Proper passing of the
1967 location into r2 of a bootloader provided DTB is always preferable
1970 config ARM_ATAG_DTB_COMPAT
1971 bool "Supplement the appended DTB with traditional ATAG information"
1972 depends on ARM_APPENDED_DTB
1974 Some old bootloaders can't be updated to a DTB capable one, yet
1975 they provide ATAGs with memory configuration, the ramdisk address,
1976 the kernel cmdline string, etc. Such information is dynamically
1977 provided by the bootloader and can't always be stored in a static
1978 DTB. To allow a device tree enabled kernel to be used with such
1979 bootloaders, this option allows zImage to extract the information
1980 from the ATAG list and store it at run time into the appended DTB.
1983 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1984 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1986 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1987 bool "Use bootloader kernel arguments if available"
1989 Uses the command-line options passed by the boot loader instead of
1990 the device tree bootargs property. If the boot loader doesn't provide
1991 any, the device tree bootargs property will be used.
1993 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1994 bool "Extend with bootloader kernel arguments"
1996 The command-line arguments provided by the boot loader will be
1997 appended to the the device tree bootargs property.
2002 string "Default kernel command string"
2005 On some architectures (EBSA110 and CATS), there is currently no way
2006 for the boot loader to pass arguments to the kernel. For these
2007 architectures, you should supply some command-line options at build
2008 time by entering them here. As a minimum, you should specify the
2009 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2012 prompt "Kernel command line type" if CMDLINE != ""
2013 default CMDLINE_FROM_BOOTLOADER
2015 config CMDLINE_FROM_BOOTLOADER
2016 bool "Use bootloader kernel arguments if available"
2018 Uses the command-line options passed by the boot loader. If
2019 the boot loader doesn't provide any, the default kernel command
2020 string provided in CMDLINE will be used.
2022 config CMDLINE_EXTEND
2023 bool "Extend bootloader kernel arguments"
2025 The command-line arguments provided by the boot loader will be
2026 appended to the default kernel command string.
2028 config CMDLINE_FORCE
2029 bool "Always use the default kernel command string"
2031 Always use the default kernel command string, even if the boot
2032 loader passes other arguments to the kernel.
2033 This is useful if you cannot or don't want to change the
2034 command-line options your boot loader passes to the kernel.
2038 bool "Kernel Execute-In-Place from ROM"
2039 depends on !ZBOOT_ROM && !ARM_LPAE
2041 Execute-In-Place allows the kernel to run from non-volatile storage
2042 directly addressable by the CPU, such as NOR flash. This saves RAM
2043 space since the text section of the kernel is not loaded from flash
2044 to RAM. Read-write sections, such as the data section and stack,
2045 are still copied to RAM. The XIP kernel is not compressed since
2046 it has to run directly from flash, so it will take more space to
2047 store it. The flash address used to link the kernel object files,
2048 and for storing it, is configuration dependent. Therefore, if you
2049 say Y here, you must know the proper physical address where to
2050 store the kernel image depending on your own flash memory usage.
2052 Also note that the make target becomes "make xipImage" rather than
2053 "make zImage" or "make Image". The final kernel binary to put in
2054 ROM memory will be arch/arm/boot/xipImage.
2058 config XIP_PHYS_ADDR
2059 hex "XIP Kernel Physical Location"
2060 depends on XIP_KERNEL
2061 default "0x00080000"
2063 This is the physical address in your flash memory the kernel will
2064 be linked for and stored to. This address is dependent on your
2068 bool "Kexec system call (EXPERIMENTAL)"
2069 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2071 kexec is a system call that implements the ability to shutdown your
2072 current kernel, and to start another kernel. It is like a reboot
2073 but it is independent of the system firmware. And like a reboot
2074 you can start any kernel with it, not just Linux.
2076 It is an ongoing process to be certain the hardware in a machine
2077 is properly shutdown, so do not be surprised if this code does not
2078 initially work for you. It may help to enable device hotplugging
2082 bool "Export atags in procfs"
2086 Should the atags used to boot the kernel be exported in an "atags"
2087 file in procfs. Useful with kexec.
2090 bool "Build kdump crash kernel (EXPERIMENTAL)"
2091 depends on EXPERIMENTAL
2093 Generate crash dump after being started by kexec. This should
2094 be normally only set in special crash dump kernels which are
2095 loaded in the main kernel with kexec-tools into a specially
2096 reserved region and then later executed after a crash by
2097 kdump/kexec. The crash dump kernel must be compiled to a
2098 memory address not used by the main kernel
2100 For more details see Documentation/kdump/kdump.txt
2102 config AUTO_ZRELADDR
2103 bool "Auto calculation of the decompressed kernel image address"
2104 depends on !ZBOOT_ROM && !ARCH_U300
2106 ZRELADDR is the physical address where the decompressed kernel
2107 image will be placed. If AUTO_ZRELADDR is selected, the address
2108 will be determined at run-time by masking the current IP with
2109 0xf8000000. This assumes the zImage being placed in the first 128MB
2110 from start of memory.
2114 menu "CPU Power Management"
2118 source "drivers/cpufreq/Kconfig"
2121 tristate "CPUfreq driver for i.MX CPUs"
2122 depends on ARCH_MXC && CPU_FREQ
2123 select CPU_FREQ_TABLE
2125 This enables the CPUfreq driver for i.MX CPUs.
2127 config CPU_FREQ_SA1100
2130 config CPU_FREQ_SA1110
2133 config CPU_FREQ_INTEGRATOR
2134 tristate "CPUfreq driver for ARM Integrator CPUs"
2135 depends on ARCH_INTEGRATOR && CPU_FREQ
2138 This enables the CPUfreq driver for ARM Integrator CPUs.
2140 For details, take a look at <file:Documentation/cpu-freq>.
2146 depends on CPU_FREQ && ARCH_PXA && PXA25x
2148 select CPU_FREQ_TABLE
2149 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2154 Internal configuration node for common cpufreq on Samsung SoC
2156 config CPU_FREQ_S3C24XX
2157 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2158 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2161 This enables the CPUfreq driver for the Samsung S3C24XX family
2164 For details, take a look at <file:Documentation/cpu-freq>.
2168 config CPU_FREQ_S3C24XX_PLL
2169 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2170 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2172 Compile in support for changing the PLL frequency from the
2173 S3C24XX series CPUfreq driver. The PLL takes time to settle
2174 after a frequency change, so by default it is not enabled.
2176 This also means that the PLL tables for the selected CPU(s) will
2177 be built which may increase the size of the kernel image.
2179 config CPU_FREQ_S3C24XX_DEBUG
2180 bool "Debug CPUfreq Samsung driver core"
2181 depends on CPU_FREQ_S3C24XX
2183 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2185 config CPU_FREQ_S3C24XX_IODEBUG
2186 bool "Debug CPUfreq Samsung driver IO timing"
2187 depends on CPU_FREQ_S3C24XX
2189 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2191 config CPU_FREQ_S3C24XX_DEBUGFS
2192 bool "Export debugfs for CPUFreq"
2193 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2195 Export status information via debugfs.
2199 source "drivers/cpuidle/Kconfig"
2203 menu "Floating point emulation"
2205 comment "At least one emulation must be selected"
2208 bool "NWFPE math emulation"
2209 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2211 Say Y to include the NWFPE floating point emulator in the kernel.
2212 This is necessary to run most binaries. Linux does not currently
2213 support floating point hardware so you need to say Y here even if
2214 your machine has an FPA or floating point co-processor podule.
2216 You may say N here if you are going to load the Acorn FPEmulator
2217 early in the bootup.
2220 bool "Support extended precision"
2221 depends on FPE_NWFPE
2223 Say Y to include 80-bit support in the kernel floating-point
2224 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2225 Note that gcc does not generate 80-bit operations by default,
2226 so in most cases this option only enlarges the size of the
2227 floating point emulator without any good reason.
2229 You almost surely want to say N here.
2232 bool "FastFPE math emulation (EXPERIMENTAL)"
2233 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2235 Say Y here to include the FAST floating point emulator in the kernel.
2236 This is an experimental much faster emulator which now also has full
2237 precision for the mantissa. It does not support any exceptions.
2238 It is very simple, and approximately 3-6 times faster than NWFPE.
2240 It should be sufficient for most programs. It may be not suitable
2241 for scientific calculations, but you have to check this for yourself.
2242 If you do not feel you need a faster FP emulation you should better
2246 bool "VFP-format floating point maths"
2247 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2249 Say Y to include VFP support code in the kernel. This is needed
2250 if your hardware includes a VFP unit.
2252 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2253 release notes and additional status information.
2255 Say N if your target does not have VFP hardware.
2263 bool "Advanced SIMD (NEON) Extension support"
2264 depends on VFPv3 && CPU_V7
2266 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2271 menu "Userspace binary formats"
2273 source "fs/Kconfig.binfmt"
2276 tristate "RISC OS personality"
2279 Say Y here to include the kernel code necessary if you want to run
2280 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2281 experimental; if this sounds frightening, say N and sleep in peace.
2282 You can also say M here to compile this support as a module (which
2283 will be called arthur).
2287 menu "Power management options"
2289 source "kernel/power/Kconfig"
2291 config ARCH_SUSPEND_POSSIBLE
2292 depends on !ARCH_S5PC100
2293 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2294 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2297 config ARM_CPU_SUSPEND
2302 source "net/Kconfig"
2304 source "drivers/Kconfig"
2308 source "arch/arm/Kconfig.debug"
2310 source "security/Kconfig"
2312 source "crypto/Kconfig"
2314 source "lib/Kconfig"