4 select ARCH_HAVE_CUSTOM_GPIO_H
6 select HAVE_DMA_API_DEBUG
7 select HAVE_IDE if PCI || ISA || PCMCIA
9 select HAVE_DMA_CONTIGUOUS if MMU
12 select SYS_SUPPORTS_APM_EMULATION
13 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
14 select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
15 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
16 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
18 select HAVE_ARCH_TRACEHOOK
19 select HAVE_KPROBES if !XIP_KERNEL
20 select HAVE_KRETPROBES if (HAVE_KPROBES)
21 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
22 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
23 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
24 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
25 select ARCH_BINFMT_ELF_RANDOMIZE_PIE
26 select HAVE_GENERIC_DMA_COHERENT
27 select HAVE_KERNEL_GZIP
28 select HAVE_KERNEL_LZO
29 select HAVE_KERNEL_LZMA
32 select HAVE_PERF_EVENTS
33 select PERF_USE_VMALLOC
34 select HAVE_REGS_AND_STACK_ACCESS_API
35 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
36 select HAVE_C_RECORDMCOUNT
37 select HAVE_GENERIC_HARDIRQS
38 select HARDIRQS_SW_RESEND
39 select GENERIC_IRQ_PROBE
40 select GENERIC_IRQ_SHOW
41 select ARCH_WANT_IPC_PARSE_VERSION
42 select HARDIRQS_SW_RESEND
43 select CPU_PM if (SUSPEND || CPU_IDLE)
44 select GENERIC_PCI_IOMAP
46 select GENERIC_SMP_IDLE_THREAD
48 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
49 select GENERIC_STRNCPY_FROM_USER
50 select GENERIC_STRNLEN_USER
51 select DCACHE_WORD_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && !CPU_BIG_ENDIAN
53 The ARM series is a line of low-power-consumption RISC chip designs
54 licensed by ARM Ltd and targeted at embedded applications and
55 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
56 manufactured, but legacy ARM-based PC hardware remains popular in
57 Europe. There is an ARM Linux project with a web page at
58 <http://www.arm.linux.org.uk/>.
60 config ARM_HAS_SG_CHAIN
63 config NEED_SG_DMA_LENGTH
66 config ARM_DMA_USE_IOMMU
67 select NEED_SG_DMA_LENGTH
68 select ARM_HAS_SG_CHAIN
77 config SYS_SUPPORTS_APM_EMULATION
85 select GENERIC_ALLOCATOR
96 The Extended Industry Standard Architecture (EISA) bus was
97 developed as an open alternative to the IBM MicroChannel bus.
99 The EISA bus provided some of the features of the IBM MicroChannel
100 bus while maintaining backward compatibility with cards made for
101 the older ISA bus. The EISA bus saw limited use between 1988 and
102 1995 when it was made obsolete by the PCI bus.
104 Say Y here if you are building a kernel for an EISA-based machine.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config RWSEM_GENERIC_SPINLOCK
132 config RWSEM_XCHGADD_ALGORITHM
135 config ARCH_HAS_ILOG2_U32
138 config ARCH_HAS_ILOG2_U64
141 config ARCH_HAS_CPUFREQ
144 Internal node to signify that the ARCH has CPUFREQ support
145 and that the relevant menu configurations are displayed for
148 config GENERIC_HWEIGHT
152 config GENERIC_CALIBRATE_DELAY
156 config ARCH_MAY_HAVE_PC_FDC
162 config NEED_DMA_MAP_STATE
165 config ARCH_HAS_DMA_SET_COHERENT_MASK
168 config GENERIC_ISA_DMA
174 config NEED_RET_TO_USER
182 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
183 default DRAM_BASE if REMAP_VECTORS_TO_RAM
186 The base address of exception vectors.
188 config ARM_PATCH_PHYS_VIRT
189 bool "Patch physical to virtual translations at runtime" if EMBEDDED
191 depends on !XIP_KERNEL && MMU
192 depends on !ARCH_REALVIEW || !SPARSEMEM
194 Patch phys-to-virt and virt-to-phys translation functions at
195 boot and module load time according to the position of the
196 kernel in system memory.
198 This can only be used with non-XIP MMU kernels where the base
199 of physical memory is at a 16MB boundary.
201 Only disable this option if you know that you do not require
202 this feature (eg, building a kernel for a single machine) and
203 you need to shrink the kernel to the minimal size.
205 config NEED_MACH_IO_H
208 Select this when mach/io.h is required to provide special
209 definitions for this platform. The need for mach/io.h should
210 be avoided when possible.
212 config NEED_MACH_MEMORY_H
215 Select this when mach/memory.h is required to provide special
216 definitions for this platform. The need for mach/memory.h should
217 be avoided when possible.
220 hex "Physical address of main memory" if MMU
221 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
222 default DRAM_BASE if !MMU
224 Please provide the physical address corresponding to the
225 location of main memory in your system.
231 source "init/Kconfig"
233 source "kernel/Kconfig.freezer"
238 bool "MMU-based Paged Memory Management Support"
241 Select if you want MMU-based virtualised addressing space
242 support by paged memory management. If unsure, say 'Y'.
245 # The "ARM system type" choice list is ordered alphabetically by option
246 # text. Please add new entries in the option alphabetic order.
249 prompt "ARM system type"
250 default ARCH_VERSATILE
253 bool "Altera SOCFPGA family"
254 select ARCH_WANT_OPTIONAL_GPIOLIB
262 select DW_APB_TIMER_OF
263 select GENERIC_CLOCKEVENTS
264 select GPIO_PL061 if GPIOLIB
269 This enables support for Altera SOCFPGA Cyclone V platform
271 config ARCH_INTEGRATOR
272 bool "ARM Ltd. Integrator family"
274 select ARCH_HAS_CPUFREQ
276 select COMMON_CLK_VERSATILE
279 select GENERIC_CLOCKEVENTS
280 select PLAT_VERSATILE
281 select PLAT_VERSATILE_FPGA_IRQ
282 select NEED_MACH_MEMORY_H
284 select MULTI_IRQ_HANDLER
286 Support for ARM's Integrator platform.
289 bool "ARM Ltd. RealView family"
292 select COMMON_CLK_VERSATILE
294 select GENERIC_CLOCKEVENTS
295 select ARCH_WANT_OPTIONAL_GPIOLIB
296 select PLAT_VERSATILE
297 select PLAT_VERSATILE_CLCD
298 select ARM_TIMER_SP804
299 select GPIO_PL061 if GPIOLIB
300 select NEED_MACH_MEMORY_H
302 This enables support for ARM Ltd RealView boards.
304 config ARCH_VERSATILE
305 bool "ARM Ltd. Versatile family"
309 select HAVE_MACH_CLKDEV
311 select GENERIC_CLOCKEVENTS
312 select ARCH_WANT_OPTIONAL_GPIOLIB
313 select PLAT_VERSATILE
314 select PLAT_VERSATILE_CLOCK
315 select PLAT_VERSATILE_CLCD
316 select PLAT_VERSATILE_FPGA_IRQ
317 select ARM_TIMER_SP804
319 This enables support for ARM Ltd Versatile board.
322 bool "ARM Ltd. Versatile Express family"
323 select ARCH_WANT_OPTIONAL_GPIOLIB
325 select ARM_TIMER_SP804
328 select GENERIC_CLOCKEVENTS
330 select HAVE_PATA_PLATFORM
333 select PLAT_VERSATILE
334 select PLAT_VERSATILE_CLCD
335 select REGULATOR_FIXED_VOLTAGE if REGULATOR
337 This enables support for the ARM Ltd Versatile Express boards.
341 select ARCH_REQUIRE_GPIOLIB
345 select NEED_MACH_IO_H if PCCARD
347 This enables support for systems based on Atmel
348 AT91RM9200 and AT91SAM9* processors.
351 bool "Broadcom BCM2835 family"
352 select ARCH_WANT_OPTIONAL_GPIOLIB
354 select ARM_ERRATA_411920
355 select ARM_TIMER_SP804
359 select GENERIC_CLOCKEVENTS
360 select MULTI_IRQ_HANDLER
364 This enables support for the Broadcom BCM2835 SoC. This SoC is
365 use in the Raspberry Pi, and Roku 2 devices.
368 bool "Broadcom BCMRING"
372 select ARM_TIMER_SP804
374 select GENERIC_CLOCKEVENTS
375 select ARCH_WANT_OPTIONAL_GPIOLIB
377 Support for Broadcom's BCMRing platform.
380 bool "Calxeda Highbank-based"
381 select ARCH_WANT_OPTIONAL_GPIOLIB
384 select ARM_TIMER_SP804
389 select GENERIC_CLOCKEVENTS
395 Support for the Calxeda Highbank SoC based boards.
398 bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
400 select ARCH_USES_GETTIMEOFFSET
401 select NEED_MACH_MEMORY_H
403 Support for Cirrus Logic 711x/721x/731x based boards.
406 bool "Cavium Networks CNS3XXX family"
408 select GENERIC_CLOCKEVENTS
410 select MIGHT_HAVE_CACHE_L2X0
411 select MIGHT_HAVE_PCI
412 select PCI_DOMAINS if PCI
414 Support for Cavium Networks CNS3XXX platform.
417 bool "Cortina Systems Gemini"
419 select ARCH_REQUIRE_GPIOLIB
420 select ARCH_USES_GETTIMEOFFSET
422 Support for the Cortina Systems Gemini family SoCs
427 select ARCH_REQUIRE_GPIOLIB
428 select GENERIC_CLOCKEVENTS
430 select GENERIC_IRQ_CHIP
431 select MIGHT_HAVE_CACHE_L2X0
436 Support for CSR SiRFprimaII/Marco/Polo platforms
443 select ARCH_USES_GETTIMEOFFSET
444 select NEED_MACH_IO_H
445 select NEED_MACH_MEMORY_H
447 This is an evaluation board for the StrongARM processor available
448 from Digital. It has limited hardware on-board, including an
449 Ethernet interface, two PCMCIA sockets, two serial ports and a
458 select ARCH_REQUIRE_GPIOLIB
459 select ARCH_HAS_HOLES_MEMORYMODEL
460 select ARCH_USES_GETTIMEOFFSET
461 select NEED_MACH_MEMORY_H
463 This enables support for the Cirrus EP93xx series of CPUs.
465 config ARCH_FOOTBRIDGE
469 select GENERIC_CLOCKEVENTS
471 select NEED_MACH_IO_H if !MMU
472 select NEED_MACH_MEMORY_H
474 Support for systems based on the DC21285 companion chip
475 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
478 bool "Freescale MXC/iMX-based"
479 select GENERIC_CLOCKEVENTS
480 select ARCH_REQUIRE_GPIOLIB
483 select GENERIC_IRQ_CHIP
484 select MULTI_IRQ_HANDLER
488 Support for Freescale MXC/iMX-based family of processors
491 bool "Freescale MXS-based"
492 select GENERIC_CLOCKEVENTS
493 select ARCH_REQUIRE_GPIOLIB
497 select HAVE_CLK_PREPARE
501 Support for Freescale MXS-based family of processors
504 bool "Hilscher NetX based"
508 select GENERIC_CLOCKEVENTS
510 This enables support for systems based on the Hilscher NetX Soc
513 bool "Hynix HMS720x-based"
516 select ARCH_USES_GETTIMEOFFSET
518 This enables support for systems based on the Hynix HMS720x
526 select ARCH_SUPPORTS_MSI
528 select NEED_MACH_MEMORY_H
529 select NEED_RET_TO_USER
531 Support for Intel's IOP13XX (XScale) family of processors.
537 select NEED_RET_TO_USER
540 select ARCH_REQUIRE_GPIOLIB
542 Support for Intel's 80219 and IOP32X (XScale) family of
549 select NEED_RET_TO_USER
552 select ARCH_REQUIRE_GPIOLIB
554 Support for Intel's IOP33X (XScale) family of processors.
559 select ARCH_HAS_DMA_SET_COHERENT_MASK
562 select ARCH_REQUIRE_GPIOLIB
563 select GENERIC_CLOCKEVENTS
564 select MIGHT_HAVE_PCI
565 select NEED_MACH_IO_H
566 select DMABOUNCE if PCI
568 Support for Intel's IXP4XX (XScale) family of processors.
571 bool "Marvell SOCs with Device Tree support"
572 select GENERIC_CLOCKEVENTS
573 select MULTI_IRQ_HANDLER
576 select GENERIC_IRQ_CHIP
580 Support for the Marvell SoC Family with device tree support
586 select ARCH_REQUIRE_GPIOLIB
587 select GENERIC_CLOCKEVENTS
590 Support for the Marvell Dove SoC 88AP510
593 bool "Marvell Kirkwood"
596 select ARCH_REQUIRE_GPIOLIB
597 select GENERIC_CLOCKEVENTS
600 Support for the following Marvell Kirkwood series SoCs:
601 88F6180, 88F6192 and 88F6281.
607 select ARCH_REQUIRE_GPIOLIB
610 select USB_ARCH_HAS_OHCI
612 select GENERIC_CLOCKEVENTS
616 Support for the NXP LPC32XX family of processors
619 bool "Marvell MV78xx0"
622 select ARCH_REQUIRE_GPIOLIB
623 select GENERIC_CLOCKEVENTS
626 Support for the following Marvell MV78xx0 series SoCs:
634 select ARCH_REQUIRE_GPIOLIB
635 select GENERIC_CLOCKEVENTS
638 Support for the following Marvell Orion 5x series SoCs:
639 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
640 Orion-2 (5281), Orion-1-90 (6183).
643 bool "Marvell PXA168/910/MMP2"
645 select ARCH_REQUIRE_GPIOLIB
647 select GENERIC_CLOCKEVENTS
652 select GENERIC_ALLOCATOR
654 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
657 bool "Micrel/Kendin KS8695"
659 select ARCH_REQUIRE_GPIOLIB
660 select NEED_MACH_MEMORY_H
662 select GENERIC_CLOCKEVENTS
664 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
665 System-on-Chip devices.
668 bool "Nuvoton W90X900 CPU"
670 select ARCH_REQUIRE_GPIOLIB
673 select GENERIC_CLOCKEVENTS
675 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
676 At present, the w90x900 has been renamed nuc900, regarding
677 the ARM series product line, you can login the following
678 link address to know more.
680 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
681 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
687 select GENERIC_CLOCKEVENTS
691 select MIGHT_HAVE_CACHE_L2X0
692 select ARCH_HAS_CPUFREQ
696 This enables support for NVIDIA Tegra based systems (Tegra APX,
697 Tegra 6xx and Tegra 2 series).
699 config ARCH_PICOXCELL
700 bool "Picochip picoXcell"
701 select ARCH_REQUIRE_GPIOLIB
702 select ARM_PATCH_PHYS_VIRT
706 select DW_APB_TIMER_OF
707 select GENERIC_CLOCKEVENTS
714 This enables support for systems based on the Picochip picoXcell
715 family of Femtocell devices. The picoxcell support requires device tree
719 bool "PXA2xx/PXA3xx-based"
722 select ARCH_HAS_CPUFREQ
725 select ARCH_REQUIRE_GPIOLIB
726 select GENERIC_CLOCKEVENTS
731 select MULTI_IRQ_HANDLER
732 select ARM_CPU_SUSPEND if PM
735 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
740 select GENERIC_CLOCKEVENTS
741 select ARCH_REQUIRE_GPIOLIB
744 Support for Qualcomm MSM/QSD based systems. This runs on the
745 apps processor of the MSM/QSD and depends on a shared memory
746 interface to the modem processor which runs the baseband
747 stack and controls some vital subsystems
748 (clock and power control, etc).
751 bool "Renesas SH-Mobile / R-Mobile"
754 select HAVE_MACH_CLKDEV
756 select GENERIC_CLOCKEVENTS
757 select MIGHT_HAVE_CACHE_L2X0
760 select MULTI_IRQ_HANDLER
761 select PM_GENERIC_DOMAINS if PM
762 select NEED_MACH_MEMORY_H
764 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
770 select ARCH_MAY_HAVE_PC_FDC
771 select HAVE_PATA_PLATFORM
774 select ARCH_SPARSEMEM_ENABLE
775 select ARCH_USES_GETTIMEOFFSET
777 select NEED_MACH_IO_H
778 select NEED_MACH_MEMORY_H
780 On the Acorn Risc-PC, Linux can support the internal IDE disk and
781 CD-ROM interface, serial and parallel port, and the floppy drive.
788 select ARCH_SPARSEMEM_ENABLE
790 select ARCH_HAS_CPUFREQ
792 select GENERIC_CLOCKEVENTS
794 select ARCH_REQUIRE_GPIOLIB
796 select NEED_MACH_MEMORY_H
799 Support for StrongARM 11x0 based boards.
802 bool "Samsung S3C24XX SoCs"
804 select ARCH_HAS_CPUFREQ
807 select ARCH_USES_GETTIMEOFFSET
808 select HAVE_S3C2410_I2C if I2C
809 select HAVE_S3C_RTC if RTC_CLASS
810 select HAVE_S3C2410_WATCHDOG if WATCHDOG
811 select NEED_MACH_IO_H
813 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
814 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
815 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
816 Samsung SMDK2410 development board (and derivatives).
819 bool "Samsung S3C64XX"
827 select ARCH_USES_GETTIMEOFFSET
828 select ARCH_HAS_CPUFREQ
829 select ARCH_REQUIRE_GPIOLIB
830 select SAMSUNG_CLKSRC
831 select SAMSUNG_IRQ_VIC_TIMER
832 select S3C_GPIO_TRACK
834 select USB_ARCH_HAS_OHCI
835 select SAMSUNG_GPIOLIB_4BIT
836 select HAVE_S3C2410_I2C if I2C
837 select HAVE_S3C2410_WATCHDOG if WATCHDOG
839 Samsung S3C64XX series based systems
842 bool "Samsung S5P6440 S5P6450"
848 select HAVE_S3C2410_WATCHDOG if WATCHDOG
849 select GENERIC_CLOCKEVENTS
850 select HAVE_S3C2410_I2C if I2C
851 select HAVE_S3C_RTC if RTC_CLASS
853 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
857 bool "Samsung S5PC100"
862 select ARCH_USES_GETTIMEOFFSET
863 select HAVE_S3C2410_I2C if I2C
864 select HAVE_S3C_RTC if RTC_CLASS
865 select HAVE_S3C2410_WATCHDOG if WATCHDOG
867 Samsung S5PC100 series based systems
870 bool "Samsung S5PV210/S5PC110"
872 select ARCH_SPARSEMEM_ENABLE
873 select ARCH_HAS_HOLES_MEMORYMODEL
878 select ARCH_HAS_CPUFREQ
879 select GENERIC_CLOCKEVENTS
880 select HAVE_S3C2410_I2C if I2C
881 select HAVE_S3C_RTC if RTC_CLASS
882 select HAVE_S3C2410_WATCHDOG if WATCHDOG
883 select NEED_MACH_MEMORY_H
885 Samsung S5PV210/S5PC110 series based systems
888 bool "SAMSUNG EXYNOS"
890 select ARCH_SPARSEMEM_ENABLE
891 select ARCH_HAS_HOLES_MEMORYMODEL
895 select ARCH_HAS_CPUFREQ
896 select GENERIC_CLOCKEVENTS
897 select HAVE_S3C_RTC if RTC_CLASS
898 select HAVE_S3C2410_I2C if I2C
899 select HAVE_S3C2410_WATCHDOG if WATCHDOG
900 select NEED_MACH_MEMORY_H
902 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
911 select ARCH_USES_GETTIMEOFFSET
912 select NEED_MACH_MEMORY_H
914 Support for the StrongARM based Digital DNARD machine, also known
915 as "Shark" (<http://www.shark-linux.de/shark.html>).
918 bool "ST-Ericsson U300 Series"
924 select ARM_PATCH_PHYS_VIRT
926 select GENERIC_CLOCKEVENTS
930 select ARCH_REQUIRE_GPIOLIB
933 Support for ST-Ericsson U300 series mobile platforms.
936 bool "ST-Ericsson U8500 Series"
940 select GENERIC_CLOCKEVENTS
942 select ARCH_REQUIRE_GPIOLIB
943 select ARCH_HAS_CPUFREQ
945 select MIGHT_HAVE_CACHE_L2X0
947 Support for ST-Ericsson's Ux500 architecture
950 bool "STMicroelectronics Nomadik"
955 select GENERIC_CLOCKEVENTS
957 select MIGHT_HAVE_CACHE_L2X0
958 select ARCH_REQUIRE_GPIOLIB
960 Support for the Nomadik platform by ST-Ericsson
964 select GENERIC_CLOCKEVENTS
965 select ARCH_REQUIRE_GPIOLIB
969 select GENERIC_ALLOCATOR
970 select GENERIC_IRQ_CHIP
971 select ARCH_HAS_HOLES_MEMORYMODEL
973 Support for TI's DaVinci platform.
979 select ARCH_REQUIRE_GPIOLIB
980 select ARCH_HAS_CPUFREQ
982 select GENERIC_CLOCKEVENTS
983 select ARCH_HAS_HOLES_MEMORYMODEL
985 Support for TI's OMAP platform (OMAP1/2/3/4).
990 select ARCH_REQUIRE_GPIOLIB
994 select GENERIC_CLOCKEVENTS
997 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
1000 bool "VIA/WonderMedia 85xx"
1003 select ARCH_HAS_CPUFREQ
1004 select GENERIC_CLOCKEVENTS
1005 select ARCH_REQUIRE_GPIOLIB
1009 select CLKDEV_LOOKUP
1011 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
1014 bool "Xilinx Zynq ARM Cortex A9 Platform"
1016 select GENERIC_CLOCKEVENTS
1017 select CLKDEV_LOOKUP
1021 select MIGHT_HAVE_CACHE_L2X0
1024 Support for Xilinx Zynq ARM Cortex A9 Platform
1028 # This is sorted alphabetically by mach-* pathname. However, plat-*
1029 # Kconfigs may be included either alphabetically (according to the
1030 # plat- suffix) or along side the corresponding mach-* source.
1032 source "arch/arm/mach-mvebu/Kconfig"
1034 source "arch/arm/mach-at91/Kconfig"
1036 source "arch/arm/mach-bcmring/Kconfig"
1038 source "arch/arm/mach-clps711x/Kconfig"
1040 source "arch/arm/mach-cns3xxx/Kconfig"
1042 source "arch/arm/mach-davinci/Kconfig"
1044 source "arch/arm/mach-dove/Kconfig"
1046 source "arch/arm/mach-ep93xx/Kconfig"
1048 source "arch/arm/mach-footbridge/Kconfig"
1050 source "arch/arm/mach-gemini/Kconfig"
1052 source "arch/arm/mach-h720x/Kconfig"
1054 source "arch/arm/mach-integrator/Kconfig"
1056 source "arch/arm/mach-iop32x/Kconfig"
1058 source "arch/arm/mach-iop33x/Kconfig"
1060 source "arch/arm/mach-iop13xx/Kconfig"
1062 source "arch/arm/mach-ixp4xx/Kconfig"
1064 source "arch/arm/mach-kirkwood/Kconfig"
1066 source "arch/arm/mach-ks8695/Kconfig"
1068 source "arch/arm/mach-msm/Kconfig"
1070 source "arch/arm/mach-mv78xx0/Kconfig"
1072 source "arch/arm/plat-mxc/Kconfig"
1074 source "arch/arm/mach-mxs/Kconfig"
1076 source "arch/arm/mach-netx/Kconfig"
1078 source "arch/arm/mach-nomadik/Kconfig"
1079 source "arch/arm/plat-nomadik/Kconfig"
1081 source "arch/arm/plat-omap/Kconfig"
1083 source "arch/arm/mach-omap1/Kconfig"
1085 source "arch/arm/mach-omap2/Kconfig"
1087 source "arch/arm/mach-orion5x/Kconfig"
1089 source "arch/arm/mach-pxa/Kconfig"
1090 source "arch/arm/plat-pxa/Kconfig"
1092 source "arch/arm/mach-mmp/Kconfig"
1094 source "arch/arm/mach-realview/Kconfig"
1096 source "arch/arm/mach-sa1100/Kconfig"
1098 source "arch/arm/plat-samsung/Kconfig"
1099 source "arch/arm/plat-s3c24xx/Kconfig"
1101 source "arch/arm/plat-spear/Kconfig"
1103 source "arch/arm/mach-s3c24xx/Kconfig"
1105 source "arch/arm/mach-s3c2412/Kconfig"
1106 source "arch/arm/mach-s3c2440/Kconfig"
1110 source "arch/arm/mach-s3c64xx/Kconfig"
1113 source "arch/arm/mach-s5p64x0/Kconfig"
1115 source "arch/arm/mach-s5pc100/Kconfig"
1117 source "arch/arm/mach-s5pv210/Kconfig"
1119 source "arch/arm/mach-exynos/Kconfig"
1121 source "arch/arm/mach-shmobile/Kconfig"
1123 source "arch/arm/mach-prima2/Kconfig"
1125 source "arch/arm/mach-tegra/Kconfig"
1127 source "arch/arm/mach-u300/Kconfig"
1129 source "arch/arm/mach-ux500/Kconfig"
1131 source "arch/arm/mach-versatile/Kconfig"
1133 source "arch/arm/mach-vexpress/Kconfig"
1134 source "arch/arm/plat-versatile/Kconfig"
1136 source "arch/arm/mach-w90x900/Kconfig"
1138 # Definitions to make life easier
1144 select GENERIC_CLOCKEVENTS
1149 select GENERIC_IRQ_CHIP
1156 config PLAT_VERSATILE
1159 config ARM_TIMER_SP804
1162 select HAVE_SCHED_CLOCK
1164 source arch/arm/mm/Kconfig
1168 default 16 if ARCH_EP93XX
1172 bool "Enable iWMMXt support"
1173 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1174 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1176 Enable support for iWMMXt context switching at run time if
1177 running on a CPU that supports it.
1181 depends on CPU_XSCALE
1184 config MULTI_IRQ_HANDLER
1187 Allow each machine to specify it's own IRQ handler at run time.
1190 source "arch/arm/Kconfig-nommu"
1193 config ARM_ERRATA_326103
1194 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1197 Executing a SWP instruction to read-only memory does not set bit 11
1198 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1199 treat the access as a read, preventing a COW from occurring and
1200 causing the faulting task to livelock.
1202 config ARM_ERRATA_411920
1203 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1204 depends on CPU_V6 || CPU_V6K
1206 Invalidation of the Instruction Cache operation can
1207 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1208 It does not affect the MPCore. This option enables the ARM Ltd.
1209 recommended workaround.
1211 config ARM_ERRATA_430973
1212 bool "ARM errata: Stale prediction on replaced interworking branch"
1215 This option enables the workaround for the 430973 Cortex-A8
1216 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1217 interworking branch is replaced with another code sequence at the
1218 same virtual address, whether due to self-modifying code or virtual
1219 to physical address re-mapping, Cortex-A8 does not recover from the
1220 stale interworking branch prediction. This results in Cortex-A8
1221 executing the new code sequence in the incorrect ARM or Thumb state.
1222 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1223 and also flushes the branch target cache at every context switch.
1224 Note that setting specific bits in the ACTLR register may not be
1225 available in non-secure mode.
1227 config ARM_ERRATA_458693
1228 bool "ARM errata: Processor deadlock when a false hazard is created"
1231 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1232 erratum. For very specific sequences of memory operations, it is
1233 possible for a hazard condition intended for a cache line to instead
1234 be incorrectly associated with a different cache line. This false
1235 hazard might then cause a processor deadlock. The workaround enables
1236 the L1 caching of the NEON accesses and disables the PLD instruction
1237 in the ACTLR register. Note that setting specific bits in the ACTLR
1238 register may not be available in non-secure mode.
1240 config ARM_ERRATA_460075
1241 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1244 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1245 erratum. Any asynchronous access to the L2 cache may encounter a
1246 situation in which recent store transactions to the L2 cache are lost
1247 and overwritten with stale memory contents from external memory. The
1248 workaround disables the write-allocate mode for the L2 cache via the
1249 ACTLR register. Note that setting specific bits in the ACTLR register
1250 may not be available in non-secure mode.
1252 config ARM_ERRATA_742230
1253 bool "ARM errata: DMB operation may be faulty"
1254 depends on CPU_V7 && SMP
1256 This option enables the workaround for the 742230 Cortex-A9
1257 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1258 between two write operations may not ensure the correct visibility
1259 ordering of the two writes. This workaround sets a specific bit in
1260 the diagnostic register of the Cortex-A9 which causes the DMB
1261 instruction to behave as a DSB, ensuring the correct behaviour of
1264 config ARM_ERRATA_742231
1265 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1266 depends on CPU_V7 && SMP
1268 This option enables the workaround for the 742231 Cortex-A9
1269 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1270 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1271 accessing some data located in the same cache line, may get corrupted
1272 data due to bad handling of the address hazard when the line gets
1273 replaced from one of the CPUs at the same time as another CPU is
1274 accessing it. This workaround sets specific bits in the diagnostic
1275 register of the Cortex-A9 which reduces the linefill issuing
1276 capabilities of the processor.
1278 config PL310_ERRATA_588369
1279 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1280 depends on CACHE_L2X0
1282 The PL310 L2 cache controller implements three types of Clean &
1283 Invalidate maintenance operations: by Physical Address
1284 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1285 They are architecturally defined to behave as the execution of a
1286 clean operation followed immediately by an invalidate operation,
1287 both performing to the same memory location. This functionality
1288 is not correctly implemented in PL310 as clean lines are not
1289 invalidated as a result of these operations.
1291 config ARM_ERRATA_720789
1292 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1295 This option enables the workaround for the 720789 Cortex-A9 (prior to
1296 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1297 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1298 As a consequence of this erratum, some TLB entries which should be
1299 invalidated are not, resulting in an incoherency in the system page
1300 tables. The workaround changes the TLB flushing routines to invalidate
1301 entries regardless of the ASID.
1303 config PL310_ERRATA_727915
1304 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1305 depends on CACHE_L2X0
1307 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1308 operation (offset 0x7FC). This operation runs in background so that
1309 PL310 can handle normal accesses while it is in progress. Under very
1310 rare circumstances, due to this erratum, write data can be lost when
1311 PL310 treats a cacheable write transaction during a Clean &
1312 Invalidate by Way operation.
1314 config ARM_ERRATA_743622
1315 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1318 This option enables the workaround for the 743622 Cortex-A9
1319 (r2p*) erratum. Under very rare conditions, a faulty
1320 optimisation in the Cortex-A9 Store Buffer may lead to data
1321 corruption. This workaround sets a specific bit in the diagnostic
1322 register of the Cortex-A9 which disables the Store Buffer
1323 optimisation, preventing the defect from occurring. This has no
1324 visible impact on the overall performance or power consumption of the
1327 config ARM_ERRATA_751472
1328 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1331 This option enables the workaround for the 751472 Cortex-A9 (prior
1332 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1333 completion of a following broadcasted operation if the second
1334 operation is received by a CPU before the ICIALLUIS has completed,
1335 potentially leading to corrupted entries in the cache or TLB.
1337 config PL310_ERRATA_753970
1338 bool "PL310 errata: cache sync operation may be faulty"
1339 depends on CACHE_PL310
1341 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1343 Under some condition the effect of cache sync operation on
1344 the store buffer still remains when the operation completes.
1345 This means that the store buffer is always asked to drain and
1346 this prevents it from merging any further writes. The workaround
1347 is to replace the normal offset of cache sync operation (0x730)
1348 by another offset targeting an unmapped PL310 register 0x740.
1349 This has the same effect as the cache sync operation: store buffer
1350 drain and waiting for all buffers empty.
1352 config ARM_ERRATA_754322
1353 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1356 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1357 r3p*) erratum. A speculative memory access may cause a page table walk
1358 which starts prior to an ASID switch but completes afterwards. This
1359 can populate the micro-TLB with a stale entry which may be hit with
1360 the new ASID. This workaround places two dsb instructions in the mm
1361 switching code so that no page table walks can cross the ASID switch.
1363 config ARM_ERRATA_754327
1364 bool "ARM errata: no automatic Store Buffer drain"
1365 depends on CPU_V7 && SMP
1367 This option enables the workaround for the 754327 Cortex-A9 (prior to
1368 r2p0) erratum. The Store Buffer does not have any automatic draining
1369 mechanism and therefore a livelock may occur if an external agent
1370 continuously polls a memory location waiting to observe an update.
1371 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1372 written polling loops from denying visibility of updates to memory.
1374 config ARM_ERRATA_364296
1375 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1376 depends on CPU_V6 && !SMP
1378 This options enables the workaround for the 364296 ARM1136
1379 r0p2 erratum (possible cache data corruption with
1380 hit-under-miss enabled). It sets the undocumented bit 31 in
1381 the auxiliary control register and the FI bit in the control
1382 register, thus disabling hit-under-miss without putting the
1383 processor into full low interrupt latency mode. ARM11MPCore
1386 config ARM_ERRATA_764369
1387 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1388 depends on CPU_V7 && SMP
1390 This option enables the workaround for erratum 764369
1391 affecting Cortex-A9 MPCore with two or more processors (all
1392 current revisions). Under certain timing circumstances, a data
1393 cache line maintenance operation by MVA targeting an Inner
1394 Shareable memory region may fail to proceed up to either the
1395 Point of Coherency or to the Point of Unification of the
1396 system. This workaround adds a DSB instruction before the
1397 relevant cache maintenance functions and sets a specific bit
1398 in the diagnostic control register of the SCU.
1400 config PL310_ERRATA_769419
1401 bool "PL310 errata: no automatic Store Buffer drain"
1402 depends on CACHE_L2X0
1404 On revisions of the PL310 prior to r3p2, the Store Buffer does
1405 not automatically drain. This can cause normal, non-cacheable
1406 writes to be retained when the memory system is idle, leading
1407 to suboptimal I/O performance for drivers using coherent DMA.
1408 This option adds a write barrier to the cpu_idle loop so that,
1409 on systems with an outer cache, the store buffer is drained
1414 source "arch/arm/common/Kconfig"
1424 Find out whether you have ISA slots on your motherboard. ISA is the
1425 name of a bus system, i.e. the way the CPU talks to the other stuff
1426 inside your box. Other bus systems are PCI, EISA, MicroChannel
1427 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1428 newer boards don't support it. If you have ISA, say Y, otherwise N.
1430 # Select ISA DMA controller support
1435 # Select ISA DMA interface
1440 bool "PCI support" if MIGHT_HAVE_PCI
1442 Find out whether you have a PCI motherboard. PCI is the name of a
1443 bus system, i.e. the way the CPU talks to the other stuff inside
1444 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1445 VESA. If you have PCI, say Y, otherwise N.
1451 config PCI_NANOENGINE
1452 bool "BSE nanoEngine PCI support"
1453 depends on SA1100_NANOENGINE
1455 Enable PCI on the BSE nanoEngine board.
1460 # Select the host bridge type
1461 config PCI_HOST_VIA82C505
1463 depends on PCI && ARCH_SHARK
1466 config PCI_HOST_ITE8152
1468 depends on PCI && MACH_ARMCORE
1472 source "drivers/pci/Kconfig"
1474 source "drivers/pcmcia/Kconfig"
1478 menu "Kernel Features"
1483 This option should be selected by machines which have an SMP-
1486 The only effect of this option is to make the SMP-related
1487 options available to the user for configuration.
1490 bool "Symmetric Multi-Processing"
1491 depends on CPU_V6K || CPU_V7
1492 depends on GENERIC_CLOCKEVENTS
1495 select USE_GENERIC_SMP_HELPERS
1496 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1498 This enables support for systems with more than one CPU. If you have
1499 a system with only one CPU, like most personal computers, say N. If
1500 you have a system with more than one CPU, say Y.
1502 If you say N here, the kernel will run on single and multiprocessor
1503 machines, but will use only one CPU of a multiprocessor machine. If
1504 you say Y here, the kernel will run on many, but not all, single
1505 processor machines. On a single processor machine, the kernel will
1506 run faster if you say N here.
1508 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1509 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1510 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1512 If you don't know what to do here, say N.
1515 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1516 depends on EXPERIMENTAL
1517 depends on SMP && !XIP_KERNEL
1520 SMP kernels contain instructions which fail on non-SMP processors.
1521 Enabling this option allows the kernel to modify itself to make
1522 these instructions safe. Disabling it allows about 1K of space
1525 If you don't know what to do here, say Y.
1527 config ARM_CPU_TOPOLOGY
1528 bool "Support cpu topology definition"
1529 depends on SMP && CPU_V7
1532 Support ARM cpu topology definition. The MPIDR register defines
1533 affinity between processors which is then used to describe the cpu
1534 topology of an ARM System.
1537 bool "Multi-core scheduler support"
1538 depends on ARM_CPU_TOPOLOGY
1540 Multi-core scheduler support improves the CPU scheduler's decision
1541 making when dealing with multi-core CPU chips at a cost of slightly
1542 increased overhead in some places. If unsure say N here.
1545 bool "SMT scheduler support"
1546 depends on ARM_CPU_TOPOLOGY
1548 Improves the CPU scheduler's decision making when dealing with
1549 MultiThreading at a cost of slightly increased overhead in some
1550 places. If unsure say N here.
1555 This option enables support for the ARM system coherency unit
1557 config ARM_ARCH_TIMER
1558 bool "Architected timer support"
1561 This option enables support for the ARM architected timer
1567 This options enables support for the ARM timer and watchdog unit
1570 prompt "Memory split"
1573 Select the desired split between kernel and user memory.
1575 If you are not absolutely sure what you are doing, leave this
1579 bool "3G/1G user/kernel split"
1581 bool "2G/2G user/kernel split"
1583 bool "1G/3G user/kernel split"
1588 default 0x40000000 if VMSPLIT_1G
1589 default 0x80000000 if VMSPLIT_2G
1593 int "Maximum number of CPUs (2-32)"
1599 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1600 depends on SMP && HOTPLUG && EXPERIMENTAL
1602 Say Y here to experiment with turning CPUs off and on. CPUs
1603 can be controlled through /sys/devices/system/cpu.
1606 bool "Use local timer interrupts"
1609 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1611 Enable support for local timers on SMP platforms, rather then the
1612 legacy IPI broadcast method. Local timers allows the system
1613 accounting to be spread across the timer interval, preventing a
1614 "thundering herd" at every timer tick.
1618 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1619 default 355 if ARCH_U8500
1620 default 264 if MACH_H4700
1621 default 512 if SOC_OMAP5
1622 default 288 if ARCH_VT8500
1625 Maximum number of GPIOs in the system.
1627 If unsure, leave the default value.
1629 source kernel/Kconfig.preempt
1633 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \
1634 ARCH_S5PV210 || ARCH_EXYNOS4
1635 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1636 default AT91_TIMER_HZ if ARCH_AT91
1637 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1640 config THUMB2_KERNEL
1641 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1642 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1644 select ARM_ASM_UNIFIED
1647 By enabling this option, the kernel will be compiled in
1648 Thumb-2 mode. A compiler/assembler that understand the unified
1649 ARM-Thumb syntax is needed.
1653 config THUMB2_AVOID_R_ARM_THM_JUMP11
1654 bool "Work around buggy Thumb-2 short branch relocations in gas"
1655 depends on THUMB2_KERNEL && MODULES
1658 Various binutils versions can resolve Thumb-2 branches to
1659 locally-defined, preemptible global symbols as short-range "b.n"
1660 branch instructions.
1662 This is a problem, because there's no guarantee the final
1663 destination of the symbol, or any candidate locations for a
1664 trampoline, are within range of the branch. For this reason, the
1665 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1666 relocation in modules at all, and it makes little sense to add
1669 The symptom is that the kernel fails with an "unsupported
1670 relocation" error when loading some modules.
1672 Until fixed tools are available, passing
1673 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1674 code which hits this problem, at the cost of a bit of extra runtime
1675 stack usage in some cases.
1677 The problem is described in more detail at:
1678 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1680 Only Thumb-2 kernels are affected.
1682 Unless you are sure your tools don't have this problem, say Y.
1684 config ARM_ASM_UNIFIED
1688 bool "Use the ARM EABI to compile the kernel"
1690 This option allows for the kernel to be compiled using the latest
1691 ARM ABI (aka EABI). This is only useful if you are using a user
1692 space environment that is also compiled with EABI.
1694 Since there are major incompatibilities between the legacy ABI and
1695 EABI, especially with regard to structure member alignment, this
1696 option also changes the kernel syscall calling convention to
1697 disambiguate both ABIs and allow for backward compatibility support
1698 (selected with CONFIG_OABI_COMPAT).
1700 To use this you need GCC version 4.0.0 or later.
1703 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1704 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1707 This option preserves the old syscall interface along with the
1708 new (ARM EABI) one. It also provides a compatibility layer to
1709 intercept syscalls that have structure arguments which layout
1710 in memory differs between the legacy ABI and the new ARM EABI
1711 (only for non "thumb" binaries). This option adds a tiny
1712 overhead to all syscalls and produces a slightly larger kernel.
1713 If you know you'll be using only pure EABI user space then you
1714 can say N here. If this option is not selected and you attempt
1715 to execute a legacy ABI binary then the result will be
1716 UNPREDICTABLE (in fact it can be predicted that it won't work
1717 at all). If in doubt say Y.
1719 config ARCH_HAS_HOLES_MEMORYMODEL
1722 config ARCH_SPARSEMEM_ENABLE
1725 config ARCH_SPARSEMEM_DEFAULT
1726 def_bool ARCH_SPARSEMEM_ENABLE
1728 config ARCH_SELECT_MEMORY_MODEL
1729 def_bool ARCH_SPARSEMEM_ENABLE
1731 config HAVE_ARCH_PFN_VALID
1732 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1735 bool "High Memory Support"
1738 The address space of ARM processors is only 4 Gigabytes large
1739 and it has to accommodate user address space, kernel address
1740 space as well as some memory mapped IO. That means that, if you
1741 have a large amount of physical memory and/or IO, not all of the
1742 memory can be "permanently mapped" by the kernel. The physical
1743 memory that is not permanently mapped is called "high memory".
1745 Depending on the selected kernel/user memory split, minimum
1746 vmalloc space and actual amount of RAM, you may not need this
1747 option which should result in a slightly faster kernel.
1752 bool "Allocate 2nd-level pagetables from highmem"
1755 config HW_PERF_EVENTS
1756 bool "Enable hardware performance counter support for perf events"
1757 depends on PERF_EVENTS
1760 Enable hardware performance counter support for perf events. If
1761 disabled, perf events will use software events only.
1765 config FORCE_MAX_ZONEORDER
1766 int "Maximum zone order" if ARCH_SHMOBILE
1767 range 11 64 if ARCH_SHMOBILE
1768 default "9" if SA1111
1771 The kernel memory allocator divides physically contiguous memory
1772 blocks into "zones", where each zone is a power of two number of
1773 pages. This option selects the largest power of two that the kernel
1774 keeps in the memory allocator. If you need to allocate very large
1775 blocks of physically contiguous memory, then you may need to
1776 increase this value.
1778 This config option is actually maximum order plus one. For example,
1779 a value of 11 means that the largest free memory block is 2^10 pages.
1782 bool "Timer and CPU usage LEDs"
1783 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1784 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1785 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1786 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1787 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1788 ARCH_AT91 || ARCH_DAVINCI || \
1789 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1791 If you say Y here, the LEDs on your machine will be used
1792 to provide useful information about your current system status.
1794 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1795 be able to select which LEDs are active using the options below. If
1796 you are compiling a kernel for the EBSA-110 or the LART however, the
1797 red LED will simply flash regularly to indicate that the system is
1798 still functional. It is safe to say Y here if you have a CATS
1799 system, but the driver will do nothing.
1802 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1803 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1804 || MACH_OMAP_PERSEUS2
1806 depends on !GENERIC_CLOCKEVENTS
1807 default y if ARCH_EBSA110
1809 If you say Y here, one of the system LEDs (the green one on the
1810 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1811 will flash regularly to indicate that the system is still
1812 operational. This is mainly useful to kernel hackers who are
1813 debugging unstable kernels.
1815 The LART uses the same LED for both Timer LED and CPU usage LED
1816 functions. You may choose to use both, but the Timer LED function
1817 will overrule the CPU usage LED.
1820 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1822 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1823 || MACH_OMAP_PERSEUS2
1826 If you say Y here, the red LED will be used to give a good real
1827 time indication of CPU usage, by lighting whenever the idle task
1828 is not currently executing.
1830 The LART uses the same LED for both Timer LED and CPU usage LED
1831 functions. You may choose to use both, but the Timer LED function
1832 will overrule the CPU usage LED.
1834 config ALIGNMENT_TRAP
1836 depends on CPU_CP15_MMU
1837 default y if !ARCH_EBSA110
1838 select HAVE_PROC_CPU if PROC_FS
1840 ARM processors cannot fetch/store information which is not
1841 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1842 address divisible by 4. On 32-bit ARM processors, these non-aligned
1843 fetch/store instructions will be emulated in software if you say
1844 here, which has a severe performance impact. This is necessary for
1845 correct operation of some network protocols. With an IP-only
1846 configuration it is safe to say N, otherwise say Y.
1848 config UACCESS_WITH_MEMCPY
1849 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1850 depends on MMU && EXPERIMENTAL
1851 default y if CPU_FEROCEON
1853 Implement faster copy_to_user and clear_user methods for CPU
1854 cores where a 8-word STM instruction give significantly higher
1855 memory write throughput than a sequence of individual 32bit stores.
1857 A possible side effect is a slight increase in scheduling latency
1858 between threads sharing the same address space if they invoke
1859 such copy operations with large buffers.
1861 However, if the CPU data cache is using a write-allocate mode,
1862 this option is unlikely to provide any performance gain.
1866 prompt "Enable seccomp to safely compute untrusted bytecode"
1868 This kernel feature is useful for number crunching applications
1869 that may need to compute untrusted bytecode during their
1870 execution. By using pipes or other transports made available to
1871 the process as file descriptors supporting the read/write
1872 syscalls, it's possible to isolate those applications in
1873 their own address space using seccomp. Once seccomp is
1874 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1875 and the task is only allowed to execute a few safe syscalls
1876 defined by each seccomp mode.
1878 config CC_STACKPROTECTOR
1879 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1880 depends on EXPERIMENTAL
1882 This option turns on the -fstack-protector GCC feature. This
1883 feature puts, at the beginning of functions, a canary value on
1884 the stack just before the return address, and validates
1885 the value just before actually returning. Stack based buffer
1886 overflows (that need to overwrite this return address) now also
1887 overwrite the canary, which gets detected and the attack is then
1888 neutralized via a kernel panic.
1889 This feature requires gcc version 4.2 or above.
1891 config DEPRECATED_PARAM_STRUCT
1892 bool "Provide old way to pass kernel parameters"
1894 This was deprecated in 2001 and announced to live on for 5 years.
1895 Some old boot loaders still use this way.
1902 bool "Flattened Device Tree support"
1904 select OF_EARLY_FLATTREE
1907 Include support for flattened device tree machine descriptions.
1909 # Compressed boot loader in ROM. Yes, we really want to ask about
1910 # TEXT and BSS so we preserve their values in the config files.
1911 config ZBOOT_ROM_TEXT
1912 hex "Compressed ROM boot loader base address"
1915 The physical address at which the ROM-able zImage is to be
1916 placed in the target. Platforms which normally make use of
1917 ROM-able zImage formats normally set this to a suitable
1918 value in their defconfig file.
1920 If ZBOOT_ROM is not enabled, this has no effect.
1922 config ZBOOT_ROM_BSS
1923 hex "Compressed ROM boot loader BSS address"
1926 The base address of an area of read/write memory in the target
1927 for the ROM-able zImage which must be available while the
1928 decompressor is running. It must be large enough to hold the
1929 entire decompressed kernel plus an additional 128 KiB.
1930 Platforms which normally make use of ROM-able zImage formats
1931 normally set this to a suitable value in their defconfig file.
1933 If ZBOOT_ROM is not enabled, this has no effect.
1936 bool "Compressed boot loader in ROM/flash"
1937 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1939 Say Y here if you intend to execute your compressed kernel image
1940 (zImage) directly from ROM or flash. If unsure, say N.
1943 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1944 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1945 default ZBOOT_ROM_NONE
1947 Include experimental SD/MMC loading code in the ROM-able zImage.
1948 With this enabled it is possible to write the ROM-able zImage
1949 kernel image to an MMC or SD card and boot the kernel straight
1950 from the reset vector. At reset the processor Mask ROM will load
1951 the first part of the ROM-able zImage which in turn loads the
1952 rest the kernel image to RAM.
1954 config ZBOOT_ROM_NONE
1955 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1957 Do not load image from SD or MMC
1959 config ZBOOT_ROM_MMCIF
1960 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1962 Load image from MMCIF hardware block.
1964 config ZBOOT_ROM_SH_MOBILE_SDHI
1965 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1967 Load image from SDHI hardware block
1971 config ARM_APPENDED_DTB
1972 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1973 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1975 With this option, the boot code will look for a device tree binary
1976 (DTB) appended to zImage
1977 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1979 This is meant as a backward compatibility convenience for those
1980 systems with a bootloader that can't be upgraded to accommodate
1981 the documented boot protocol using a device tree.
1983 Beware that there is very little in terms of protection against
1984 this option being confused by leftover garbage in memory that might
1985 look like a DTB header after a reboot if no actual DTB is appended
1986 to zImage. Do not leave this option active in a production kernel
1987 if you don't intend to always append a DTB. Proper passing of the
1988 location into r2 of a bootloader provided DTB is always preferable
1991 config ARM_ATAG_DTB_COMPAT
1992 bool "Supplement the appended DTB with traditional ATAG information"
1993 depends on ARM_APPENDED_DTB
1995 Some old bootloaders can't be updated to a DTB capable one, yet
1996 they provide ATAGs with memory configuration, the ramdisk address,
1997 the kernel cmdline string, etc. Such information is dynamically
1998 provided by the bootloader and can't always be stored in a static
1999 DTB. To allow a device tree enabled kernel to be used with such
2000 bootloaders, this option allows zImage to extract the information
2001 from the ATAG list and store it at run time into the appended DTB.
2004 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
2005 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2007 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
2008 bool "Use bootloader kernel arguments if available"
2010 Uses the command-line options passed by the boot loader instead of
2011 the device tree bootargs property. If the boot loader doesn't provide
2012 any, the device tree bootargs property will be used.
2014 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
2015 bool "Extend with bootloader kernel arguments"
2017 The command-line arguments provided by the boot loader will be
2018 appended to the the device tree bootargs property.
2023 string "Default kernel command string"
2026 On some architectures (EBSA110 and CATS), there is currently no way
2027 for the boot loader to pass arguments to the kernel. For these
2028 architectures, you should supply some command-line options at build
2029 time by entering them here. As a minimum, you should specify the
2030 memory size and the root device (e.g., mem=64M root=/dev/nfs).
2033 prompt "Kernel command line type" if CMDLINE != ""
2034 default CMDLINE_FROM_BOOTLOADER
2036 config CMDLINE_FROM_BOOTLOADER
2037 bool "Use bootloader kernel arguments if available"
2039 Uses the command-line options passed by the boot loader. If
2040 the boot loader doesn't provide any, the default kernel command
2041 string provided in CMDLINE will be used.
2043 config CMDLINE_EXTEND
2044 bool "Extend bootloader kernel arguments"
2046 The command-line arguments provided by the boot loader will be
2047 appended to the default kernel command string.
2049 config CMDLINE_FORCE
2050 bool "Always use the default kernel command string"
2052 Always use the default kernel command string, even if the boot
2053 loader passes other arguments to the kernel.
2054 This is useful if you cannot or don't want to change the
2055 command-line options your boot loader passes to the kernel.
2059 bool "Kernel Execute-In-Place from ROM"
2060 depends on !ZBOOT_ROM && !ARM_LPAE
2062 Execute-In-Place allows the kernel to run from non-volatile storage
2063 directly addressable by the CPU, such as NOR flash. This saves RAM
2064 space since the text section of the kernel is not loaded from flash
2065 to RAM. Read-write sections, such as the data section and stack,
2066 are still copied to RAM. The XIP kernel is not compressed since
2067 it has to run directly from flash, so it will take more space to
2068 store it. The flash address used to link the kernel object files,
2069 and for storing it, is configuration dependent. Therefore, if you
2070 say Y here, you must know the proper physical address where to
2071 store the kernel image depending on your own flash memory usage.
2073 Also note that the make target becomes "make xipImage" rather than
2074 "make zImage" or "make Image". The final kernel binary to put in
2075 ROM memory will be arch/arm/boot/xipImage.
2079 config XIP_PHYS_ADDR
2080 hex "XIP Kernel Physical Location"
2081 depends on XIP_KERNEL
2082 default "0x00080000"
2084 This is the physical address in your flash memory the kernel will
2085 be linked for and stored to. This address is dependent on your
2089 bool "Kexec system call (EXPERIMENTAL)"
2090 depends on EXPERIMENTAL && (!SMP || HOTPLUG_CPU)
2092 kexec is a system call that implements the ability to shutdown your
2093 current kernel, and to start another kernel. It is like a reboot
2094 but it is independent of the system firmware. And like a reboot
2095 you can start any kernel with it, not just Linux.
2097 It is an ongoing process to be certain the hardware in a machine
2098 is properly shutdown, so do not be surprised if this code does not
2099 initially work for you. It may help to enable device hotplugging
2103 bool "Export atags in procfs"
2107 Should the atags used to boot the kernel be exported in an "atags"
2108 file in procfs. Useful with kexec.
2111 bool "Build kdump crash kernel (EXPERIMENTAL)"
2112 depends on EXPERIMENTAL
2114 Generate crash dump after being started by kexec. This should
2115 be normally only set in special crash dump kernels which are
2116 loaded in the main kernel with kexec-tools into a specially
2117 reserved region and then later executed after a crash by
2118 kdump/kexec. The crash dump kernel must be compiled to a
2119 memory address not used by the main kernel
2121 For more details see Documentation/kdump/kdump.txt
2123 config AUTO_ZRELADDR
2124 bool "Auto calculation of the decompressed kernel image address"
2125 depends on !ZBOOT_ROM && !ARCH_U300
2127 ZRELADDR is the physical address where the decompressed kernel
2128 image will be placed. If AUTO_ZRELADDR is selected, the address
2129 will be determined at run-time by masking the current IP with
2130 0xf8000000. This assumes the zImage being placed in the first 128MB
2131 from start of memory.
2135 menu "CPU Power Management"
2139 source "drivers/cpufreq/Kconfig"
2142 tristate "CPUfreq driver for i.MX CPUs"
2143 depends on ARCH_MXC && CPU_FREQ
2144 select CPU_FREQ_TABLE
2146 This enables the CPUfreq driver for i.MX CPUs.
2148 config CPU_FREQ_SA1100
2151 config CPU_FREQ_SA1110
2154 config CPU_FREQ_INTEGRATOR
2155 tristate "CPUfreq driver for ARM Integrator CPUs"
2156 depends on ARCH_INTEGRATOR && CPU_FREQ
2159 This enables the CPUfreq driver for ARM Integrator CPUs.
2161 For details, take a look at <file:Documentation/cpu-freq>.
2167 depends on CPU_FREQ && ARCH_PXA && PXA25x
2169 select CPU_FREQ_TABLE
2170 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2175 Internal configuration node for common cpufreq on Samsung SoC
2177 config CPU_FREQ_S3C24XX
2178 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2179 depends on ARCH_S3C24XX && CPU_FREQ && EXPERIMENTAL
2182 This enables the CPUfreq driver for the Samsung S3C24XX family
2185 For details, take a look at <file:Documentation/cpu-freq>.
2189 config CPU_FREQ_S3C24XX_PLL
2190 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2191 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2193 Compile in support for changing the PLL frequency from the
2194 S3C24XX series CPUfreq driver. The PLL takes time to settle
2195 after a frequency change, so by default it is not enabled.
2197 This also means that the PLL tables for the selected CPU(s) will
2198 be built which may increase the size of the kernel image.
2200 config CPU_FREQ_S3C24XX_DEBUG
2201 bool "Debug CPUfreq Samsung driver core"
2202 depends on CPU_FREQ_S3C24XX
2204 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2206 config CPU_FREQ_S3C24XX_IODEBUG
2207 bool "Debug CPUfreq Samsung driver IO timing"
2208 depends on CPU_FREQ_S3C24XX
2210 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2212 config CPU_FREQ_S3C24XX_DEBUGFS
2213 bool "Export debugfs for CPUFreq"
2214 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2216 Export status information via debugfs.
2220 source "drivers/cpuidle/Kconfig"
2224 menu "Floating point emulation"
2226 comment "At least one emulation must be selected"
2229 bool "NWFPE math emulation"
2230 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2232 Say Y to include the NWFPE floating point emulator in the kernel.
2233 This is necessary to run most binaries. Linux does not currently
2234 support floating point hardware so you need to say Y here even if
2235 your machine has an FPA or floating point co-processor podule.
2237 You may say N here if you are going to load the Acorn FPEmulator
2238 early in the bootup.
2241 bool "Support extended precision"
2242 depends on FPE_NWFPE
2244 Say Y to include 80-bit support in the kernel floating-point
2245 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2246 Note that gcc does not generate 80-bit operations by default,
2247 so in most cases this option only enlarges the size of the
2248 floating point emulator without any good reason.
2250 You almost surely want to say N here.
2253 bool "FastFPE math emulation (EXPERIMENTAL)"
2254 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2256 Say Y here to include the FAST floating point emulator in the kernel.
2257 This is an experimental much faster emulator which now also has full
2258 precision for the mantissa. It does not support any exceptions.
2259 It is very simple, and approximately 3-6 times faster than NWFPE.
2261 It should be sufficient for most programs. It may be not suitable
2262 for scientific calculations, but you have to check this for yourself.
2263 If you do not feel you need a faster FP emulation you should better
2267 bool "VFP-format floating point maths"
2268 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2270 Say Y to include VFP support code in the kernel. This is needed
2271 if your hardware includes a VFP unit.
2273 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2274 release notes and additional status information.
2276 Say N if your target does not have VFP hardware.
2284 bool "Advanced SIMD (NEON) Extension support"
2285 depends on VFPv3 && CPU_V7
2287 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2292 menu "Userspace binary formats"
2294 source "fs/Kconfig.binfmt"
2297 tristate "RISC OS personality"
2300 Say Y here to include the kernel code necessary if you want to run
2301 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2302 experimental; if this sounds frightening, say N and sleep in peace.
2303 You can also say M here to compile this support as a module (which
2304 will be called arthur).
2308 menu "Power management options"
2310 source "kernel/power/Kconfig"
2312 config ARCH_SUSPEND_POSSIBLE
2313 depends on !ARCH_S5PC100
2314 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2315 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2318 config ARM_CPU_SUSPEND
2323 source "net/Kconfig"
2325 source "drivers/Kconfig"
2329 source "arch/arm/Kconfig.debug"
2331 source "security/Kconfig"
2333 source "crypto/Kconfig"
2335 source "lib/Kconfig"