1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_CORRECT_STACKTRACE_ON_KRETPROBE if HAVE_KRETPROBES && FRAME_POINTER && !ARM_UNWIND
7 select ARCH_HAS_BINFMT_FLAT
8 select ARCH_HAS_CURRENT_STACK_POINTER
9 select ARCH_HAS_DEBUG_VIRTUAL if MMU
10 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
11 select ARCH_HAS_ELF_RANDOMIZE
12 select ARCH_HAS_FORTIFY_SOURCE
13 select ARCH_HAS_KEEPINITRD
15 select ARCH_HAS_MEMBARRIER_SYNC_CORE
16 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
17 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
18 select ARCH_HAS_PHYS_TO_DMA
19 select ARCH_HAS_SETUP_DMA_OPS
20 select ARCH_HAS_SET_MEMORY
21 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
22 select ARCH_HAS_STRICT_MODULE_RWX if MMU
23 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB || !MMU
24 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB || !MMU
25 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
26 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
27 select ARCH_HAVE_CUSTOM_GPIO_H
28 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
29 select ARCH_HAS_GCOV_PROFILE_ALL
30 select ARCH_KEEP_MEMBLOCK
31 select ARCH_MIGHT_HAVE_PC_PARPORT
32 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
33 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
34 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
35 select ARCH_SUPPORTS_ATOMIC_RMW
36 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
37 select ARCH_USE_BUILTIN_BSWAP
38 select ARCH_USE_CMPXCHG_LOCKREF
39 select ARCH_USE_MEMTEST
40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
41 select ARCH_WANT_GENERAL_HUGETLB
42 select ARCH_WANT_IPC_PARSE_VERSION
43 select ARCH_WANT_LD_ORPHAN_WARN
44 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
45 select BUILDTIME_TABLE_SORT if MMU
46 select CLONE_BACKWARDS
47 select CPU_PM if SUSPEND || CPU_IDLE
48 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
49 select DMA_DECLARE_COHERENT
50 select DMA_GLOBAL_POOL if !MMU
52 select DMA_NONCOHERENT_MMAP if MMU
54 select EDAC_ATOMIC_SCRUB
55 select GENERIC_ALLOCATOR
56 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
57 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
58 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
59 select GENERIC_IRQ_IPI if SMP
60 select GENERIC_CPU_AUTOPROBE
61 select GENERIC_EARLY_IOREMAP
62 select GENERIC_IDLE_POLL_SETUP
63 select GENERIC_IRQ_MULTI_HANDLER
64 select GENERIC_IRQ_PROBE
65 select GENERIC_IRQ_SHOW
66 select GENERIC_IRQ_SHOW_LEVEL
67 select GENERIC_LIB_DEVMEM_IS_ALLOWED
68 select GENERIC_PCI_IOMAP
69 select GENERIC_SCHED_CLOCK
70 select GENERIC_SMP_IDLE_THREAD
71 select HARDIRQS_SW_RESEND
72 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
73 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
74 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
75 select HAVE_ARCH_KFENCE if MMU && !XIP_KERNEL
76 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
77 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
78 select HAVE_ARCH_MMAP_RND_BITS if MMU
79 select HAVE_ARCH_PFN_VALID
80 select HAVE_ARCH_SECCOMP
81 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
82 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
83 select HAVE_ARCH_TRACEHOOK
84 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
85 select HAVE_ARM_SMCCC if CPU_V7
86 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
87 select HAVE_CONTEXT_TRACKING
88 select HAVE_C_RECORDMCOUNT
89 select HAVE_BUILDTIME_MCOUNT_SORT
90 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
91 select HAVE_DMA_CONTIGUOUS if MMU
92 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
93 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
94 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
95 select HAVE_EXIT_THREAD
96 select HAVE_FAST_GUP if ARM_LPAE
97 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
98 select HAVE_FUNCTION_GRAPH_TRACER
99 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
100 select HAVE_GCC_PLUGINS
101 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
102 select HAVE_IRQ_TIME_ACCOUNTING
103 select HAVE_KERNEL_GZIP
104 select HAVE_KERNEL_LZ4
105 select HAVE_KERNEL_LZMA
106 select HAVE_KERNEL_LZO
107 select HAVE_KERNEL_XZ
108 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
109 select HAVE_KRETPROBES if HAVE_KPROBES
110 select HAVE_MOD_ARCH_SPECIFIC
112 select HAVE_OPTPROBES if !THUMB2_KERNEL
113 select HAVE_PERF_EVENTS
114 select HAVE_PERF_REGS
115 select HAVE_PERF_USER_STACK_DUMP
116 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
117 select HAVE_REGS_AND_STACK_ACCESS_API
119 select HAVE_STACKPROTECTOR
120 select HAVE_SYSCALL_TRACEPOINTS
122 select HAVE_VIRT_CPU_ACCOUNTING_GEN
123 select IRQ_FORCED_THREADING
124 select MODULES_USE_ELF_REL
125 select NEED_DMA_MAP_STATE
126 select OF_EARLY_FLATTREE if OF
128 select OLD_SIGSUSPEND3
129 select PCI_SYSCALL if PCI
130 select PERF_USE_VMALLOC
132 select SYS_SUPPORTS_APM_EMULATION
133 select THREAD_INFO_IN_TASK
134 select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
135 select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
136 # Above selects are sorted alphabetically; please add new ones
137 # according to that. Thanks.
139 The ARM series is a line of low-power-consumption RISC chip designs
140 licensed by ARM Ltd and targeted at embedded applications and
141 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
142 manufactured, but legacy ARM-based PC hardware remains popular in
143 Europe. There is an ARM Linux project with a web page at
144 <http://www.arm.linux.org.uk/>.
146 config ARM_HAS_GROUP_RELOCS
148 depends on !LD_IS_LLD || LLD_VERSION >= 140000
149 depends on !COMPILE_TEST
151 Whether or not to use R_ARM_ALU_PC_Gn or R_ARM_LDR_PC_Gn group
152 relocations, which have been around for a long time, but were not
153 supported in LLD until version 14. The combined range is -/+ 256 MiB,
154 which is usually sufficient, but not for allyesconfig, so we disable
155 this feature when doing compile testing.
157 config ARM_HAS_SG_CHAIN
160 config ARM_DMA_USE_IOMMU
162 select ARM_HAS_SG_CHAIN
163 select NEED_SG_DMA_LENGTH
167 config ARM_DMA_IOMMU_ALIGNMENT
168 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
172 DMA mapping framework by default aligns all buffers to the smallest
173 PAGE_SIZE order which is greater than or equal to the requested buffer
174 size. This works well for buffers up to a few hundreds kilobytes, but
175 for larger buffers it just a waste of address space. Drivers which has
176 relatively small addressing window (like 64Mib) might run out of
177 virtual space with just a few allocations.
179 With this parameter you can specify the maximum PAGE_SIZE order for
180 DMA IOMMU buffers. Larger buffers will be aligned only to this
181 specified order. The order is expressed as a power of two multiplied
186 config SYS_SUPPORTS_APM_EMULATION
191 select GENERIC_ALLOCATOR
202 config STACKTRACE_SUPPORT
206 config LOCKDEP_SUPPORT
210 config ARCH_HAS_ILOG2_U32
213 config ARCH_HAS_ILOG2_U64
216 config ARCH_HAS_BANDGAP
219 config FIX_EARLYCON_MEM
222 config GENERIC_HWEIGHT
226 config GENERIC_CALIBRATE_DELAY
230 config ARCH_MAY_HAVE_PC_FDC
233 config ARCH_SUPPORTS_UPROBES
236 config GENERIC_ISA_DMA
245 config ARM_PATCH_PHYS_VIRT
246 bool "Patch physical to virtual translations at runtime" if EMBEDDED
248 depends on !XIP_KERNEL && MMU
250 Patch phys-to-virt and virt-to-phys translation functions at
251 boot and module load time according to the position of the
252 kernel in system memory.
254 This can only be used with non-XIP MMU kernels where the base
255 of physical memory is at a 2 MiB boundary.
257 Only disable this option if you know that you do not require
258 this feature (eg, building a kernel for a single machine) and
259 you need to shrink the kernel to the minimal size.
261 config NEED_MACH_IO_H
264 Select this when mach/io.h is required to provide special
265 definitions for this platform. The need for mach/io.h should
266 be avoided when possible.
268 config NEED_MACH_MEMORY_H
271 Select this when mach/memory.h is required to provide special
272 definitions for this platform. The need for mach/memory.h should
273 be avoided when possible.
276 hex "Physical address of main memory" if MMU
277 depends on !ARM_PATCH_PHYS_VIRT
278 default DRAM_BASE if !MMU
279 default 0x00000000 if ARCH_FOOTBRIDGE
280 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
281 default 0x30000000 if ARCH_S3C24XX
282 default 0xa0000000 if ARCH_IOP32X || ARCH_PXA
283 default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100
286 Please provide the physical address corresponding to the
287 location of main memory in your system.
293 config PGTABLE_LEVELS
295 default 3 if ARM_LPAE
301 bool "MMU-based Paged Memory Management Support"
304 Select if you want MMU-based virtualised addressing space
305 support by paged memory management. If unsure, say 'Y'.
307 config ARM_SINGLE_ARMV7M
318 config ARCH_MMAP_RND_BITS_MIN
321 config ARCH_MMAP_RND_BITS_MAX
322 default 14 if PAGE_OFFSET=0x40000000
323 default 15 if PAGE_OFFSET=0x80000000
327 # The "ARM system type" choice list is ordered alphabetically by option
328 # text. Please add new entries in the option alphabetic order.
331 prompt "ARM system type"
333 default ARCH_MULTIPLATFORM
335 config ARCH_MULTIPLATFORM
336 bool "Allow multiple platforms to be selected"
337 select ARCH_FLATMEM_ENABLE
338 select ARCH_SPARSEMEM_ENABLE
339 select ARCH_SELECT_MEMORY_MODEL
340 select ARM_HAS_SG_CHAIN
341 select ARM_PATCH_PHYS_VIRT
346 select PCI_DOMAINS_GENERIC if PCI
350 config ARCH_FOOTBRIDGE
352 depends on CPU_LITTLE_ENDIAN
356 select NEED_MACH_MEMORY_H
358 Support for systems based on the DC21285 companion chip
359 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
363 depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
364 depends on CPU_LITTLE_ENDIAN
367 select ARCH_MAY_HAVE_PC_FDC
368 select ARCH_SPARSEMEM_ENABLE
369 select ARM_HAS_SG_CHAIN
372 select HAVE_PATA_PLATFORM
374 select LEGACY_TIMER_TICK
375 select NEED_MACH_IO_H
376 select NEED_MACH_MEMORY_H
379 On the Acorn Risc-PC, Linux can support the internal IDE disk and
380 CD-ROM interface, serial and parallel port, and the floppy drive.
384 depends on CPU_LITTLE_ENDIAN
387 select ARCH_SPARSEMEM_ENABLE
390 select TIMER_OF if OF
397 select NEED_MACH_MEMORY_H
400 Support for StrongARM 11x0 based boards.
404 menu "Multiple platform selection"
405 depends on ARCH_MULTIPLATFORM
407 comment "CPU Core family selection"
410 bool "ARMv4 based platforms (FA526)"
411 depends on !ARCH_MULTI_V6_V7
412 select ARCH_MULTI_V4_V5
415 config ARCH_MULTI_V4T
416 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
417 depends on !ARCH_MULTI_V6_V7
418 select ARCH_MULTI_V4_V5
419 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
420 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
421 CPU_ARM925T || CPU_ARM940T)
424 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
425 depends on !ARCH_MULTI_V6_V7
426 select ARCH_MULTI_V4_V5
427 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
428 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
429 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
431 config ARCH_MULTI_V4_V5
435 bool "ARMv6 based platforms (ARM11)"
436 select ARCH_MULTI_V6_V7
440 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
442 select ARCH_MULTI_V6_V7
446 config ARCH_MULTI_V6_V7
448 select MIGHT_HAVE_CACHE_L2X0
450 config ARCH_MULTI_CPU_AUTO
451 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
457 bool "Dummy Virtual Machine"
458 depends on ARCH_MULTI_V7
461 select ARM_GIC_V2M if PCI
463 select ARM_GIC_V3_ITS if PCI
465 select HAVE_ARM_ARCH_TIMER
468 bool "Airoha SoC Support"
469 depends on ARCH_MULTI_V7
474 select HAVE_ARM_ARCH_TIMER
477 Support for Airoha EN7523 SoCs
480 # This is sorted alphabetically by mach-* pathname. However, plat-*
481 # Kconfigs may be included either alphabetically (according to the
482 # plat- suffix) or along side the corresponding mach-* source.
484 source "arch/arm/mach-actions/Kconfig"
486 source "arch/arm/mach-alpine/Kconfig"
488 source "arch/arm/mach-artpec/Kconfig"
490 source "arch/arm/mach-asm9260/Kconfig"
492 source "arch/arm/mach-aspeed/Kconfig"
494 source "arch/arm/mach-at91/Kconfig"
496 source "arch/arm/mach-axxia/Kconfig"
498 source "arch/arm/mach-bcm/Kconfig"
500 source "arch/arm/mach-berlin/Kconfig"
502 source "arch/arm/mach-clps711x/Kconfig"
504 source "arch/arm/mach-cns3xxx/Kconfig"
506 source "arch/arm/mach-davinci/Kconfig"
508 source "arch/arm/mach-digicolor/Kconfig"
510 source "arch/arm/mach-dove/Kconfig"
512 source "arch/arm/mach-ep93xx/Kconfig"
514 source "arch/arm/mach-exynos/Kconfig"
516 source "arch/arm/mach-footbridge/Kconfig"
518 source "arch/arm/mach-gemini/Kconfig"
520 source "arch/arm/mach-highbank/Kconfig"
522 source "arch/arm/mach-hisi/Kconfig"
524 source "arch/arm/mach-hpe/Kconfig"
526 source "arch/arm/mach-imx/Kconfig"
528 source "arch/arm/mach-iop32x/Kconfig"
530 source "arch/arm/mach-ixp4xx/Kconfig"
532 source "arch/arm/mach-keystone/Kconfig"
534 source "arch/arm/mach-lpc32xx/Kconfig"
536 source "arch/arm/mach-mediatek/Kconfig"
538 source "arch/arm/mach-meson/Kconfig"
540 source "arch/arm/mach-milbeaut/Kconfig"
542 source "arch/arm/mach-mmp/Kconfig"
544 source "arch/arm/mach-moxart/Kconfig"
546 source "arch/arm/mach-mstar/Kconfig"
548 source "arch/arm/mach-mv78xx0/Kconfig"
550 source "arch/arm/mach-mvebu/Kconfig"
552 source "arch/arm/mach-mxs/Kconfig"
554 source "arch/arm/mach-nomadik/Kconfig"
556 source "arch/arm/mach-npcm/Kconfig"
558 source "arch/arm/mach-nspire/Kconfig"
560 source "arch/arm/mach-omap1/Kconfig"
562 source "arch/arm/mach-omap2/Kconfig"
564 source "arch/arm/mach-orion5x/Kconfig"
566 source "arch/arm/mach-oxnas/Kconfig"
568 source "arch/arm/mach-pxa/Kconfig"
570 source "arch/arm/mach-qcom/Kconfig"
572 source "arch/arm/mach-rda/Kconfig"
574 source "arch/arm/mach-realtek/Kconfig"
576 source "arch/arm/mach-rockchip/Kconfig"
578 source "arch/arm/mach-s3c/Kconfig"
580 source "arch/arm/mach-s5pv210/Kconfig"
582 source "arch/arm/mach-sa1100/Kconfig"
584 source "arch/arm/mach-shmobile/Kconfig"
586 source "arch/arm/mach-socfpga/Kconfig"
588 source "arch/arm/mach-spear/Kconfig"
590 source "arch/arm/mach-sti/Kconfig"
592 source "arch/arm/mach-stm32/Kconfig"
594 source "arch/arm/mach-sunxi/Kconfig"
596 source "arch/arm/mach-tegra/Kconfig"
598 source "arch/arm/mach-uniphier/Kconfig"
600 source "arch/arm/mach-ux500/Kconfig"
602 source "arch/arm/mach-versatile/Kconfig"
604 source "arch/arm/mach-vt8500/Kconfig"
606 source "arch/arm/mach-zynq/Kconfig"
608 # ARMv7-M architecture
610 bool "NXP LPC18xx/LPC43xx"
611 depends on ARM_SINGLE_ARMV7M
612 select ARCH_HAS_RESET_CONTROLLER
614 select CLKSRC_LPC32XX
617 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
618 high performance microcontrollers.
621 bool "ARM MPS2 platform"
622 depends on ARM_SINGLE_ARMV7M
626 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
627 with a range of available cores like Cortex-M3/M4/M7.
629 Please, note that depends which Application Note is used memory map
630 for the platform may vary, so adjustment of RAM base might be needed.
632 # Definitions to make life easier
640 select GENERIC_IRQ_CHIP
643 config PLAT_ORION_LEGACY
647 config PLAT_VERSATILE
650 source "arch/arm/mm/Kconfig"
653 bool "Enable iWMMXt support"
654 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
655 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
657 Enable support for iWMMXt context switching at run time if
658 running on a CPU that supports it.
661 source "arch/arm/Kconfig-nommu"
664 config PJ4B_ERRATA_4742
665 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
666 depends on CPU_PJ4B && MACH_ARMADA_370
669 When coming out of either a Wait for Interrupt (WFI) or a Wait for
670 Event (WFE) IDLE states, a specific timing sensitivity exists between
671 the retiring WFI/WFE instructions and the newly issued subsequent
672 instructions. This sensitivity can result in a CPU hang scenario.
674 The software must insert either a Data Synchronization Barrier (DSB)
675 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
678 config ARM_ERRATA_326103
679 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
682 Executing a SWP instruction to read-only memory does not set bit 11
683 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
684 treat the access as a read, preventing a COW from occurring and
685 causing the faulting task to livelock.
687 config ARM_ERRATA_411920
688 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
689 depends on CPU_V6 || CPU_V6K
691 Invalidation of the Instruction Cache operation can
692 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
693 It does not affect the MPCore. This option enables the ARM Ltd.
694 recommended workaround.
696 config ARM_ERRATA_430973
697 bool "ARM errata: Stale prediction on replaced interworking branch"
700 This option enables the workaround for the 430973 Cortex-A8
701 r1p* erratum. If a code sequence containing an ARM/Thumb
702 interworking branch is replaced with another code sequence at the
703 same virtual address, whether due to self-modifying code or virtual
704 to physical address re-mapping, Cortex-A8 does not recover from the
705 stale interworking branch prediction. This results in Cortex-A8
706 executing the new code sequence in the incorrect ARM or Thumb state.
707 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
708 and also flushes the branch target cache at every context switch.
709 Note that setting specific bits in the ACTLR register may not be
710 available in non-secure mode.
712 config ARM_ERRATA_458693
713 bool "ARM errata: Processor deadlock when a false hazard is created"
715 depends on !ARCH_MULTIPLATFORM
717 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
718 erratum. For very specific sequences of memory operations, it is
719 possible for a hazard condition intended for a cache line to instead
720 be incorrectly associated with a different cache line. This false
721 hazard might then cause a processor deadlock. The workaround enables
722 the L1 caching of the NEON accesses and disables the PLD instruction
723 in the ACTLR register. Note that setting specific bits in the ACTLR
724 register may not be available in non-secure mode.
726 config ARM_ERRATA_460075
727 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
729 depends on !ARCH_MULTIPLATFORM
731 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
732 erratum. Any asynchronous access to the L2 cache may encounter a
733 situation in which recent store transactions to the L2 cache are lost
734 and overwritten with stale memory contents from external memory. The
735 workaround disables the write-allocate mode for the L2 cache via the
736 ACTLR register. Note that setting specific bits in the ACTLR register
737 may not be available in non-secure mode.
739 config ARM_ERRATA_742230
740 bool "ARM errata: DMB operation may be faulty"
741 depends on CPU_V7 && SMP
742 depends on !ARCH_MULTIPLATFORM
744 This option enables the workaround for the 742230 Cortex-A9
745 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
746 between two write operations may not ensure the correct visibility
747 ordering of the two writes. This workaround sets a specific bit in
748 the diagnostic register of the Cortex-A9 which causes the DMB
749 instruction to behave as a DSB, ensuring the correct behaviour of
752 config ARM_ERRATA_742231
753 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
754 depends on CPU_V7 && SMP
755 depends on !ARCH_MULTIPLATFORM
757 This option enables the workaround for the 742231 Cortex-A9
758 (r2p0..r2p2) erratum. Under certain conditions, specific to the
759 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
760 accessing some data located in the same cache line, may get corrupted
761 data due to bad handling of the address hazard when the line gets
762 replaced from one of the CPUs at the same time as another CPU is
763 accessing it. This workaround sets specific bits in the diagnostic
764 register of the Cortex-A9 which reduces the linefill issuing
765 capabilities of the processor.
767 config ARM_ERRATA_643719
768 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
769 depends on CPU_V7 && SMP
772 This option enables the workaround for the 643719 Cortex-A9 (prior to
773 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
774 register returns zero when it should return one. The workaround
775 corrects this value, ensuring cache maintenance operations which use
776 it behave as intended and avoiding data corruption.
778 config ARM_ERRATA_720789
779 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
782 This option enables the workaround for the 720789 Cortex-A9 (prior to
783 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
784 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
785 As a consequence of this erratum, some TLB entries which should be
786 invalidated are not, resulting in an incoherency in the system page
787 tables. The workaround changes the TLB flushing routines to invalidate
788 entries regardless of the ASID.
790 config ARM_ERRATA_743622
791 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
793 depends on !ARCH_MULTIPLATFORM
795 This option enables the workaround for the 743622 Cortex-A9
796 (r2p*) erratum. Under very rare conditions, a faulty
797 optimisation in the Cortex-A9 Store Buffer may lead to data
798 corruption. This workaround sets a specific bit in the diagnostic
799 register of the Cortex-A9 which disables the Store Buffer
800 optimisation, preventing the defect from occurring. This has no
801 visible impact on the overall performance or power consumption of the
804 config ARM_ERRATA_751472
805 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
807 depends on !ARCH_MULTIPLATFORM
809 This option enables the workaround for the 751472 Cortex-A9 (prior
810 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
811 completion of a following broadcasted operation if the second
812 operation is received by a CPU before the ICIALLUIS has completed,
813 potentially leading to corrupted entries in the cache or TLB.
815 config ARM_ERRATA_754322
816 bool "ARM errata: possible faulty MMU translations following an ASID switch"
819 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
820 r3p*) erratum. A speculative memory access may cause a page table walk
821 which starts prior to an ASID switch but completes afterwards. This
822 can populate the micro-TLB with a stale entry which may be hit with
823 the new ASID. This workaround places two dsb instructions in the mm
824 switching code so that no page table walks can cross the ASID switch.
826 config ARM_ERRATA_754327
827 bool "ARM errata: no automatic Store Buffer drain"
828 depends on CPU_V7 && SMP
830 This option enables the workaround for the 754327 Cortex-A9 (prior to
831 r2p0) erratum. The Store Buffer does not have any automatic draining
832 mechanism and therefore a livelock may occur if an external agent
833 continuously polls a memory location waiting to observe an update.
834 This workaround defines cpu_relax() as smp_mb(), preventing correctly
835 written polling loops from denying visibility of updates to memory.
837 config ARM_ERRATA_364296
838 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
841 This options enables the workaround for the 364296 ARM1136
842 r0p2 erratum (possible cache data corruption with
843 hit-under-miss enabled). It sets the undocumented bit 31 in
844 the auxiliary control register and the FI bit in the control
845 register, thus disabling hit-under-miss without putting the
846 processor into full low interrupt latency mode. ARM11MPCore
849 config ARM_ERRATA_764369
850 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
851 depends on CPU_V7 && SMP
853 This option enables the workaround for erratum 764369
854 affecting Cortex-A9 MPCore with two or more processors (all
855 current revisions). Under certain timing circumstances, a data
856 cache line maintenance operation by MVA targeting an Inner
857 Shareable memory region may fail to proceed up to either the
858 Point of Coherency or to the Point of Unification of the
859 system. This workaround adds a DSB instruction before the
860 relevant cache maintenance functions and sets a specific bit
861 in the diagnostic control register of the SCU.
863 config ARM_ERRATA_764319
864 bool "ARM errata: Read to DBGPRSR and DBGOSLSR may generate Undefined instruction"
867 This option enables the workaround for the 764319 Cortex A-9 erratum.
868 CP14 read accesses to the DBGPRSR and DBGOSLSR registers generate an
869 unexpected Undefined Instruction exception when the DBGSWENABLE
870 external pin is set to 0, even when the CP14 accesses are performed
871 from a privileged mode. This work around catches the exception in a
872 way the kernel does not stop execution.
874 config ARM_ERRATA_775420
875 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
878 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
879 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
880 operation aborts with MMU exception, it might cause the processor
881 to deadlock. This workaround puts DSB before executing ISB if
882 an abort may occur on cache maintenance.
884 config ARM_ERRATA_798181
885 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
886 depends on CPU_V7 && SMP
888 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
889 adequately shooting down all use of the old entries. This
890 option enables the Linux kernel workaround for this erratum
891 which sends an IPI to the CPUs that are running the same ASID
892 as the one being invalidated.
894 config ARM_ERRATA_773022
895 bool "ARM errata: incorrect instructions may be executed from loop buffer"
898 This option enables the workaround for the 773022 Cortex-A15
899 (up to r0p4) erratum. In certain rare sequences of code, the
900 loop buffer may deliver incorrect instructions. This
901 workaround disables the loop buffer to avoid the erratum.
903 config ARM_ERRATA_818325_852422
904 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
907 This option enables the workaround for:
908 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
909 instruction might deadlock. Fixed in r0p1.
910 - Cortex-A12 852422: Execution of a sequence of instructions might
911 lead to either a data corruption or a CPU deadlock. Not fixed in
912 any Cortex-A12 cores yet.
913 This workaround for all both errata involves setting bit[12] of the
914 Feature Register. This bit disables an optimisation applied to a
915 sequence of 2 instructions that use opposing condition codes.
917 config ARM_ERRATA_821420
918 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
921 This option enables the workaround for the 821420 Cortex-A12
922 (all revs) erratum. In very rare timing conditions, a sequence
923 of VMOV to Core registers instructions, for which the second
924 one is in the shadow of a branch or abort, can lead to a
925 deadlock when the VMOV instructions are issued out-of-order.
927 config ARM_ERRATA_825619
928 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
931 This option enables the workaround for the 825619 Cortex-A12
932 (all revs) erratum. Within rare timing constraints, executing a
933 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
934 and Device/Strongly-Ordered loads and stores might cause deadlock
936 config ARM_ERRATA_857271
937 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
940 This option enables the workaround for the 857271 Cortex-A12
941 (all revs) erratum. Under very rare timing conditions, the CPU might
942 hang. The workaround is expected to have a < 1% performance impact.
944 config ARM_ERRATA_852421
945 bool "ARM errata: A17: DMB ST might fail to create order between stores"
948 This option enables the workaround for the 852421 Cortex-A17
949 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
950 execution of a DMB ST instruction might fail to properly order
951 stores from GroupA and stores from GroupB.
953 config ARM_ERRATA_852423
954 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
957 This option enables the workaround for:
958 - Cortex-A17 852423: Execution of a sequence of instructions might
959 lead to either a data corruption or a CPU deadlock. Not fixed in
960 any Cortex-A17 cores yet.
961 This is identical to Cortex-A12 erratum 852422. It is a separate
962 config option from the A12 erratum due to the way errata are checked
965 config ARM_ERRATA_857272
966 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
969 This option enables the workaround for the 857272 Cortex-A17 erratum.
970 This erratum is not known to be fixed in any A17 revision.
971 This is identical to Cortex-A12 erratum 857271. It is a separate
972 config option from the A12 erratum due to the way errata are checked
977 source "arch/arm/common/Kconfig"
984 Find out whether you have ISA slots on your motherboard. ISA is the
985 name of a bus system, i.e. the way the CPU talks to the other stuff
986 inside your box. Other bus systems are PCI, EISA, MicroChannel
987 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
988 newer boards don't support it. If you have ISA, say Y, otherwise N.
990 # Select ISA DMA controller support
995 # Select ISA DMA interface
999 config PCI_NANOENGINE
1000 bool "BSE nanoEngine PCI support"
1001 depends on SA1100_NANOENGINE
1003 Enable PCI on the BSE nanoEngine board.
1005 config ARM_ERRATA_814220
1006 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1009 The v7 ARM states that all cache and branch predictor maintenance
1010 operations that do not specify an address execute, relative to
1011 each other, in program order.
1012 However, because of this erratum, an L2 set/way cache maintenance
1013 operation can overtake an L1 set/way cache maintenance operation.
1014 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1019 menu "Kernel Features"
1024 This option should be selected by machines which have an SMP-
1027 The only effect of this option is to make the SMP-related
1028 options available to the user for configuration.
1031 bool "Symmetric Multi-Processing"
1032 depends on CPU_V6K || CPU_V7
1034 depends on MMU || ARM_MPU
1037 This enables support for systems with more than one CPU. If you have
1038 a system with only one CPU, say N. If you have a system with more
1039 than one CPU, say Y.
1041 If you say N here, the kernel will run on uni- and multiprocessor
1042 machines, but will use only one CPU of a multiprocessor machine. If
1043 you say Y here, the kernel will run on many, but not all,
1044 uniprocessor machines. On a uniprocessor machine, the kernel
1045 will run faster if you say N here.
1047 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1048 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1049 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1051 If you don't know what to do here, say N.
1054 bool "Allow booting SMP kernel on uniprocessor systems"
1055 depends on SMP && !XIP_KERNEL && MMU
1058 SMP kernels contain instructions which fail on non-SMP processors.
1059 Enabling this option allows the kernel to modify itself to make
1060 these instructions safe. Disabling it allows about 1K of space
1063 If you don't know what to do here, say Y.
1066 config CURRENT_POINTER_IN_TPIDRURO
1068 depends on CPU_32v6K && !CPU_V6
1072 select HAVE_IRQ_EXIT_ON_IRQ_STACK
1073 select HAVE_SOFTIRQ_ON_OWN_STACK
1075 config ARM_CPU_TOPOLOGY
1076 bool "Support cpu topology definition"
1077 depends on SMP && CPU_V7
1080 Support ARM cpu topology definition. The MPIDR register defines
1081 affinity between processors which is then used to describe the cpu
1082 topology of an ARM System.
1085 bool "Multi-core scheduler support"
1086 depends on ARM_CPU_TOPOLOGY
1088 Multi-core scheduler support improves the CPU scheduler's decision
1089 making when dealing with multi-core CPU chips at a cost of slightly
1090 increased overhead in some places. If unsure say N here.
1093 bool "SMT scheduler support"
1094 depends on ARM_CPU_TOPOLOGY
1096 Improves the CPU scheduler's decision making when dealing with
1097 MultiThreading at a cost of slightly increased overhead in some
1098 places. If unsure say N here.
1103 This option enables support for the ARM snoop control unit
1105 config HAVE_ARM_ARCH_TIMER
1106 bool "Architected timer support"
1108 select ARM_ARCH_TIMER
1110 This option enables support for the ARM architected timer
1115 This options enables support for the ARM timer and watchdog unit
1118 bool "Multi-Cluster Power Management"
1119 depends on CPU_V7 && SMP
1121 This option provides the common power management infrastructure
1122 for (multi-)cluster based systems, such as big.LITTLE based
1125 config MCPM_QUAD_CLUSTER
1129 To avoid wasting resources unnecessarily, MCPM only supports up
1130 to 2 clusters by default.
1131 Platforms with 3 or 4 clusters that use MCPM must select this
1132 option to allow the additional clusters to be managed.
1135 bool "big.LITTLE support (Experimental)"
1136 depends on CPU_V7 && SMP
1139 This option enables support selections for the big.LITTLE
1140 system architecture.
1143 bool "big.LITTLE switcher support"
1144 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1147 The big.LITTLE "switcher" provides the core functionality to
1148 transparently handle transition between a cluster of A15's
1149 and a cluster of A7's in a big.LITTLE system.
1151 config BL_SWITCHER_DUMMY_IF
1152 tristate "Simple big.LITTLE switcher user interface"
1153 depends on BL_SWITCHER && DEBUG_KERNEL
1155 This is a simple and dummy char dev interface to control
1156 the big.LITTLE switcher core code. It is meant for
1157 debugging purposes only.
1160 prompt "Memory split"
1164 Select the desired split between kernel and user memory.
1166 If you are not absolutely sure what you are doing, leave this
1170 bool "3G/1G user/kernel split"
1171 config VMSPLIT_3G_OPT
1172 depends on !ARM_LPAE
1173 bool "3G/1G user/kernel split (for full 1G low memory)"
1175 bool "2G/2G user/kernel split"
1177 bool "1G/3G user/kernel split"
1182 default PHYS_OFFSET if !MMU
1183 default 0x40000000 if VMSPLIT_1G
1184 default 0x80000000 if VMSPLIT_2G
1185 default 0xB0000000 if VMSPLIT_3G_OPT
1188 config KASAN_SHADOW_OFFSET
1191 default 0x1f000000 if PAGE_OFFSET=0x40000000
1192 default 0x5f000000 if PAGE_OFFSET=0x80000000
1193 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1194 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1198 int "Maximum number of CPUs (2-32)"
1199 range 2 16 if DEBUG_KMAP_LOCAL
1200 range 2 32 if !DEBUG_KMAP_LOCAL
1204 The maximum number of CPUs that the kernel can support.
1205 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1206 debugging is enabled, which uses half of the per-CPU fixmap
1207 slots as guard regions.
1210 bool "Support for hot-pluggable CPUs"
1212 select GENERIC_IRQ_MIGRATION
1214 Say Y here to experiment with turning CPUs off and on. CPUs
1215 can be controlled through /sys/devices/system/cpu.
1218 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1219 depends on HAVE_ARM_SMCCC
1222 Say Y here if you want Linux to communicate with system firmware
1223 implementing the PSCI specification for CPU-centric power
1224 management operations described in ARM document number ARM DEN
1225 0022A ("Power State Coordination Interface System Software on
1228 # The GPIO number here must be sorted by descending number. In case of
1229 # a multiplatform kernel, we just want the highest value required by the
1230 # selected platforms.
1233 default 2048 if ARCH_INTEL_SOCFPGA
1234 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1235 ARCH_ZYNQ || ARCH_ASPEED
1236 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1237 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1238 default 416 if ARCH_SUNXI
1239 default 392 if ARCH_U8500
1240 default 352 if ARCH_VT8500
1241 default 288 if ARCH_ROCKCHIP
1242 default 264 if MACH_H4700
1245 Maximum number of GPIOs in the system.
1247 If unsure, leave the default value.
1251 default 128 if SOC_AT91RM9200
1255 depends on HZ_FIXED = 0
1256 prompt "Timer frequency"
1280 default HZ_FIXED if HZ_FIXED != 0
1281 default 100 if HZ_100
1282 default 200 if HZ_200
1283 default 250 if HZ_250
1284 default 300 if HZ_300
1285 default 500 if HZ_500
1289 def_bool HIGH_RES_TIMERS
1291 config THUMB2_KERNEL
1292 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1293 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1294 default y if CPU_THUMBONLY
1297 By enabling this option, the kernel will be compiled in
1302 config ARM_PATCH_IDIV
1303 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1304 depends on CPU_32v7 && !XIP_KERNEL
1307 The ARM compiler inserts calls to __aeabi_idiv() and
1308 __aeabi_uidiv() when it needs to perform division on signed
1309 and unsigned integers. Some v7 CPUs have support for the sdiv
1310 and udiv instructions that can be used to implement those
1313 Enabling this option allows the kernel to modify itself to
1314 replace the first two instructions of these library functions
1315 with the sdiv or udiv plus "bx lr" instructions when the CPU
1316 it is running on supports them. Typically this will be faster
1317 and less power intensive than running the original library
1318 code to do integer division.
1321 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1322 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1323 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1325 This option allows for the kernel to be compiled using the latest
1326 ARM ABI (aka EABI). This is only useful if you are using a user
1327 space environment that is also compiled with EABI.
1329 Since there are major incompatibilities between the legacy ABI and
1330 EABI, especially with regard to structure member alignment, this
1331 option also changes the kernel syscall calling convention to
1332 disambiguate both ABIs and allow for backward compatibility support
1333 (selected with CONFIG_OABI_COMPAT).
1335 To use this you need GCC version 4.0.0 or later.
1338 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1339 depends on AEABI && !THUMB2_KERNEL
1341 This option preserves the old syscall interface along with the
1342 new (ARM EABI) one. It also provides a compatibility layer to
1343 intercept syscalls that have structure arguments which layout
1344 in memory differs between the legacy ABI and the new ARM EABI
1345 (only for non "thumb" binaries). This option adds a tiny
1346 overhead to all syscalls and produces a slightly larger kernel.
1348 The seccomp filter system will not be available when this is
1349 selected, since there is no way yet to sensibly distinguish
1350 between calling conventions during filtering.
1352 If you know you'll be using only pure EABI user space then you
1353 can say N here. If this option is not selected and you attempt
1354 to execute a legacy ABI binary then the result will be
1355 UNPREDICTABLE (in fact it can be predicted that it won't work
1356 at all). If in doubt say N.
1358 config ARCH_SELECT_MEMORY_MODEL
1361 config ARCH_FLATMEM_ENABLE
1364 config ARCH_SPARSEMEM_ENABLE
1366 select SPARSEMEM_STATIC if SPARSEMEM
1369 bool "High Memory Support"
1372 select KMAP_LOCAL_NON_LINEAR_PTE_ARRAY
1374 The address space of ARM processors is only 4 Gigabytes large
1375 and it has to accommodate user address space, kernel address
1376 space as well as some memory mapped IO. That means that, if you
1377 have a large amount of physical memory and/or IO, not all of the
1378 memory can be "permanently mapped" by the kernel. The physical
1379 memory that is not permanently mapped is called "high memory".
1381 Depending on the selected kernel/user memory split, minimum
1382 vmalloc space and actual amount of RAM, you may not need this
1383 option which should result in a slightly faster kernel.
1388 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1392 The VM uses one page of physical memory for each page table.
1393 For systems with a lot of processes, this can use a lot of
1394 precious low memory, eventually leading to low memory being
1395 consumed by page tables. Setting this option will allow
1396 user-space 2nd level page tables to reside in high memory.
1398 config CPU_SW_DOMAIN_PAN
1399 bool "Enable use of CPU domains to implement privileged no-access"
1400 depends on MMU && !ARM_LPAE
1403 Increase kernel security by ensuring that normal kernel accesses
1404 are unable to access userspace addresses. This can help prevent
1405 use-after-free bugs becoming an exploitable privilege escalation
1406 by ensuring that magic values (such as LIST_POISON) will always
1407 fault when dereferenced.
1409 CPUs with low-vector mappings use a best-efforts implementation.
1410 Their lower 1MB needs to remain accessible for the vectors, but
1411 the remainder of userspace will become appropriately inaccessible.
1413 config HW_PERF_EVENTS
1417 config ARM_MODULE_PLTS
1418 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1422 Allocate PLTs when loading modules so that jumps and calls whose
1423 targets are too far away for their relative offsets to be encoded
1424 in the instructions themselves can be bounced via veneers in the
1425 module's PLT. This allows modules to be allocated in the generic
1426 vmalloc area after the dedicated module memory area has been
1427 exhausted. The modules will use slightly more memory, but after
1428 rounding up to page size, the actual memory footprint is usually
1431 Disabling this is usually safe for small single-platform
1432 configurations. If unsure, say y.
1434 config FORCE_MAX_ZONEORDER
1435 int "Maximum zone order"
1436 default "12" if SOC_AM33XX
1437 default "9" if SA1111
1440 The kernel memory allocator divides physically contiguous memory
1441 blocks into "zones", where each zone is a power of two number of
1442 pages. This option selects the largest power of two that the kernel
1443 keeps in the memory allocator. If you need to allocate very large
1444 blocks of physically contiguous memory, then you may need to
1445 increase this value.
1447 This config option is actually maximum order plus one. For example,
1448 a value of 11 means that the largest free memory block is 2^10 pages.
1450 config ALIGNMENT_TRAP
1451 def_bool CPU_CP15_MMU
1452 select HAVE_PROC_CPU if PROC_FS
1454 ARM processors cannot fetch/store information which is not
1455 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1456 address divisible by 4. On 32-bit ARM processors, these non-aligned
1457 fetch/store instructions will be emulated in software if you say
1458 here, which has a severe performance impact. This is necessary for
1459 correct operation of some network protocols. With an IP-only
1460 configuration it is safe to say N, otherwise say Y.
1462 config UACCESS_WITH_MEMCPY
1463 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1465 default y if CPU_FEROCEON
1467 Implement faster copy_to_user and clear_user methods for CPU
1468 cores where a 8-word STM instruction give significantly higher
1469 memory write throughput than a sequence of individual 32bit stores.
1471 A possible side effect is a slight increase in scheduling latency
1472 between threads sharing the same address space if they invoke
1473 such copy operations with large buffers.
1475 However, if the CPU data cache is using a write-allocate mode,
1476 this option is unlikely to provide any performance gain.
1479 bool "Enable paravirtualization code"
1481 This changes the kernel so it can modify itself when it is run
1482 under a hypervisor, potentially improving performance significantly
1483 over full virtualization.
1485 config PARAVIRT_TIME_ACCOUNTING
1486 bool "Paravirtual steal time accounting"
1489 Select this option to enable fine granularity task steal time
1490 accounting. Time spent executing other tasks in parallel with
1491 the current vCPU is discounted from the vCPU power. To account for
1492 that, there can be a small performance impact.
1494 If in doubt, say N here.
1501 bool "Xen guest support on ARM"
1502 depends on ARM && AEABI && OF
1503 depends on CPU_V7 && !CPU_V6
1504 depends on !GENERIC_ATOMIC64
1506 select ARCH_DMA_ADDR_T_64BIT
1512 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1514 config CC_HAVE_STACKPROTECTOR_TLS
1515 def_bool $(cc-option,-mtp=cp15 -mstack-protector-guard=tls -mstack-protector-guard-offset=0)
1517 config STACKPROTECTOR_PER_TASK
1518 bool "Use a unique stack canary value for each task"
1519 depends on STACKPROTECTOR && CURRENT_POINTER_IN_TPIDRURO && !XIP_DEFLATED_DATA
1520 depends on GCC_PLUGINS || CC_HAVE_STACKPROTECTOR_TLS
1521 select GCC_PLUGIN_ARM_SSP_PER_TASK if !CC_HAVE_STACKPROTECTOR_TLS
1524 Due to the fact that GCC uses an ordinary symbol reference from
1525 which to load the value of the stack canary, this value can only
1526 change at reboot time on SMP systems, and all tasks running in the
1527 kernel's address space are forced to use the same canary value for
1528 the entire duration that the system is up.
1530 Enable this option to switch to a different method that uses a
1531 different canary value for each task.
1538 bool "Flattened Device Tree support"
1542 Include support for flattened device tree machine descriptions.
1545 bool "Support for the traditional ATAGS boot data passing"
1548 This is the traditional way of passing data to the kernel at boot
1549 time. If you are solely relying on the flattened device tree (or
1550 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1551 to remove ATAGS support from your kernel binary.
1553 config UNUSED_BOARD_FILES
1554 bool "Board support for machines without known users"
1557 Most ATAGS based board files are completely unused and are
1558 scheduled for removal in early 2023, and left out of kernels
1559 by default now. If you are using a board file that is marked
1560 as unused, turn on this option to build support into the kernel.
1562 To keep support for your individual board from being removed,
1563 send a reply to the email discussion at
1564 https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/
1566 config DEPRECATED_PARAM_STRUCT
1567 bool "Provide old way to pass kernel parameters"
1570 This was deprecated in 2001 and announced to live on for 5 years.
1571 Some old boot loaders still use this way.
1573 # Compressed boot loader in ROM. Yes, we really want to ask about
1574 # TEXT and BSS so we preserve their values in the config files.
1575 config ZBOOT_ROM_TEXT
1576 hex "Compressed ROM boot loader base address"
1579 The physical address at which the ROM-able zImage is to be
1580 placed in the target. Platforms which normally make use of
1581 ROM-able zImage formats normally set this to a suitable
1582 value in their defconfig file.
1584 If ZBOOT_ROM is not enabled, this has no effect.
1586 config ZBOOT_ROM_BSS
1587 hex "Compressed ROM boot loader BSS address"
1590 The base address of an area of read/write memory in the target
1591 for the ROM-able zImage which must be available while the
1592 decompressor is running. It must be large enough to hold the
1593 entire decompressed kernel plus an additional 128 KiB.
1594 Platforms which normally make use of ROM-able zImage formats
1595 normally set this to a suitable value in their defconfig file.
1597 If ZBOOT_ROM is not enabled, this has no effect.
1600 bool "Compressed boot loader in ROM/flash"
1601 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1602 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1604 Say Y here if you intend to execute your compressed kernel image
1605 (zImage) directly from ROM or flash. If unsure, say N.
1607 config ARM_APPENDED_DTB
1608 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1611 With this option, the boot code will look for a device tree binary
1612 (DTB) appended to zImage
1613 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1615 This is meant as a backward compatibility convenience for those
1616 systems with a bootloader that can't be upgraded to accommodate
1617 the documented boot protocol using a device tree.
1619 Beware that there is very little in terms of protection against
1620 this option being confused by leftover garbage in memory that might
1621 look like a DTB header after a reboot if no actual DTB is appended
1622 to zImage. Do not leave this option active in a production kernel
1623 if you don't intend to always append a DTB. Proper passing of the
1624 location into r2 of a bootloader provided DTB is always preferable
1627 config ARM_ATAG_DTB_COMPAT
1628 bool "Supplement the appended DTB with traditional ATAG information"
1629 depends on ARM_APPENDED_DTB
1631 Some old bootloaders can't be updated to a DTB capable one, yet
1632 they provide ATAGs with memory configuration, the ramdisk address,
1633 the kernel cmdline string, etc. Such information is dynamically
1634 provided by the bootloader and can't always be stored in a static
1635 DTB. To allow a device tree enabled kernel to be used with such
1636 bootloaders, this option allows zImage to extract the information
1637 from the ATAG list and store it at run time into the appended DTB.
1640 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1641 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1643 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1644 bool "Use bootloader kernel arguments if available"
1646 Uses the command-line options passed by the boot loader instead of
1647 the device tree bootargs property. If the boot loader doesn't provide
1648 any, the device tree bootargs property will be used.
1650 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1651 bool "Extend with bootloader kernel arguments"
1653 The command-line arguments provided by the boot loader will be
1654 appended to the the device tree bootargs property.
1659 string "Default kernel command string"
1662 On some architectures (e.g. CATS), there is currently no way
1663 for the boot loader to pass arguments to the kernel. For these
1664 architectures, you should supply some command-line options at build
1665 time by entering them here. As a minimum, you should specify the
1666 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1669 prompt "Kernel command line type" if CMDLINE != ""
1670 default CMDLINE_FROM_BOOTLOADER
1673 config CMDLINE_FROM_BOOTLOADER
1674 bool "Use bootloader kernel arguments if available"
1676 Uses the command-line options passed by the boot loader. If
1677 the boot loader doesn't provide any, the default kernel command
1678 string provided in CMDLINE will be used.
1680 config CMDLINE_EXTEND
1681 bool "Extend bootloader kernel arguments"
1683 The command-line arguments provided by the boot loader will be
1684 appended to the default kernel command string.
1686 config CMDLINE_FORCE
1687 bool "Always use the default kernel command string"
1689 Always use the default kernel command string, even if the boot
1690 loader passes other arguments to the kernel.
1691 This is useful if you cannot or don't want to change the
1692 command-line options your boot loader passes to the kernel.
1696 bool "Kernel Execute-In-Place from ROM"
1697 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1699 Execute-In-Place allows the kernel to run from non-volatile storage
1700 directly addressable by the CPU, such as NOR flash. This saves RAM
1701 space since the text section of the kernel is not loaded from flash
1702 to RAM. Read-write sections, such as the data section and stack,
1703 are still copied to RAM. The XIP kernel is not compressed since
1704 it has to run directly from flash, so it will take more space to
1705 store it. The flash address used to link the kernel object files,
1706 and for storing it, is configuration dependent. Therefore, if you
1707 say Y here, you must know the proper physical address where to
1708 store the kernel image depending on your own flash memory usage.
1710 Also note that the make target becomes "make xipImage" rather than
1711 "make zImage" or "make Image". The final kernel binary to put in
1712 ROM memory will be arch/arm/boot/xipImage.
1716 config XIP_PHYS_ADDR
1717 hex "XIP Kernel Physical Location"
1718 depends on XIP_KERNEL
1719 default "0x00080000"
1721 This is the physical address in your flash memory the kernel will
1722 be linked for and stored to. This address is dependent on your
1725 config XIP_DEFLATED_DATA
1726 bool "Store kernel .data section compressed in ROM"
1727 depends on XIP_KERNEL
1730 Before the kernel is actually executed, its .data section has to be
1731 copied to RAM from ROM. This option allows for storing that data
1732 in compressed form and decompressed to RAM rather than merely being
1733 copied, saving some precious ROM space. A possible drawback is a
1734 slightly longer boot delay.
1737 bool "Kexec system call (EXPERIMENTAL)"
1738 depends on (!SMP || PM_SLEEP_SMP)
1742 kexec is a system call that implements the ability to shutdown your
1743 current kernel, and to start another kernel. It is like a reboot
1744 but it is independent of the system firmware. And like a reboot
1745 you can start any kernel with it, not just Linux.
1747 It is an ongoing process to be certain the hardware in a machine
1748 is properly shutdown, so do not be surprised if this code does not
1749 initially work for you.
1752 bool "Export atags in procfs"
1753 depends on ATAGS && KEXEC
1756 Should the atags used to boot the kernel be exported in an "atags"
1757 file in procfs. Useful with kexec.
1760 bool "Build kdump crash kernel (EXPERIMENTAL)"
1762 Generate crash dump after being started by kexec. This should
1763 be normally only set in special crash dump kernels which are
1764 loaded in the main kernel with kexec-tools into a specially
1765 reserved region and then later executed after a crash by
1766 kdump/kexec. The crash dump kernel must be compiled to a
1767 memory address not used by the main kernel
1769 For more details see Documentation/admin-guide/kdump/kdump.rst
1771 config AUTO_ZRELADDR
1772 bool "Auto calculation of the decompressed kernel image address"
1774 ZRELADDR is the physical address where the decompressed kernel
1775 image will be placed. If AUTO_ZRELADDR is selected, the address
1776 will be determined at run-time, either by masking the current IP
1777 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1778 This assumes the zImage being placed in the first 128MB from
1785 bool "UEFI runtime support"
1786 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1788 select EFI_PARAMS_FROM_FDT
1790 select EFI_GENERIC_STUB
1791 select EFI_RUNTIME_WRAPPERS
1793 This option provides support for runtime services provided
1794 by UEFI firmware (such as non-volatile variables, realtime
1795 clock, and platform reset). A UEFI stub is also provided to
1796 allow the kernel to be booted as an EFI application. This
1797 is only useful for kernels that may run on systems that have
1801 bool "Enable support for SMBIOS (DMI) tables"
1805 This enables SMBIOS/DMI feature for systems.
1807 This option is only useful on systems that have UEFI firmware.
1808 However, even with this option, the resultant kernel should
1809 continue to boot on existing non-UEFI platforms.
1811 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1812 i.e., the the practice of identifying the platform via DMI to
1813 decide whether certain workarounds for buggy hardware and/or
1814 firmware need to be enabled. This would require the DMI subsystem
1815 to be enabled much earlier than we do on ARM, which is non-trivial.
1819 menu "CPU Power Management"
1821 source "drivers/cpufreq/Kconfig"
1823 source "drivers/cpuidle/Kconfig"
1827 menu "Floating point emulation"
1829 comment "At least one emulation must be selected"
1832 bool "NWFPE math emulation"
1833 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1835 Say Y to include the NWFPE floating point emulator in the kernel.
1836 This is necessary to run most binaries. Linux does not currently
1837 support floating point hardware so you need to say Y here even if
1838 your machine has an FPA or floating point co-processor podule.
1840 You may say N here if you are going to load the Acorn FPEmulator
1841 early in the bootup.
1844 bool "Support extended precision"
1845 depends on FPE_NWFPE
1847 Say Y to include 80-bit support in the kernel floating-point
1848 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1849 Note that gcc does not generate 80-bit operations by default,
1850 so in most cases this option only enlarges the size of the
1851 floating point emulator without any good reason.
1853 You almost surely want to say N here.
1856 bool "FastFPE math emulation (EXPERIMENTAL)"
1857 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1859 Say Y here to include the FAST floating point emulator in the kernel.
1860 This is an experimental much faster emulator which now also has full
1861 precision for the mantissa. It does not support any exceptions.
1862 It is very simple, and approximately 3-6 times faster than NWFPE.
1864 It should be sufficient for most programs. It may be not suitable
1865 for scientific calculations, but you have to check this for yourself.
1866 If you do not feel you need a faster FP emulation you should better
1870 bool "VFP-format floating point maths"
1871 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1873 Say Y to include VFP support code in the kernel. This is needed
1874 if your hardware includes a VFP unit.
1876 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1877 release notes and additional status information.
1879 Say N if your target does not have VFP hardware.
1887 bool "Advanced SIMD (NEON) Extension support"
1888 depends on VFPv3 && CPU_V7
1890 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1893 config KERNEL_MODE_NEON
1894 bool "Support for NEON in kernel mode"
1895 depends on NEON && AEABI
1897 Say Y to include support for NEON in kernel mode.
1901 menu "Power management options"
1903 source "kernel/power/Kconfig"
1905 config ARCH_SUSPEND_POSSIBLE
1906 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1907 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1910 config ARM_CPU_SUSPEND
1911 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1912 depends on ARCH_SUSPEND_POSSIBLE
1914 config ARCH_HIBERNATION_POSSIBLE
1917 default y if ARCH_SUSPEND_POSSIBLE
1922 source "arch/arm/crypto/Kconfig"
1925 source "arch/arm/Kconfig.assembler"