5 select HAVE_DMA_API_DEBUG
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
33 The ARM series is a line of low-power-consumption RISC chip designs
34 licensed by ARM Ltd and targeted at embedded applications and
35 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
36 manufactured, but legacy ARM-based PC hardware remains popular in
37 Europe. There is an ARM Linux project with a web page at
38 <http://www.arm.linux.org.uk/>.
40 config ARM_HAS_SG_CHAIN
49 config SYS_SUPPORTS_APM_EMULATION
52 config HAVE_SCHED_CLOCK
58 config ARCH_USES_GETTIMEOFFSET
62 config GENERIC_CLOCKEVENTS
65 config GENERIC_CLOCKEVENTS_BROADCAST
67 depends on GENERIC_CLOCKEVENTS
76 select GENERIC_ALLOCATOR
87 The Extended Industry Standard Architecture (EISA) bus was
88 developed as an open alternative to the IBM MicroChannel bus.
90 The EISA bus provided some of the features of the IBM MicroChannel
91 bus while maintaining backward compatibility with cards made for
92 the older ISA bus. The EISA bus saw limited use between 1988 and
93 1995 when it was made obsolete by the PCI bus.
95 Say Y here if you are building a kernel for an EISA-based machine.
105 MicroChannel Architecture is found in some IBM PS/2 machines and
106 laptops. It is a bus system similar to PCI or ISA. See
107 <file:Documentation/mca.txt> (and especially the web page given
108 there) before attempting to build an MCA bus kernel.
110 config STACKTRACE_SUPPORT
114 config HAVE_LATENCYTOP_SUPPORT
119 config LOCKDEP_SUPPORT
123 config TRACE_IRQFLAGS_SUPPORT
127 config HARDIRQS_SW_RESEND
131 config GENERIC_IRQ_PROBE
135 config GENERIC_LOCKBREAK
138 depends on SMP && PREEMPT
140 config RWSEM_GENERIC_SPINLOCK
144 config RWSEM_XCHGADD_ALGORITHM
147 config ARCH_HAS_ILOG2_U32
150 config ARCH_HAS_ILOG2_U64
153 config ARCH_HAS_CPUFREQ
156 Internal node to signify that the ARCH has CPUFREQ support
157 and that the relevant menu configurations are displayed for
160 config ARCH_HAS_CPU_IDLE_WAIT
163 config GENERIC_HWEIGHT
167 config GENERIC_CALIBRATE_DELAY
171 config ARCH_MAY_HAVE_PC_FDC
177 config NEED_DMA_MAP_STATE
180 config GENERIC_ISA_DMA
191 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
192 default DRAM_BASE if REMAP_VECTORS_TO_RAM
195 The base address of exception vectors.
197 config ARM_PATCH_PHYS_VIRT
198 bool "Patch physical to virtual translations at runtime" if EMBEDDED
200 depends on !XIP_KERNEL && MMU
201 depends on !ARCH_REALVIEW || !SPARSEMEM
203 Patch phys-to-virt and virt-to-phys translation functions at
204 boot and module load time according to the position of the
205 kernel in system memory.
207 This can only be used with non-XIP MMU kernels where the base
208 of physical memory is at a 16MB boundary.
210 Only disable this option if you know that you do not require
211 this feature (eg, building a kernel for a single machine) and
212 you need to shrink the kernel to the minimal size.
214 config NEED_MACH_MEMORY_H
217 Select this when mach/memory.h is required to provide special
218 definitions for this platform. The need for mach/memory.h should
219 be avoided when possible.
222 hex "Physical address of main memory"
223 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 Please provide the physical address corresponding to the
226 location of main memory in your system.
228 source "init/Kconfig"
230 source "kernel/Kconfig.freezer"
235 bool "MMU-based Paged Memory Management Support"
238 Select if you want MMU-based virtualised addressing space
239 support by paged memory management. If unsure, say 'Y'.
242 # The "ARM system type" choice list is ordered alphabetically by option
243 # text. Please add new entries in the option alphabetic order.
246 prompt "ARM system type"
247 default ARCH_VERSATILE
249 config ARCH_INTEGRATOR
250 bool "ARM Ltd. Integrator family"
252 select ARCH_HAS_CPUFREQ
254 select HAVE_MACH_CLKDEV
256 select GENERIC_CLOCKEVENTS
257 select PLAT_VERSATILE
258 select PLAT_VERSATILE_FPGA_IRQ
259 select NEED_MACH_MEMORY_H
261 Support for ARM's Integrator platform.
264 bool "ARM Ltd. RealView family"
267 select HAVE_MACH_CLKDEV
269 select GENERIC_CLOCKEVENTS
270 select ARCH_WANT_OPTIONAL_GPIOLIB
271 select PLAT_VERSATILE
272 select PLAT_VERSATILE_CLCD
273 select ARM_TIMER_SP804
274 select GPIO_PL061 if GPIOLIB
275 select NEED_MACH_MEMORY_H
277 This enables support for ARM Ltd RealView boards.
279 config ARCH_VERSATILE
280 bool "ARM Ltd. Versatile family"
284 select HAVE_MACH_CLKDEV
286 select GENERIC_CLOCKEVENTS
287 select ARCH_WANT_OPTIONAL_GPIOLIB
288 select PLAT_VERSATILE
289 select PLAT_VERSATILE_CLCD
290 select PLAT_VERSATILE_FPGA_IRQ
291 select ARM_TIMER_SP804
293 This enables support for ARM Ltd Versatile board.
296 bool "ARM Ltd. Versatile Express family"
297 select ARCH_WANT_OPTIONAL_GPIOLIB
299 select ARM_TIMER_SP804
301 select HAVE_MACH_CLKDEV
302 select GENERIC_CLOCKEVENTS
304 select HAVE_PATA_PLATFORM
306 select PLAT_VERSATILE
307 select PLAT_VERSATILE_CLCD
309 This enables support for the ARM Ltd Versatile Express boards.
313 select ARCH_REQUIRE_GPIOLIB
317 This enables support for systems based on the Atmel AT91RM9200,
318 AT91SAM9 and AT91CAP9 processors.
321 bool "Broadcom BCMRING"
325 select ARM_TIMER_SP804
327 select GENERIC_CLOCKEVENTS
328 select ARCH_WANT_OPTIONAL_GPIOLIB
330 Support for Broadcom's BCMRing platform.
333 bool "Cirrus Logic CLPS711x/EP721x-based"
335 select ARCH_USES_GETTIMEOFFSET
336 select NEED_MACH_MEMORY_H
338 Support for Cirrus Logic 711x/721x based boards.
341 bool "Cavium Networks CNS3XXX family"
343 select GENERIC_CLOCKEVENTS
345 select MIGHT_HAVE_PCI
346 select PCI_DOMAINS if PCI
348 Support for Cavium Networks CNS3XXX platform.
351 bool "Cortina Systems Gemini"
353 select ARCH_REQUIRE_GPIOLIB
354 select ARCH_USES_GETTIMEOFFSET
356 Support for the Cortina Systems Gemini family SoCs
359 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
363 select GENERIC_CLOCKEVENTS
365 select GENERIC_IRQ_CHIP
369 Support for CSR SiRFSoC ARM Cortex A9 Platform
376 select ARCH_USES_GETTIMEOFFSET
377 select NEED_MACH_MEMORY_H
379 This is an evaluation board for the StrongARM processor available
380 from Digital. It has limited hardware on-board, including an
381 Ethernet interface, two PCMCIA sockets, two serial ports and a
390 select ARCH_REQUIRE_GPIOLIB
391 select ARCH_HAS_HOLES_MEMORYMODEL
392 select ARCH_USES_GETTIMEOFFSET
395 This enables support for the Cirrus EP93xx series of CPUs.
397 config ARCH_FOOTBRIDGE
401 select GENERIC_CLOCKEVENTS
402 select NEED_MACH_MEMORY_H
404 Support for systems based on the DC21285 companion chip
405 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
408 bool "Freescale MXC/iMX-based"
409 select GENERIC_CLOCKEVENTS
410 select ARCH_REQUIRE_GPIOLIB
413 select GENERIC_IRQ_CHIP
414 select HAVE_SCHED_CLOCK
416 Support for Freescale MXC/iMX-based family of processors
419 bool "Freescale MXS-based"
420 select GENERIC_CLOCKEVENTS
421 select ARCH_REQUIRE_GPIOLIB
425 Support for Freescale MXS-based family of processors
428 bool "Hilscher NetX based"
432 select GENERIC_CLOCKEVENTS
434 This enables support for systems based on the Hilscher NetX Soc
437 bool "Hynix HMS720x-based"
440 select ARCH_USES_GETTIMEOFFSET
442 This enables support for systems based on the Hynix HMS720x
450 select ARCH_SUPPORTS_MSI
452 select NEED_MACH_MEMORY_H
454 Support for Intel's IOP13XX (XScale) family of processors.
462 select ARCH_REQUIRE_GPIOLIB
464 Support for Intel's 80219 and IOP32X (XScale) family of
473 select ARCH_REQUIRE_GPIOLIB
475 Support for Intel's IOP33X (XScale) family of processors.
482 select ARCH_USES_GETTIMEOFFSET
483 select NEED_MACH_MEMORY_H
485 Support for Intel's IXP23xx (XScale) family of processors.
488 bool "IXP2400/2800-based"
492 select ARCH_USES_GETTIMEOFFSET
493 select NEED_MACH_MEMORY_H
495 Support for Intel's IXP2400/2800 (XScale) family of processors.
503 select GENERIC_CLOCKEVENTS
504 select HAVE_SCHED_CLOCK
505 select MIGHT_HAVE_PCI
506 select DMABOUNCE if PCI
508 Support for Intel's IXP4XX (XScale) family of processors.
514 select ARCH_REQUIRE_GPIOLIB
515 select GENERIC_CLOCKEVENTS
518 Support for the Marvell Dove SoC 88AP510
521 bool "Marvell Kirkwood"
524 select ARCH_REQUIRE_GPIOLIB
525 select GENERIC_CLOCKEVENTS
528 Support for the following Marvell Kirkwood series SoCs:
529 88F6180, 88F6192 and 88F6281.
535 select ARCH_REQUIRE_GPIOLIB
538 select USB_ARCH_HAS_OHCI
541 select GENERIC_CLOCKEVENTS
543 Support for the NXP LPC32XX family of processors
546 bool "Marvell MV78xx0"
549 select ARCH_REQUIRE_GPIOLIB
550 select GENERIC_CLOCKEVENTS
553 Support for the following Marvell MV78xx0 series SoCs:
561 select ARCH_REQUIRE_GPIOLIB
562 select GENERIC_CLOCKEVENTS
565 Support for the following Marvell Orion 5x series SoCs:
566 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
567 Orion-2 (5281), Orion-1-90 (6183).
570 bool "Marvell PXA168/910/MMP2"
572 select ARCH_REQUIRE_GPIOLIB
574 select GENERIC_CLOCKEVENTS
575 select HAVE_SCHED_CLOCK
580 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
583 bool "Micrel/Kendin KS8695"
585 select ARCH_REQUIRE_GPIOLIB
586 select ARCH_USES_GETTIMEOFFSET
587 select NEED_MACH_MEMORY_H
589 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
590 System-on-Chip devices.
593 bool "Nuvoton W90X900 CPU"
595 select ARCH_REQUIRE_GPIOLIB
598 select GENERIC_CLOCKEVENTS
600 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
601 At present, the w90x900 has been renamed nuc900, regarding
602 the ARM series product line, you can login the following
603 link address to know more.
605 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
606 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
609 bool "Nuvoton NUC93X CPU"
613 Support for Nuvoton (Winbond logic dept.) NUC93X MCU,The NUC93X is a
614 low-power and high performance MPEG-4/JPEG multimedia controller chip.
621 select GENERIC_CLOCKEVENTS
624 select HAVE_SCHED_CLOCK
625 select ARCH_HAS_CPUFREQ
627 This enables support for NVIDIA Tegra based systems (Tegra APX,
628 Tegra 6xx and Tegra 2 series).
631 bool "Philips Nexperia PNX4008 Mobile"
634 select ARCH_USES_GETTIMEOFFSET
636 This enables support for Philips PNX4008 mobile platform.
639 bool "PXA2xx/PXA3xx-based"
642 select ARCH_HAS_CPUFREQ
645 select ARCH_REQUIRE_GPIOLIB
646 select GENERIC_CLOCKEVENTS
647 select HAVE_SCHED_CLOCK
652 select MULTI_IRQ_HANDLER
654 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
659 select GENERIC_CLOCKEVENTS
660 select ARCH_REQUIRE_GPIOLIB
663 Support for Qualcomm MSM/QSD based systems. This runs on the
664 apps processor of the MSM/QSD and depends on a shared memory
665 interface to the modem processor which runs the baseband
666 stack and controls some vital subsystems
667 (clock and power control, etc).
670 bool "Renesas SH-Mobile / R-Mobile"
673 select HAVE_MACH_CLKDEV
674 select GENERIC_CLOCKEVENTS
677 select MULTI_IRQ_HANDLER
678 select PM_GENERIC_DOMAINS if PM
679 select NEED_MACH_MEMORY_H
681 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
688 select ARCH_MAY_HAVE_PC_FDC
689 select HAVE_PATA_PLATFORM
692 select ARCH_SPARSEMEM_ENABLE
693 select ARCH_USES_GETTIMEOFFSET
694 select NEED_MACH_MEMORY_H
696 On the Acorn Risc-PC, Linux can support the internal IDE disk and
697 CD-ROM interface, serial and parallel port, and the floppy drive.
704 select ARCH_SPARSEMEM_ENABLE
706 select ARCH_HAS_CPUFREQ
708 select GENERIC_CLOCKEVENTS
710 select HAVE_SCHED_CLOCK
712 select ARCH_REQUIRE_GPIOLIB
713 select NEED_MACH_MEMORY_H
715 Support for StrongARM 11x0 based boards.
718 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
720 select ARCH_HAS_CPUFREQ
723 select ARCH_USES_GETTIMEOFFSET
724 select HAVE_S3C2410_I2C if I2C
726 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
727 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
728 the Samsung SMDK2410 development board (and derivatives).
730 Note, the S3C2416 and the S3C2450 are so close that they even share
731 the same SoC ID code. This means that there is no separate machine
732 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
735 bool "Samsung S3C64XX"
742 select ARCH_USES_GETTIMEOFFSET
743 select ARCH_HAS_CPUFREQ
744 select ARCH_REQUIRE_GPIOLIB
745 select SAMSUNG_CLKSRC
746 select SAMSUNG_IRQ_VIC_TIMER
747 select SAMSUNG_IRQ_UART
748 select S3C_GPIO_TRACK
749 select S3C_GPIO_PULL_UPDOWN
750 select S3C_GPIO_CFG_S3C24XX
751 select S3C_GPIO_CFG_S3C64XX
753 select USB_ARCH_HAS_OHCI
754 select SAMSUNG_GPIOLIB_4BIT
755 select HAVE_S3C2410_I2C if I2C
756 select HAVE_S3C2410_WATCHDOG if WATCHDOG
758 Samsung S3C64XX series based systems
761 bool "Samsung S5P6440 S5P6450"
767 select HAVE_S3C2410_WATCHDOG if WATCHDOG
768 select GENERIC_CLOCKEVENTS
769 select HAVE_SCHED_CLOCK
770 select HAVE_S3C2410_I2C if I2C
771 select HAVE_S3C_RTC if RTC_CLASS
773 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
777 bool "Samsung S5PC100"
782 select ARM_L1_CACHE_SHIFT_6
783 select ARCH_USES_GETTIMEOFFSET
784 select HAVE_S3C2410_I2C if I2C
785 select HAVE_S3C_RTC if RTC_CLASS
786 select HAVE_S3C2410_WATCHDOG if WATCHDOG
788 Samsung S5PC100 series based systems
791 bool "Samsung S5PV210/S5PC110"
793 select ARCH_SPARSEMEM_ENABLE
794 select ARCH_HAS_HOLES_MEMORYMODEL
799 select ARM_L1_CACHE_SHIFT_6
800 select ARCH_HAS_CPUFREQ
801 select GENERIC_CLOCKEVENTS
802 select HAVE_SCHED_CLOCK
803 select HAVE_S3C2410_I2C if I2C
804 select HAVE_S3C_RTC if RTC_CLASS
805 select HAVE_S3C2410_WATCHDOG if WATCHDOG
806 select NEED_MACH_MEMORY_H
808 Samsung S5PV210/S5PC110 series based systems
811 bool "Samsung EXYNOS4"
813 select ARCH_SPARSEMEM_ENABLE
814 select ARCH_HAS_HOLES_MEMORYMODEL
818 select ARCH_HAS_CPUFREQ
819 select GENERIC_CLOCKEVENTS
820 select HAVE_S3C_RTC if RTC_CLASS
821 select HAVE_S3C2410_I2C if I2C
822 select HAVE_S3C2410_WATCHDOG if WATCHDOG
823 select NEED_MACH_MEMORY_H
825 Samsung EXYNOS4 series based systems
834 select ARCH_USES_GETTIMEOFFSET
835 select NEED_MACH_MEMORY_H
837 Support for the StrongARM based Digital DNARD machine, also known
838 as "Shark" (<http://www.shark-linux.de/shark.html>).
841 bool "Telechips TCC ARM926-based systems"
846 select GENERIC_CLOCKEVENTS
848 Support for Telechips TCC ARM926-based systems.
851 bool "ST-Ericsson U300 Series"
855 select HAVE_SCHED_CLOCK
859 select GENERIC_CLOCKEVENTS
861 select HAVE_MACH_CLKDEV
863 select ARCH_REQUIRE_GPIOLIB
864 select NEED_MACH_MEMORY_H
866 Support for ST-Ericsson U300 series mobile platforms.
869 bool "ST-Ericsson U8500 Series"
872 select GENERIC_CLOCKEVENTS
874 select ARCH_REQUIRE_GPIOLIB
875 select ARCH_HAS_CPUFREQ
877 Support for ST-Ericsson's Ux500 architecture
880 bool "STMicroelectronics Nomadik"
885 select GENERIC_CLOCKEVENTS
886 select ARCH_REQUIRE_GPIOLIB
888 Support for the Nomadik platform by ST-Ericsson
892 select GENERIC_CLOCKEVENTS
893 select ARCH_REQUIRE_GPIOLIB
897 select GENERIC_ALLOCATOR
898 select GENERIC_IRQ_CHIP
899 select ARCH_HAS_HOLES_MEMORYMODEL
901 Support for TI's DaVinci platform.
906 select ARCH_REQUIRE_GPIOLIB
907 select ARCH_HAS_CPUFREQ
909 select GENERIC_CLOCKEVENTS
910 select HAVE_SCHED_CLOCK
911 select ARCH_HAS_HOLES_MEMORYMODEL
913 Support for TI's OMAP platform (OMAP1/2/3/4).
918 select ARCH_REQUIRE_GPIOLIB
921 select GENERIC_CLOCKEVENTS
924 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
927 bool "VIA/WonderMedia 85xx"
930 select ARCH_HAS_CPUFREQ
931 select GENERIC_CLOCKEVENTS
932 select ARCH_REQUIRE_GPIOLIB
935 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
938 bool "Xilinx Zynq ARM Cortex A9 Platform"
941 select GENERIC_CLOCKEVENTS
948 Support for Xilinx Zynq ARM Cortex A9 Platform
952 # This is sorted alphabetically by mach-* pathname. However, plat-*
953 # Kconfigs may be included either alphabetically (according to the
954 # plat- suffix) or along side the corresponding mach-* source.
956 source "arch/arm/mach-at91/Kconfig"
958 source "arch/arm/mach-bcmring/Kconfig"
960 source "arch/arm/mach-clps711x/Kconfig"
962 source "arch/arm/mach-cns3xxx/Kconfig"
964 source "arch/arm/mach-davinci/Kconfig"
966 source "arch/arm/mach-dove/Kconfig"
968 source "arch/arm/mach-ep93xx/Kconfig"
970 source "arch/arm/mach-footbridge/Kconfig"
972 source "arch/arm/mach-gemini/Kconfig"
974 source "arch/arm/mach-h720x/Kconfig"
976 source "arch/arm/mach-integrator/Kconfig"
978 source "arch/arm/mach-iop32x/Kconfig"
980 source "arch/arm/mach-iop33x/Kconfig"
982 source "arch/arm/mach-iop13xx/Kconfig"
984 source "arch/arm/mach-ixp4xx/Kconfig"
986 source "arch/arm/mach-ixp2000/Kconfig"
988 source "arch/arm/mach-ixp23xx/Kconfig"
990 source "arch/arm/mach-kirkwood/Kconfig"
992 source "arch/arm/mach-ks8695/Kconfig"
994 source "arch/arm/mach-lpc32xx/Kconfig"
996 source "arch/arm/mach-msm/Kconfig"
998 source "arch/arm/mach-mv78xx0/Kconfig"
1000 source "arch/arm/plat-mxc/Kconfig"
1002 source "arch/arm/mach-mxs/Kconfig"
1004 source "arch/arm/mach-netx/Kconfig"
1006 source "arch/arm/mach-nomadik/Kconfig"
1007 source "arch/arm/plat-nomadik/Kconfig"
1009 source "arch/arm/mach-nuc93x/Kconfig"
1011 source "arch/arm/plat-omap/Kconfig"
1013 source "arch/arm/mach-omap1/Kconfig"
1015 source "arch/arm/mach-omap2/Kconfig"
1017 source "arch/arm/mach-orion5x/Kconfig"
1019 source "arch/arm/mach-pxa/Kconfig"
1020 source "arch/arm/plat-pxa/Kconfig"
1022 source "arch/arm/mach-mmp/Kconfig"
1024 source "arch/arm/mach-realview/Kconfig"
1026 source "arch/arm/mach-sa1100/Kconfig"
1028 source "arch/arm/plat-samsung/Kconfig"
1029 source "arch/arm/plat-s3c24xx/Kconfig"
1030 source "arch/arm/plat-s5p/Kconfig"
1032 source "arch/arm/plat-spear/Kconfig"
1034 source "arch/arm/plat-tcc/Kconfig"
1037 source "arch/arm/mach-s3c2410/Kconfig"
1038 source "arch/arm/mach-s3c2412/Kconfig"
1039 source "arch/arm/mach-s3c2416/Kconfig"
1040 source "arch/arm/mach-s3c2440/Kconfig"
1041 source "arch/arm/mach-s3c2443/Kconfig"
1045 source "arch/arm/mach-s3c64xx/Kconfig"
1048 source "arch/arm/mach-s5p64x0/Kconfig"
1050 source "arch/arm/mach-s5pc100/Kconfig"
1052 source "arch/arm/mach-s5pv210/Kconfig"
1054 source "arch/arm/mach-exynos4/Kconfig"
1056 source "arch/arm/mach-shmobile/Kconfig"
1058 source "arch/arm/mach-tegra/Kconfig"
1060 source "arch/arm/mach-u300/Kconfig"
1062 source "arch/arm/mach-ux500/Kconfig"
1064 source "arch/arm/mach-versatile/Kconfig"
1066 source "arch/arm/mach-vexpress/Kconfig"
1067 source "arch/arm/plat-versatile/Kconfig"
1069 source "arch/arm/mach-vt8500/Kconfig"
1071 source "arch/arm/mach-w90x900/Kconfig"
1073 # Definitions to make life easier
1079 select GENERIC_CLOCKEVENTS
1080 select HAVE_SCHED_CLOCK
1085 select GENERIC_IRQ_CHIP
1086 select HAVE_SCHED_CLOCK
1091 config PLAT_VERSATILE
1094 config ARM_TIMER_SP804
1098 source arch/arm/mm/Kconfig
1101 bool "Enable iWMMXt support"
1102 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1103 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1105 Enable support for iWMMXt context switching at run time if
1106 running on a CPU that supports it.
1108 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1111 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1115 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1116 (!ARCH_OMAP3 || OMAP3_EMU)
1120 config MULTI_IRQ_HANDLER
1123 Allow each machine to specify it's own IRQ handler at run time.
1126 source "arch/arm/Kconfig-nommu"
1129 config ARM_ERRATA_411920
1130 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1131 depends on CPU_V6 || CPU_V6K
1133 Invalidation of the Instruction Cache operation can
1134 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1135 It does not affect the MPCore. This option enables the ARM Ltd.
1136 recommended workaround.
1138 config ARM_ERRATA_430973
1139 bool "ARM errata: Stale prediction on replaced interworking branch"
1142 This option enables the workaround for the 430973 Cortex-A8
1143 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1144 interworking branch is replaced with another code sequence at the
1145 same virtual address, whether due to self-modifying code or virtual
1146 to physical address re-mapping, Cortex-A8 does not recover from the
1147 stale interworking branch prediction. This results in Cortex-A8
1148 executing the new code sequence in the incorrect ARM or Thumb state.
1149 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1150 and also flushes the branch target cache at every context switch.
1151 Note that setting specific bits in the ACTLR register may not be
1152 available in non-secure mode.
1154 config ARM_ERRATA_458693
1155 bool "ARM errata: Processor deadlock when a false hazard is created"
1158 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1159 erratum. For very specific sequences of memory operations, it is
1160 possible for a hazard condition intended for a cache line to instead
1161 be incorrectly associated with a different cache line. This false
1162 hazard might then cause a processor deadlock. The workaround enables
1163 the L1 caching of the NEON accesses and disables the PLD instruction
1164 in the ACTLR register. Note that setting specific bits in the ACTLR
1165 register may not be available in non-secure mode.
1167 config ARM_ERRATA_460075
1168 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1171 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1172 erratum. Any asynchronous access to the L2 cache may encounter a
1173 situation in which recent store transactions to the L2 cache are lost
1174 and overwritten with stale memory contents from external memory. The
1175 workaround disables the write-allocate mode for the L2 cache via the
1176 ACTLR register. Note that setting specific bits in the ACTLR register
1177 may not be available in non-secure mode.
1179 config ARM_ERRATA_742230
1180 bool "ARM errata: DMB operation may be faulty"
1181 depends on CPU_V7 && SMP
1183 This option enables the workaround for the 742230 Cortex-A9
1184 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1185 between two write operations may not ensure the correct visibility
1186 ordering of the two writes. This workaround sets a specific bit in
1187 the diagnostic register of the Cortex-A9 which causes the DMB
1188 instruction to behave as a DSB, ensuring the correct behaviour of
1191 config ARM_ERRATA_742231
1192 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1193 depends on CPU_V7 && SMP
1195 This option enables the workaround for the 742231 Cortex-A9
1196 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1197 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1198 accessing some data located in the same cache line, may get corrupted
1199 data due to bad handling of the address hazard when the line gets
1200 replaced from one of the CPUs at the same time as another CPU is
1201 accessing it. This workaround sets specific bits in the diagnostic
1202 register of the Cortex-A9 which reduces the linefill issuing
1203 capabilities of the processor.
1205 config PL310_ERRATA_588369
1206 bool "Clean & Invalidate maintenance operations do not invalidate clean lines"
1207 depends on CACHE_L2X0
1209 The PL310 L2 cache controller implements three types of Clean &
1210 Invalidate maintenance operations: by Physical Address
1211 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1212 They are architecturally defined to behave as the execution of a
1213 clean operation followed immediately by an invalidate operation,
1214 both performing to the same memory location. This functionality
1215 is not correctly implemented in PL310 as clean lines are not
1216 invalidated as a result of these operations.
1218 config ARM_ERRATA_720789
1219 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1220 depends on CPU_V7 && SMP
1222 This option enables the workaround for the 720789 Cortex-A9 (prior to
1223 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1224 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1225 As a consequence of this erratum, some TLB entries which should be
1226 invalidated are not, resulting in an incoherency in the system page
1227 tables. The workaround changes the TLB flushing routines to invalidate
1228 entries regardless of the ASID.
1230 config PL310_ERRATA_727915
1231 bool "Background Clean & Invalidate by Way operation can cause data corruption"
1232 depends on CACHE_L2X0
1234 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1235 operation (offset 0x7FC). This operation runs in background so that
1236 PL310 can handle normal accesses while it is in progress. Under very
1237 rare circumstances, due to this erratum, write data can be lost when
1238 PL310 treats a cacheable write transaction during a Clean &
1239 Invalidate by Way operation.
1241 config ARM_ERRATA_743622
1242 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1245 This option enables the workaround for the 743622 Cortex-A9
1246 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1247 optimisation in the Cortex-A9 Store Buffer may lead to data
1248 corruption. This workaround sets a specific bit in the diagnostic
1249 register of the Cortex-A9 which disables the Store Buffer
1250 optimisation, preventing the defect from occurring. This has no
1251 visible impact on the overall performance or power consumption of the
1254 config ARM_ERRATA_751472
1255 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1256 depends on CPU_V7 && SMP
1258 This option enables the workaround for the 751472 Cortex-A9 (prior
1259 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1260 completion of a following broadcasted operation if the second
1261 operation is received by a CPU before the ICIALLUIS has completed,
1262 potentially leading to corrupted entries in the cache or TLB.
1264 config ARM_ERRATA_753970
1265 bool "ARM errata: cache sync operation may be faulty"
1266 depends on CACHE_PL310
1268 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1270 Under some condition the effect of cache sync operation on
1271 the store buffer still remains when the operation completes.
1272 This means that the store buffer is always asked to drain and
1273 this prevents it from merging any further writes. The workaround
1274 is to replace the normal offset of cache sync operation (0x730)
1275 by another offset targeting an unmapped PL310 register 0x740.
1276 This has the same effect as the cache sync operation: store buffer
1277 drain and waiting for all buffers empty.
1279 config ARM_ERRATA_754322
1280 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1283 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1284 r3p*) erratum. A speculative memory access may cause a page table walk
1285 which starts prior to an ASID switch but completes afterwards. This
1286 can populate the micro-TLB with a stale entry which may be hit with
1287 the new ASID. This workaround places two dsb instructions in the mm
1288 switching code so that no page table walks can cross the ASID switch.
1290 config ARM_ERRATA_754327
1291 bool "ARM errata: no automatic Store Buffer drain"
1292 depends on CPU_V7 && SMP
1294 This option enables the workaround for the 754327 Cortex-A9 (prior to
1295 r2p0) erratum. The Store Buffer does not have any automatic draining
1296 mechanism and therefore a livelock may occur if an external agent
1297 continuously polls a memory location waiting to observe an update.
1298 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1299 written polling loops from denying visibility of updates to memory.
1301 config ARM_ERRATA_364296
1302 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1303 depends on CPU_V6 && !SMP
1305 This options enables the workaround for the 364296 ARM1136
1306 r0p2 erratum (possible cache data corruption with
1307 hit-under-miss enabled). It sets the undocumented bit 31 in
1308 the auxiliary control register and the FI bit in the control
1309 register, thus disabling hit-under-miss without putting the
1310 processor into full low interrupt latency mode. ARM11MPCore
1313 config ARM_ERRATA_764369
1314 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1315 depends on CPU_V7 && SMP
1317 This option enables the workaround for erratum 764369
1318 affecting Cortex-A9 MPCore with two or more processors (all
1319 current revisions). Under certain timing circumstances, a data
1320 cache line maintenance operation by MVA targeting an Inner
1321 Shareable memory region may fail to proceed up to either the
1322 Point of Coherency or to the Point of Unification of the
1323 system. This workaround adds a DSB instruction before the
1324 relevant cache maintenance functions and sets a specific bit
1325 in the diagnostic control register of the SCU.
1329 source "arch/arm/common/Kconfig"
1339 Find out whether you have ISA slots on your motherboard. ISA is the
1340 name of a bus system, i.e. the way the CPU talks to the other stuff
1341 inside your box. Other bus systems are PCI, EISA, MicroChannel
1342 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1343 newer boards don't support it. If you have ISA, say Y, otherwise N.
1345 # Select ISA DMA controller support
1350 # Select ISA DMA interface
1355 bool "PCI support" if MIGHT_HAVE_PCI
1357 Find out whether you have a PCI motherboard. PCI is the name of a
1358 bus system, i.e. the way the CPU talks to the other stuff inside
1359 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1360 VESA. If you have PCI, say Y, otherwise N.
1366 config PCI_NANOENGINE
1367 bool "BSE nanoEngine PCI support"
1368 depends on SA1100_NANOENGINE
1370 Enable PCI on the BSE nanoEngine board.
1375 # Select the host bridge type
1376 config PCI_HOST_VIA82C505
1378 depends on PCI && ARCH_SHARK
1381 config PCI_HOST_ITE8152
1383 depends on PCI && MACH_ARMCORE
1387 source "drivers/pci/Kconfig"
1389 source "drivers/pcmcia/Kconfig"
1393 menu "Kernel Features"
1395 source "kernel/time/Kconfig"
1398 bool "Symmetric Multi-Processing"
1399 depends on CPU_V6K || CPU_V7
1400 depends on GENERIC_CLOCKEVENTS
1401 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1402 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1403 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1404 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
1405 select USE_GENERIC_SMP_HELPERS
1406 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1408 This enables support for systems with more than one CPU. If you have
1409 a system with only one CPU, like most personal computers, say N. If
1410 you have a system with more than one CPU, say Y.
1412 If you say N here, the kernel will run on single and multiprocessor
1413 machines, but will use only one CPU of a multiprocessor machine. If
1414 you say Y here, the kernel will run on many, but not all, single
1415 processor machines. On a single processor machine, the kernel will
1416 run faster if you say N here.
1418 See also <file:Documentation/i386/IO-APIC.txt>,
1419 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1420 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1422 If you don't know what to do here, say N.
1425 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1426 depends on EXPERIMENTAL
1427 depends on SMP && !XIP_KERNEL
1430 SMP kernels contain instructions which fail on non-SMP processors.
1431 Enabling this option allows the kernel to modify itself to make
1432 these instructions safe. Disabling it allows about 1K of space
1435 If you don't know what to do here, say Y.
1440 This option enables support for the ARM system coherency unit
1447 This options enables support for the ARM timer and watchdog unit
1450 prompt "Memory split"
1453 Select the desired split between kernel and user memory.
1455 If you are not absolutely sure what you are doing, leave this
1459 bool "3G/1G user/kernel split"
1461 bool "2G/2G user/kernel split"
1463 bool "1G/3G user/kernel split"
1468 default 0x40000000 if VMSPLIT_1G
1469 default 0x80000000 if VMSPLIT_2G
1473 int "Maximum number of CPUs (2-32)"
1479 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1480 depends on SMP && HOTPLUG && EXPERIMENTAL
1482 Say Y here to experiment with turning CPUs off and on. CPUs
1483 can be controlled through /sys/devices/system/cpu.
1486 bool "Use local timer interrupts"
1489 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1491 Enable support for local timers on SMP platforms, rather then the
1492 legacy IPI broadcast method. Local timers allows the system
1493 accounting to be spread across the timer interval, preventing a
1494 "thundering herd" at every timer tick.
1496 source kernel/Kconfig.preempt
1500 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1501 ARCH_S5PV210 || ARCH_EXYNOS4
1502 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1503 default AT91_TIMER_HZ if ARCH_AT91
1504 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1507 config THUMB2_KERNEL
1508 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1509 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1511 select ARM_ASM_UNIFIED
1513 By enabling this option, the kernel will be compiled in
1514 Thumb-2 mode. A compiler/assembler that understand the unified
1515 ARM-Thumb syntax is needed.
1519 config THUMB2_AVOID_R_ARM_THM_JUMP11
1520 bool "Work around buggy Thumb-2 short branch relocations in gas"
1521 depends on THUMB2_KERNEL && MODULES
1524 Various binutils versions can resolve Thumb-2 branches to
1525 locally-defined, preemptible global symbols as short-range "b.n"
1526 branch instructions.
1528 This is a problem, because there's no guarantee the final
1529 destination of the symbol, or any candidate locations for a
1530 trampoline, are within range of the branch. For this reason, the
1531 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1532 relocation in modules at all, and it makes little sense to add
1535 The symptom is that the kernel fails with an "unsupported
1536 relocation" error when loading some modules.
1538 Until fixed tools are available, passing
1539 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1540 code which hits this problem, at the cost of a bit of extra runtime
1541 stack usage in some cases.
1543 The problem is described in more detail at:
1544 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1546 Only Thumb-2 kernels are affected.
1548 Unless you are sure your tools don't have this problem, say Y.
1550 config ARM_ASM_UNIFIED
1554 bool "Use the ARM EABI to compile the kernel"
1556 This option allows for the kernel to be compiled using the latest
1557 ARM ABI (aka EABI). This is only useful if you are using a user
1558 space environment that is also compiled with EABI.
1560 Since there are major incompatibilities between the legacy ABI and
1561 EABI, especially with regard to structure member alignment, this
1562 option also changes the kernel syscall calling convention to
1563 disambiguate both ABIs and allow for backward compatibility support
1564 (selected with CONFIG_OABI_COMPAT).
1566 To use this you need GCC version 4.0.0 or later.
1569 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1570 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1573 This option preserves the old syscall interface along with the
1574 new (ARM EABI) one. It also provides a compatibility layer to
1575 intercept syscalls that have structure arguments which layout
1576 in memory differs between the legacy ABI and the new ARM EABI
1577 (only for non "thumb" binaries). This option adds a tiny
1578 overhead to all syscalls and produces a slightly larger kernel.
1579 If you know you'll be using only pure EABI user space then you
1580 can say N here. If this option is not selected and you attempt
1581 to execute a legacy ABI binary then the result will be
1582 UNPREDICTABLE (in fact it can be predicted that it won't work
1583 at all). If in doubt say Y.
1585 config ARCH_HAS_HOLES_MEMORYMODEL
1588 config ARCH_SPARSEMEM_ENABLE
1591 config ARCH_SPARSEMEM_DEFAULT
1592 def_bool ARCH_SPARSEMEM_ENABLE
1594 config ARCH_SELECT_MEMORY_MODEL
1595 def_bool ARCH_SPARSEMEM_ENABLE
1597 config HAVE_ARCH_PFN_VALID
1598 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1601 bool "High Memory Support"
1604 The address space of ARM processors is only 4 Gigabytes large
1605 and it has to accommodate user address space, kernel address
1606 space as well as some memory mapped IO. That means that, if you
1607 have a large amount of physical memory and/or IO, not all of the
1608 memory can be "permanently mapped" by the kernel. The physical
1609 memory that is not permanently mapped is called "high memory".
1611 Depending on the selected kernel/user memory split, minimum
1612 vmalloc space and actual amount of RAM, you may not need this
1613 option which should result in a slightly faster kernel.
1618 bool "Allocate 2nd-level pagetables from highmem"
1621 config HW_PERF_EVENTS
1622 bool "Enable hardware performance counter support for perf events"
1623 depends on PERF_EVENTS && CPU_HAS_PMU
1626 Enable hardware performance counter support for perf events. If
1627 disabled, perf events will use software events only.
1631 config FORCE_MAX_ZONEORDER
1632 int "Maximum zone order" if ARCH_SHMOBILE
1633 range 11 64 if ARCH_SHMOBILE
1634 default "9" if SA1111
1637 The kernel memory allocator divides physically contiguous memory
1638 blocks into "zones", where each zone is a power of two number of
1639 pages. This option selects the largest power of two that the kernel
1640 keeps in the memory allocator. If you need to allocate very large
1641 blocks of physically contiguous memory, then you may need to
1642 increase this value.
1644 This config option is actually maximum order plus one. For example,
1645 a value of 11 means that the largest free memory block is 2^10 pages.
1648 bool "Timer and CPU usage LEDs"
1649 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1650 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1651 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1652 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1653 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1654 ARCH_AT91 || ARCH_DAVINCI || \
1655 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1657 If you say Y here, the LEDs on your machine will be used
1658 to provide useful information about your current system status.
1660 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1661 be able to select which LEDs are active using the options below. If
1662 you are compiling a kernel for the EBSA-110 or the LART however, the
1663 red LED will simply flash regularly to indicate that the system is
1664 still functional. It is safe to say Y here if you have a CATS
1665 system, but the driver will do nothing.
1668 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1669 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1670 || MACH_OMAP_PERSEUS2
1672 depends on !GENERIC_CLOCKEVENTS
1673 default y if ARCH_EBSA110
1675 If you say Y here, one of the system LEDs (the green one on the
1676 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1677 will flash regularly to indicate that the system is still
1678 operational. This is mainly useful to kernel hackers who are
1679 debugging unstable kernels.
1681 The LART uses the same LED for both Timer LED and CPU usage LED
1682 functions. You may choose to use both, but the Timer LED function
1683 will overrule the CPU usage LED.
1686 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1688 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1689 || MACH_OMAP_PERSEUS2
1692 If you say Y here, the red LED will be used to give a good real
1693 time indication of CPU usage, by lighting whenever the idle task
1694 is not currently executing.
1696 The LART uses the same LED for both Timer LED and CPU usage LED
1697 functions. You may choose to use both, but the Timer LED function
1698 will overrule the CPU usage LED.
1700 config ALIGNMENT_TRAP
1702 depends on CPU_CP15_MMU
1703 default y if !ARCH_EBSA110
1704 select HAVE_PROC_CPU if PROC_FS
1706 ARM processors cannot fetch/store information which is not
1707 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1708 address divisible by 4. On 32-bit ARM processors, these non-aligned
1709 fetch/store instructions will be emulated in software if you say
1710 here, which has a severe performance impact. This is necessary for
1711 correct operation of some network protocols. With an IP-only
1712 configuration it is safe to say N, otherwise say Y.
1714 config UACCESS_WITH_MEMCPY
1715 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1716 depends on MMU && EXPERIMENTAL
1717 default y if CPU_FEROCEON
1719 Implement faster copy_to_user and clear_user methods for CPU
1720 cores where a 8-word STM instruction give significantly higher
1721 memory write throughput than a sequence of individual 32bit stores.
1723 A possible side effect is a slight increase in scheduling latency
1724 between threads sharing the same address space if they invoke
1725 such copy operations with large buffers.
1727 However, if the CPU data cache is using a write-allocate mode,
1728 this option is unlikely to provide any performance gain.
1732 prompt "Enable seccomp to safely compute untrusted bytecode"
1734 This kernel feature is useful for number crunching applications
1735 that may need to compute untrusted bytecode during their
1736 execution. By using pipes or other transports made available to
1737 the process as file descriptors supporting the read/write
1738 syscalls, it's possible to isolate those applications in
1739 their own address space using seccomp. Once seccomp is
1740 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1741 and the task is only allowed to execute a few safe syscalls
1742 defined by each seccomp mode.
1744 config CC_STACKPROTECTOR
1745 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1746 depends on EXPERIMENTAL
1748 This option turns on the -fstack-protector GCC feature. This
1749 feature puts, at the beginning of functions, a canary value on
1750 the stack just before the return address, and validates
1751 the value just before actually returning. Stack based buffer
1752 overflows (that need to overwrite this return address) now also
1753 overwrite the canary, which gets detected and the attack is then
1754 neutralized via a kernel panic.
1755 This feature requires gcc version 4.2 or above.
1757 config DEPRECATED_PARAM_STRUCT
1758 bool "Provide old way to pass kernel parameters"
1760 This was deprecated in 2001 and announced to live on for 5 years.
1761 Some old boot loaders still use this way.
1768 bool "Flattened Device Tree support"
1770 select OF_EARLY_FLATTREE
1773 Include support for flattened device tree machine descriptions.
1775 # Compressed boot loader in ROM. Yes, we really want to ask about
1776 # TEXT and BSS so we preserve their values in the config files.
1777 config ZBOOT_ROM_TEXT
1778 hex "Compressed ROM boot loader base address"
1781 The physical address at which the ROM-able zImage is to be
1782 placed in the target. Platforms which normally make use of
1783 ROM-able zImage formats normally set this to a suitable
1784 value in their defconfig file.
1786 If ZBOOT_ROM is not enabled, this has no effect.
1788 config ZBOOT_ROM_BSS
1789 hex "Compressed ROM boot loader BSS address"
1792 The base address of an area of read/write memory in the target
1793 for the ROM-able zImage which must be available while the
1794 decompressor is running. It must be large enough to hold the
1795 entire decompressed kernel plus an additional 128 KiB.
1796 Platforms which normally make use of ROM-able zImage formats
1797 normally set this to a suitable value in their defconfig file.
1799 If ZBOOT_ROM is not enabled, this has no effect.
1802 bool "Compressed boot loader in ROM/flash"
1803 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1805 Say Y here if you intend to execute your compressed kernel image
1806 (zImage) directly from ROM or flash. If unsure, say N.
1809 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1810 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1811 default ZBOOT_ROM_NONE
1813 Include experimental SD/MMC loading code in the ROM-able zImage.
1814 With this enabled it is possible to write the the ROM-able zImage
1815 kernel image to an MMC or SD card and boot the kernel straight
1816 from the reset vector. At reset the processor Mask ROM will load
1817 the first part of the the ROM-able zImage which in turn loads the
1818 rest the kernel image to RAM.
1820 config ZBOOT_ROM_NONE
1821 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1823 Do not load image from SD or MMC
1825 config ZBOOT_ROM_MMCIF
1826 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1828 Load image from MMCIF hardware block.
1830 config ZBOOT_ROM_SH_MOBILE_SDHI
1831 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1833 Load image from SDHI hardware block
1838 string "Default kernel command string"
1841 On some architectures (EBSA110 and CATS), there is currently no way
1842 for the boot loader to pass arguments to the kernel. For these
1843 architectures, you should supply some command-line options at build
1844 time by entering them here. As a minimum, you should specify the
1845 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1848 prompt "Kernel command line type" if CMDLINE != ""
1849 default CMDLINE_FROM_BOOTLOADER
1851 config CMDLINE_FROM_BOOTLOADER
1852 bool "Use bootloader kernel arguments if available"
1854 Uses the command-line options passed by the boot loader. If
1855 the boot loader doesn't provide any, the default kernel command
1856 string provided in CMDLINE will be used.
1858 config CMDLINE_EXTEND
1859 bool "Extend bootloader kernel arguments"
1861 The command-line arguments provided by the boot loader will be
1862 appended to the default kernel command string.
1864 config CMDLINE_FORCE
1865 bool "Always use the default kernel command string"
1867 Always use the default kernel command string, even if the boot
1868 loader passes other arguments to the kernel.
1869 This is useful if you cannot or don't want to change the
1870 command-line options your boot loader passes to the kernel.
1874 bool "Kernel Execute-In-Place from ROM"
1875 depends on !ZBOOT_ROM
1877 Execute-In-Place allows the kernel to run from non-volatile storage
1878 directly addressable by the CPU, such as NOR flash. This saves RAM
1879 space since the text section of the kernel is not loaded from flash
1880 to RAM. Read-write sections, such as the data section and stack,
1881 are still copied to RAM. The XIP kernel is not compressed since
1882 it has to run directly from flash, so it will take more space to
1883 store it. The flash address used to link the kernel object files,
1884 and for storing it, is configuration dependent. Therefore, if you
1885 say Y here, you must know the proper physical address where to
1886 store the kernel image depending on your own flash memory usage.
1888 Also note that the make target becomes "make xipImage" rather than
1889 "make zImage" or "make Image". The final kernel binary to put in
1890 ROM memory will be arch/arm/boot/xipImage.
1894 config XIP_PHYS_ADDR
1895 hex "XIP Kernel Physical Location"
1896 depends on XIP_KERNEL
1897 default "0x00080000"
1899 This is the physical address in your flash memory the kernel will
1900 be linked for and stored to. This address is dependent on your
1904 bool "Kexec system call (EXPERIMENTAL)"
1905 depends on EXPERIMENTAL
1907 kexec is a system call that implements the ability to shutdown your
1908 current kernel, and to start another kernel. It is like a reboot
1909 but it is independent of the system firmware. And like a reboot
1910 you can start any kernel with it, not just Linux.
1912 It is an ongoing process to be certain the hardware in a machine
1913 is properly shutdown, so do not be surprised if this code does not
1914 initially work for you. It may help to enable device hotplugging
1918 bool "Export atags in procfs"
1922 Should the atags used to boot the kernel be exported in an "atags"
1923 file in procfs. Useful with kexec.
1926 bool "Build kdump crash kernel (EXPERIMENTAL)"
1927 depends on EXPERIMENTAL
1929 Generate crash dump after being started by kexec. This should
1930 be normally only set in special crash dump kernels which are
1931 loaded in the main kernel with kexec-tools into a specially
1932 reserved region and then later executed after a crash by
1933 kdump/kexec. The crash dump kernel must be compiled to a
1934 memory address not used by the main kernel
1936 For more details see Documentation/kdump/kdump.txt
1938 config AUTO_ZRELADDR
1939 bool "Auto calculation of the decompressed kernel image address"
1940 depends on !ZBOOT_ROM && !ARCH_U300
1942 ZRELADDR is the physical address where the decompressed kernel
1943 image will be placed. If AUTO_ZRELADDR is selected, the address
1944 will be determined at run-time by masking the current IP with
1945 0xf8000000. This assumes the zImage being placed in the first 128MB
1946 from start of memory.
1950 menu "CPU Power Management"
1954 source "drivers/cpufreq/Kconfig"
1957 tristate "CPUfreq driver for i.MX CPUs"
1958 depends on ARCH_MXC && CPU_FREQ
1960 This enables the CPUfreq driver for i.MX CPUs.
1962 config CPU_FREQ_SA1100
1965 config CPU_FREQ_SA1110
1968 config CPU_FREQ_INTEGRATOR
1969 tristate "CPUfreq driver for ARM Integrator CPUs"
1970 depends on ARCH_INTEGRATOR && CPU_FREQ
1973 This enables the CPUfreq driver for ARM Integrator CPUs.
1975 For details, take a look at <file:Documentation/cpu-freq>.
1981 depends on CPU_FREQ && ARCH_PXA && PXA25x
1983 select CPU_FREQ_TABLE
1984 select CPU_FREQ_DEFAULT_GOV_USERSPACE
1989 Internal configuration node for common cpufreq on Samsung SoC
1991 config CPU_FREQ_S3C24XX
1992 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
1993 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
1996 This enables the CPUfreq driver for the Samsung S3C24XX family
1999 For details, take a look at <file:Documentation/cpu-freq>.
2003 config CPU_FREQ_S3C24XX_PLL
2004 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2005 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2007 Compile in support for changing the PLL frequency from the
2008 S3C24XX series CPUfreq driver. The PLL takes time to settle
2009 after a frequency change, so by default it is not enabled.
2011 This also means that the PLL tables for the selected CPU(s) will
2012 be built which may increase the size of the kernel image.
2014 config CPU_FREQ_S3C24XX_DEBUG
2015 bool "Debug CPUfreq Samsung driver core"
2016 depends on CPU_FREQ_S3C24XX
2018 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2020 config CPU_FREQ_S3C24XX_IODEBUG
2021 bool "Debug CPUfreq Samsung driver IO timing"
2022 depends on CPU_FREQ_S3C24XX
2024 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2026 config CPU_FREQ_S3C24XX_DEBUGFS
2027 bool "Export debugfs for CPUFreq"
2028 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2030 Export status information via debugfs.
2034 source "drivers/cpuidle/Kconfig"
2038 menu "Floating point emulation"
2040 comment "At least one emulation must be selected"
2043 bool "NWFPE math emulation"
2044 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2046 Say Y to include the NWFPE floating point emulator in the kernel.
2047 This is necessary to run most binaries. Linux does not currently
2048 support floating point hardware so you need to say Y here even if
2049 your machine has an FPA or floating point co-processor podule.
2051 You may say N here if you are going to load the Acorn FPEmulator
2052 early in the bootup.
2055 bool "Support extended precision"
2056 depends on FPE_NWFPE
2058 Say Y to include 80-bit support in the kernel floating-point
2059 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2060 Note that gcc does not generate 80-bit operations by default,
2061 so in most cases this option only enlarges the size of the
2062 floating point emulator without any good reason.
2064 You almost surely want to say N here.
2067 bool "FastFPE math emulation (EXPERIMENTAL)"
2068 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2070 Say Y here to include the FAST floating point emulator in the kernel.
2071 This is an experimental much faster emulator which now also has full
2072 precision for the mantissa. It does not support any exceptions.
2073 It is very simple, and approximately 3-6 times faster than NWFPE.
2075 It should be sufficient for most programs. It may be not suitable
2076 for scientific calculations, but you have to check this for yourself.
2077 If you do not feel you need a faster FP emulation you should better
2081 bool "VFP-format floating point maths"
2082 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2084 Say Y to include VFP support code in the kernel. This is needed
2085 if your hardware includes a VFP unit.
2087 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2088 release notes and additional status information.
2090 Say N if your target does not have VFP hardware.
2098 bool "Advanced SIMD (NEON) Extension support"
2099 depends on VFPv3 && CPU_V7
2101 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2106 menu "Userspace binary formats"
2108 source "fs/Kconfig.binfmt"
2111 tristate "RISC OS personality"
2114 Say Y here to include the kernel code necessary if you want to run
2115 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2116 experimental; if this sounds frightening, say N and sleep in peace.
2117 You can also say M here to compile this support as a module (which
2118 will be called arthur).
2122 menu "Power management options"
2124 source "kernel/power/Kconfig"
2126 config ARCH_SUSPEND_POSSIBLE
2127 depends on !ARCH_S5P64X0 && !ARCH_S5PC100
2128 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2129 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2134 source "net/Kconfig"
2136 source "drivers/Kconfig"
2140 source "arch/arm/Kconfig.debug"
2142 source "security/Kconfig"
2144 source "crypto/Kconfig"
2146 source "lib/Kconfig"