1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
11 imply SPL_SEPARATE_BSS
14 bool "Enable support for CRC32 instruction"
18 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
19 This is faster than software crc32 calculation. This instruction may
20 not be present on all ARMv8.0, but is always present on ARMv8.1 and
23 config COUNTER_FREQUENCY
24 int "Timer clock frequency"
25 depends on ARM64 || CPU_V7A
26 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
27 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
28 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
29 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
30 default 100000000 if ARCH_ZYNQMP
33 For platforms with ARMv8-A and ARMv7-A which features a system
34 counter, those platforms needs software to program the counter
35 frequency. Setup time clock frequency for certain platform.
36 0 means no need to configure the system counter frequency.
37 For platforms needs the frequency set in U-Boot with a
38 pre-defined value, should have the macro defined as a non-zero value.
40 config POSITION_INDEPENDENT
41 bool "Generate position-independent pre-relocation code"
42 depends on ARM64 || CPU_V7A
44 U-Boot expects to be linked to a specific hard-coded address, and to
45 be loaded to and run from that address. This option lifts that
46 restriction, thus allowing the code to be loaded to and executed from
47 almost any 4K aligned address. This logic relies on the relocation
48 information that is embedded in the binary to support U-Boot
49 relocating itself to the top-of-RAM later during execution.
51 config INIT_SP_RELATIVE
52 bool "Specify the early stack pointer relative to the .bss section"
54 default n if ARCH_QEMU
55 default y if POSITION_INDEPENDENT
57 U-Boot typically uses a hard-coded value for the stack pointer
58 before relocation. Enable this option to instead calculate the
59 initial SP at run-time. This is useful to avoid hard-coding addresses
60 into U-Boot, so that it can be loaded and executed at arbitrary
61 addresses and thus avoid using arbitrary addresses at runtime.
63 If this option is enabled, the early stack pointer is set to
64 &_bss_start with a offset value added. The offset is specified by
65 SYS_INIT_SP_BSS_OFFSET.
67 config SYS_INIT_SP_BSS_OFFSET
68 int "Early stack offset from the .bss base address"
70 depends on INIT_SP_RELATIVE
73 This option's value is the offset added to &_bss_start in order to
74 calculate the stack pointer. This offset should be large enough so
75 that the early malloc region, global data (gd), and early stack usage
76 do not overlap any appended DTB.
78 config SPL_SYS_NO_VECTOR_TABLE
82 config LINUX_KERNEL_IMAGE_HEADER
86 Place a Linux kernel image header at the start of the U-Boot binary.
87 The format of the header is described in the Linux kernel source at
88 Documentation/arm64/booting.txt. This feature is useful since the
89 image header reports the amount of memory (BSS and similar) that
90 U-Boot needs to use, but which isn't part of the binary.
92 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
93 depends on LINUX_KERNEL_IMAGE_HEADER
96 The value subtracted from CONFIG_TEXT_BASE to calculate the
97 TEXT_OFFSET value written to the Linux kernel image header.
109 ARM GICV3 Interrupt translation service (ITS).
110 Basic support for programming locality specific peripheral
111 interrupts (LPI) configuration tables and enable LPI tables.
112 LPI configuration table can be used by u-boot or Linux.
113 ARM GICV3 has limitation, once the LPI table is enabled, LPI
114 configuration table can not be re-programmed, unless GICV3 reset.
120 config DMA_ADDR_T_64BIT
130 config GPIO_EXTRA_HEADER
133 # Used for compatibility with asm files copied from the kernel
134 config ARM_ASM_UNIFIED
138 # Used for compatibility with asm files copied from the kernel
142 config SYS_ICACHE_OFF
143 bool "Do not enable icache"
145 Do not enable instruction cache in U-Boot.
147 config SPL_SYS_ICACHE_OFF
148 bool "Do not enable icache in SPL"
150 default SYS_ICACHE_OFF
152 Do not enable instruction cache in SPL.
154 config SYS_DCACHE_OFF
155 bool "Do not enable dcache"
157 Do not enable data cache in U-Boot.
159 config SPL_SYS_DCACHE_OFF
160 bool "Do not enable dcache in SPL"
162 default SYS_DCACHE_OFF
164 Do not enable data cache in SPL.
166 config SYS_ARM_CACHE_CP15
167 bool "CP15 based cache enabling support"
169 Select this if your processor suports enabling caches by using
173 bool "MMU-based Paged Memory Management Support"
174 select SYS_ARM_CACHE_CP15
176 Select if you want MMU-based virtualised addressing space
177 support via paged memory management.
180 bool 'Use the ARM v7 PMSA Compliant MPU'
182 Some ARM systems without an MMU have instead a Memory Protection
183 Unit (MPU) that defines the type and permissions for regions of
185 If your CPU has an MPU then you should choose 'y' here unless you
186 know that you do not want to use the MPU.
188 # If set, the workarounds for these ARM errata are applied early during U-Boot
189 # startup. Note that in general these options force the workarounds to be
190 # applied; no CPU-type/version detection exists, unlike the similar options in
191 # the Linux kernel. Do not set these options unless they apply! Also note that
192 # the following can be machine-specific errata. These do have ability to
193 # provide rudimentary version and machine-specific checks, but expect no
195 # CONFIG_ARM_ERRATA_430973
196 # CONFIG_ARM_ERRATA_454179
197 # CONFIG_ARM_ERRATA_621766
198 # CONFIG_ARM_ERRATA_798870
199 # CONFIG_ARM_ERRATA_801819
200 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
201 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
203 config ARM_ERRATA_430973
206 config ARM_ERRATA_454179
209 config ARM_ERRATA_621766
212 config ARM_ERRATA_716044
215 config ARM_ERRATA_725233
218 config ARM_ERRATA_742230
221 config ARM_ERRATA_743622
224 config ARM_ERRATA_751472
227 config ARM_ERRATA_761320
230 config ARM_ERRATA_773022
233 config ARM_ERRATA_774769
236 config ARM_ERRATA_794072
239 config ARM_ERRATA_798870
242 config ARM_ERRATA_801819
245 config ARM_ERRATA_826974
248 config ARM_ERRATA_828024
251 config ARM_ERRATA_829520
254 config ARM_ERRATA_833069
257 config ARM_ERRATA_833471
260 config ARM_ERRATA_845369
263 config ARM_ERRATA_852421
266 config ARM_ERRATA_852423
269 config ARM_ERRATA_855873
272 config ARM_CORTEX_A8_CVE_2017_5715
275 config ARM_CORTEX_A15_CVE_2017_5715
280 select SYS_CACHE_SHIFT_5
285 select SYS_CACHE_SHIFT_5
290 select SYS_CACHE_SHIFT_5
292 imply SPL_SEPARATE_BSS
296 select SYS_CACHE_SHIFT_5
301 select SYS_CACHE_SHIFT_5
303 imply SPL_SEPARATE_BSS
308 select SYS_CACHE_SHIFT_5
315 select SYS_CACHE_SHIFT_6
322 select SYS_CACHE_SHIFT_5
323 select SYS_THUMB_BUILD
329 select SYS_ARM_CACHE_CP15
331 select SYS_CACHE_SHIFT_6
334 default "arm720t" if CPU_ARM720T
335 default "arm920t" if CPU_ARM920T
336 default "arm926ejs" if CPU_ARM926EJS
337 default "arm946es" if CPU_ARM946ES
338 default "arm1136" if CPU_ARM1136
339 default "arm1176" if CPU_ARM1176
340 default "armv7" if CPU_V7A
341 default "armv7" if CPU_V7R
342 default "armv7m" if CPU_V7M
343 default "armv8" if ARM64
347 default 4 if CPU_ARM720T
348 default 4 if CPU_ARM920T
349 default 5 if CPU_ARM926EJS
350 default 5 if CPU_ARM946ES
351 default 6 if CPU_ARM1136
352 default 6 if CPU_ARM1176
359 prompt "Select the ARM data write cache policy"
360 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
361 default SYS_ARM_CACHE_WRITEBACK
363 config SYS_ARM_CACHE_WRITEBACK
364 bool "Write-back (WB)"
366 A write updates the cache only and marks the cache line as dirty.
367 External memory is updated only when the line is evicted or explicitly
370 config SYS_ARM_CACHE_WRITETHROUGH
371 bool "Write-through (WT)"
373 A write updates both the cache and the external memory system.
374 This does not mark the cache line as dirty.
376 config SYS_ARM_CACHE_WRITEALLOC
377 bool "Write allocation (WA)"
379 A cache line is allocated on a write miss. This means that executing a
380 store instruction on the processor might cause a burst read to occur.
381 There is a linefill to obtain the data for the cache line, before the
385 config ARCH_VERY_EARLY_INIT
388 config SPL_ARCH_VERY_EARLY_INIT
392 bool "Enable ARCH_CPU_INIT"
394 Some architectures require a call to arch_cpu_init().
395 Say Y here to enable it
397 config SYS_ARCH_TIMER
398 bool "ARM Generic Timer support"
399 depends on CPU_V7A || ARM64
402 The ARM Generic Timer (aka arch-timer) provides an architected
403 interface to a timer source on an SoC.
404 It is mandatory for ARMv8 implementation and widely available
408 bool "Support for ARM SMC Calling Convention (SMCCC)"
409 depends on CPU_V7A || ARM64
412 Say Y here if you want to enable ARM SMC Calling Convention.
413 This should be enabled if U-Boot needs to communicate with system
414 firmware (for example, PSCI) according to SMCCC.
416 config SYS_THUMB_BUILD
417 bool "Build U-Boot using the Thumb instruction set"
420 Use this flag to build U-Boot using the Thumb instruction set for
421 ARM architectures. Thumb instruction set provides better code
422 density. For ARM architectures that support Thumb2 this flag will
423 result in Thumb2 code generated by GCC.
425 config SPL_SYS_THUMB_BUILD
426 bool "Build SPL using the Thumb instruction set"
427 default y if SYS_THUMB_BUILD
428 depends on !ARM64 && SPL
430 Use this flag to build SPL using the Thumb instruction set for
431 ARM architectures. Thumb instruction set provides better code
432 density. For ARM architectures that support Thumb2 this flag will
433 result in Thumb2 code generated by GCC.
435 config TPL_SYS_THUMB_BUILD
436 bool "Build TPL using the Thumb instruction set"
437 default y if SYS_THUMB_BUILD
438 depends on TPL && !ARM64
440 Use this flag to build TPL using the Thumb instruction set for
441 ARM architectures. Thumb instruction set provides better code
442 density. For ARM architectures that support Thumb2 this flag will
443 result in Thumb2 code generated by GCC.
446 bool "ARM PL310 L2 cache controller"
448 Enable support for ARM PL310 L2 cache controller in U-Boot
450 config SPL_SYS_L2_PL310
451 bool "ARM PL310 L2 cache controller in SPL"
453 Enable support for ARM PL310 L2 cache controller in SPL
455 config SYS_L2CACHE_OFF
458 If SoC does not support L2CACHE or one does not want to enable
459 L2CACHE, choose this option.
461 config ENABLE_ARM_SOC_BOOT0_HOOK
462 bool "prepare BOOT0 header"
464 If the SoC's BOOT0 requires a header area filled with (magic)
465 values, then choose this option, and create a file included as
466 <asm/arch/boot0.h> which contains the required assembler code.
468 config USE_ARCH_MEMCPY
469 bool "Use an assembly optimized implementation of memcpy"
471 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
473 Enable the generation of an optimized version of memcpy.
474 Such an implementation may be faster under some conditions
475 but may increase the binary size.
477 config SPL_USE_ARCH_MEMCPY
478 bool "Use an assembly optimized implementation of memcpy for SPL"
479 default y if USE_ARCH_MEMCPY
482 Enable the generation of an optimized version of memcpy.
483 Such an implementation may be faster under some conditions
484 but may increase the binary size.
486 config TPL_USE_ARCH_MEMCPY
487 bool "Use an assembly optimized implementation of memcpy for TPL"
488 default y if USE_ARCH_MEMCPY
491 Enable the generation of an optimized version of memcpy.
492 Such an implementation may be faster under some conditions
493 but may increase the binary size.
495 config USE_ARCH_MEMMOVE
496 bool "Use an assembly optimized implementation of memmove" if !ARM64
497 default USE_ARCH_MEMCPY if ARM64
500 Enable the generation of an optimized version of memmove.
501 Such an implementation may be faster under some conditions
502 but may increase the binary size.
504 config SPL_USE_ARCH_MEMMOVE
505 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
506 default SPL_USE_ARCH_MEMCPY if ARM64
507 depends on SPL && ARM64
509 Enable the generation of an optimized version of memmove.
510 Such an implementation may be faster under some conditions
511 but may increase the binary size.
513 config TPL_USE_ARCH_MEMMOVE
514 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
515 default TPL_USE_ARCH_MEMCPY if ARM64
516 depends on TPL && ARM64
518 Enable the generation of an optimized version of memmove.
519 Such an implementation may be faster under some conditions
520 but may increase the binary size.
522 config USE_ARCH_MEMSET
523 bool "Use an assembly optimized implementation of memset"
525 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
527 Enable the generation of an optimized version of memset.
528 Such an implementation may be faster under some conditions
529 but may increase the binary size.
531 config SPL_USE_ARCH_MEMSET
532 bool "Use an assembly optimized implementation of memset for SPL"
533 default y if USE_ARCH_MEMSET
536 Enable the generation of an optimized version of memset.
537 Such an implementation may be faster under some conditions
538 but may increase the binary size.
540 config TPL_USE_ARCH_MEMSET
541 bool "Use an assembly optimized implementation of memset for TPL"
542 default y if USE_ARCH_MEMSET
545 Enable the generation of an optimized version of memset.
546 Such an implementation may be faster under some conditions
547 but may increase the binary size.
549 config ARM64_SUPPORT_AARCH32
550 bool "ARM64 system support AArch32 execution state"
552 default y if !TARGET_THUNDERX_88XX
554 This ARM64 system supports AArch32 execution state.
560 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
563 prompt "Target select"
568 select GPIO_EXTRA_HEADER
569 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
570 select SPL_SEPARATE_BSS if SPL
575 select GPIO_EXTRA_HEADER
576 select SPL_DM_SPI if SPL
579 Support for TI's DaVinci platform.
582 bool "Marvell Kirkwood"
583 select ARCH_MISC_INIT
584 select BOARD_EARLY_INIT_F
586 select GPIO_EXTRA_HEADER
590 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
595 select GPIO_EXTRA_HEADER
596 select SPL_DM_SPI if SPL
597 select SPL_DM_SPI_FLASH if SPL
598 select SPL_TIMER if SPL
599 select TIMER if !ARM64
608 select GPIO_EXTRA_HEADER
609 select SPL_SEPARATE_BSS if SPL
612 config TARGET_STV0991
613 bool "Support stv0991"
619 select GPIO_EXTRA_HEADER
626 bool "Broadcom BCM283X family"
630 select GPIO_EXTRA_HEADER
633 select SERIAL_SEARCH_ALL
638 bool "Broadcom BCM7XXX family"
641 select GPIO_EXTRA_HEADER
644 imply OF_HAS_PRIOR_STAGE
646 This enables support for Broadcom ARM-based set-top box
647 chipsets, including the 7445 family of chips.
650 bool "Broadcom broadband chip family"
655 config TARGET_VEXPRESS_CA9X4
656 bool "Support vexpress_ca9x4"
660 config TARGET_BCMCYGNUS
661 bool "Support bcmcygnus"
663 select GPIO_EXTRA_HEADER
666 imply BCM_SF2_ETH_GMAC
674 bool "Support Broadcom Northstar2"
676 select GPIO_EXTRA_HEADER
678 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
679 ARMv8 Cortex-A57 processors targeting a broad range of networking
683 bool "Support Broadcom NS3"
685 select BOARD_LATE_INIT
687 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
688 ARMv8 Cortex-A72 processors targeting a broad range of networking
692 bool "Samsung EXYNOS"
701 select GPIO_EXTRA_HEADER
702 imply SYS_THUMB_BUILD
707 bool "Samsung S5PC1XX"
713 select GPIO_EXTRA_HEADER
717 bool "Calxeda Highbank"
729 imply OF_HAS_PRIOR_STAGE
731 config ARCH_INTEGRATOR
732 bool "ARM Ltd. Integrator family"
735 select GPIO_EXTRA_HEADER
740 bool "Qualcomm IPQ40xx SoCs"
746 select GPIO_EXTRA_HEADER
760 select SYS_ARCH_TIMER
761 select SYS_THUMB_BUILD
767 bool "Texas Instruments' K3 Architecture"
772 config ARCH_OMAP2PLUS
775 select GPIO_EXTRA_HEADER
776 select SPL_BOARD_INIT if SPL
777 select SPL_STACK_R if SPL
779 imply TI_SYSC if DM && OF_CONTROL
781 imply SPL_SEPARATE_BSS
785 select GPIO_EXTRA_HEADER
786 imply DISTRO_DEFAULTS
789 Support for the Meson SoC family developed by Amlogic Inc.,
790 targeted at media players and tablet computers. We currently
791 support the S905 (GXBaby) 64-bit SoC.
796 select GPIO_EXTRA_HEADER
799 select SPL_LIBCOMMON_SUPPORT if SPL
800 select SPL_LIBGENERIC_SUPPORT if SPL
801 select SPL_OF_CONTROL if SPL
804 Support for the MediaTek SoCs family developed by MediaTek Inc.
805 Please refer to doc/README.mediatek for more information.
808 bool "NXP LPC32xx platform"
813 select GPIO_EXTRA_HEADER
819 bool "NXP i.MX8 platform"
821 select SYS_FSL_HAS_SEC
822 select SYS_FSL_SEC_COMPAT_4
823 select SYS_FSL_SEC_LE
826 select GPIO_EXTRA_HEADER
829 select ENABLE_ARM_SOC_BOOT0_HOOK
832 bool "NXP i.MX8M platform"
834 select GPIO_EXTRA_HEADER
836 select SYS_FSL_HAS_SEC
837 select SYS_FSL_SEC_COMPAT_4
838 select SYS_FSL_SEC_LE
841 select DM_EVENT if CLK
846 bool "NXP i.MX8ULP platform"
853 select GPIO_EXTRA_HEADER
859 bool "NXP i.MX9 platform"
865 select GPIO_EXTRA_HEADER
871 bool "NXP i.MXRT platform"
875 select GPIO_EXTRA_HEADER
881 bool "NXP i.MX23 family"
883 select GPIO_EXTRA_HEADER
889 bool "NXP i.MX28 family"
891 select GPIO_EXTRA_HEADER
897 bool "NXP i.MX31 family"
899 select GPIO_EXTRA_HEADER
904 select BOARD_POSTCLK_INIT
906 select GPIO_EXTRA_HEADER
908 select SYS_FSL_HAS_SEC
909 select SYS_FSL_SEC_COMPAT_4
910 select SYS_FSL_SEC_LE
911 select ROM_UNIFIED_SECTIONS
913 imply SYS_THUMB_BUILD
917 select ARCH_MISC_INIT
919 select GPIO_EXTRA_HEADER
922 select SYS_FSL_HAS_SEC
923 select SYS_FSL_SEC_COMPAT_4
924 select SYS_FSL_SEC_LE
925 imply BOARD_EARLY_INIT_F
927 imply SYS_THUMB_BUILD
931 select BOARD_POSTCLK_INIT
933 select GPIO_EXTRA_HEADER
936 select SYS_FSL_HAS_SEC
937 select SYS_FSL_SEC_COMPAT_4
938 select SYS_FSL_SEC_LE
939 select SYS_L2_PL310 if !SYS_L2CACHE_OFF
941 imply SYS_THUMB_BUILD
942 imply SPL_SEPARATE_BSS
946 select BOARD_EARLY_INIT_F
948 select GPIO_EXTRA_HEADER
953 bool "Nexell S5P4418/S5P6818 SoC"
954 select ENABLE_ARM_SOC_BOOT0_HOOK
956 select GPIO_EXTRA_HEADER
959 bool "Support Nuvoton SoCs"
980 select LINUX_KERNEL_IMAGE_HEADER
981 select OF_BOARD_SETUP
985 select POSITION_INDEPENDENT
991 select SYSRESET_WATCHDOG
992 select SYSRESET_WATCHDOG_AUTO
996 imply DISTRO_DEFAULTS
997 imply OF_HAS_PRIOR_STAGE
1000 bool "Actions Semi OWL SoCs"
1003 select GPIO_EXTRA_HEADER
1008 select SYS_RELOC_GD_ENV_ADDR
1012 bool "QEMU Virtual Platform"
1021 imply OF_HAS_PRIOR_STAGE
1024 bool "Renesas ARM SoCs"
1027 select GPIO_EXTRA_HEADER
1028 imply BOARD_EARLY_INIT_F
1031 imply SYS_THUMB_BUILD
1032 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1034 config ARCH_SNAPDRAGON
1035 bool "Qualcomm Snapdragon SoCs"
1040 select GPIO_EXTRA_HEADER
1049 bool "Altera SOCFPGA family"
1050 select ARCH_EARLY_INIT_R
1051 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1052 select ARM64 if TARGET_SOCFPGA_SOC64
1053 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1057 select GPIO_EXTRA_HEADER
1058 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1060 select SPL_DM_RESET if DM_RESET
1061 select SPL_DM_SERIAL
1062 select SPL_LIBCOMMON_SUPPORT
1063 select SPL_LIBGENERIC_SUPPORT
1064 select SPL_OF_CONTROL
1065 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1071 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1073 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1074 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1084 imply SPL_DM_SPI_FLASH
1085 imply SPL_LIBDISK_SUPPORT
1087 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1088 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1089 imply SPL_SPI_FLASH_SUPPORT
1094 bool "Support sunxi (Allwinner) SoCs"
1097 select CMD_MMC if MMC
1098 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1102 select DM_I2C if I2C
1103 select DM_SPI if SPI
1104 select DM_SPI_FLASH if SPI
1106 select DM_MMC if MMC
1107 select DM_SCSI if SCSI
1109 select GPIO_EXTRA_HEADER
1110 select OF_BOARD_SETUP
1114 select SPECIFY_CONSOLE_INDEX
1115 select SPL_SEPARATE_BSS if SPL
1116 select SPL_STACK_R if SPL
1117 select SPL_SYS_MALLOC_SIMPLE if SPL
1118 select SPL_SYS_THUMB_BUILD if !ARM64
1121 select SYS_THUMB_BUILD if !ARM64
1122 select USB if DISTRO_DEFAULTS
1123 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1124 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1125 select SPL_USE_TINY_PRINTF
1127 select SYS_RELOC_GD_ENV_ADDR
1128 imply BOARD_LATE_INIT
1131 imply CMD_UBI if MTD_RAW_NAND
1132 imply DISTRO_DEFAULTS
1135 imply OF_LIBFDT_OVERLAY
1136 imply PRE_CONSOLE_BUFFER
1138 imply SPL_LIBCOMMON_SUPPORT
1139 imply SPL_LIBGENERIC_SUPPORT
1140 imply SPL_MMC if MMC
1144 imply SYSRESET_WATCHDOG
1145 imply SYSRESET_WATCHDOG_AUTO
1150 bool "ST-Ericsson U8500 Series"
1154 select DM_MMC if MMC
1156 select DM_USB_GADGET if DM_USB
1160 imply AB8500_USB_PHY
1161 imply ARM_PL180_MMCI
1166 imply NOMADIK_MTU_TIMER
1171 imply SYS_THUMB_BUILD
1172 imply SYSRESET_SYSCON
1175 bool "Support Xilinx Versal Platform"
1179 select DM_MMC if MMC
1184 imply BOARD_LATE_INIT
1185 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1187 config ARCH_VERSAL_NET
1188 bool "Support Xilinx Versal NET Platform"
1192 select DM_MMC if MMC
1195 imply BOARD_LATE_INIT
1196 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1199 bool "Freescale Vybrid"
1201 select GPIO_EXTRA_HEADER
1202 select IOMUX_SHARE_CONF_REG
1204 select SYS_FSL_ERRATUM_ESDHC111
1209 bool "Xilinx Zynq based platform"
1210 select ARM_TWD_TIMER
1214 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1216 select DM_MMC if MMC
1222 select SPL_BOARD_INIT if SPL
1223 select SPL_CLK if SPL
1224 select SPL_DM if SPL
1225 select SPL_DM_SPI if SPL
1226 select SPL_DM_SPI_FLASH if SPL
1227 select SPL_OF_CONTROL if SPL
1228 select SPL_SEPARATE_BSS if SPL
1229 select SPL_TIMER if SPL
1232 imply ARCH_EARLY_INIT_R
1233 imply BOARD_LATE_INIT
1237 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1240 config ARCH_ZYNQMP_R5
1241 bool "Xilinx ZynqMP R5 based platform"
1245 select DM_MMC if MMC
1252 bool "Xilinx ZynqMP based platform"
1256 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1258 select DM_MMC if MMC
1260 select DM_SPI if SPI
1261 select DM_SPI_FLASH if DM_SPI
1265 select SPL_BOARD_INIT if SPL
1266 select SPL_CLK if SPL
1267 select SPL_DM if SPL
1268 select SPL_DM_SPI if SPI && SPL_DM
1269 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1270 select SPL_DM_MAILBOX if SPL
1271 imply SPL_FIRMWARE if SPL
1272 select SPL_SEPARATE_BSS if SPL
1274 imply ZYNQMP_IPI if DM_MAILBOX
1276 imply BOARD_LATE_INIT
1278 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1282 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1286 select GPIO_EXTRA_HEADER
1287 imply DISTRO_DEFAULTS
1289 imply SPL_TIMER if SPL
1291 config ARCH_VEXPRESS64
1292 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1300 select MTD_NOR_FLASH if MTD
1301 select FLASH_CFI_DRIVER if MTD
1302 select ENV_IS_IN_FLASH if MTD
1303 imply DISTRO_DEFAULTS
1305 config TARGET_CORSTONE1000
1306 bool "Support Corstone1000 Platform"
1311 config TARGET_TOTAL_COMPUTE
1312 bool "Support Total Compute Platform"
1320 config TARGET_LS2080A_EMU
1321 bool "Support ls2080a_emu"
1324 select ARMV8_MULTIENTRY
1325 select FSL_DDR_SYNC_REFRESH
1326 select GPIO_EXTRA_HEADER
1328 Support for Freescale LS2080A_EMU platform.
1329 The LS2080A Development System (EMULATOR) is a pre-silicon
1330 development platform that supports the QorIQ LS2080A
1331 Layerscape Architecture processor.
1333 config TARGET_LS1088AQDS
1334 bool "Support ls1088aqds"
1337 select ARMV8_MULTIENTRY
1338 select ARCH_SUPPORT_TFABOOT
1339 select BOARD_LATE_INIT
1340 select GPIO_EXTRA_HEADER
1342 select FSL_DDR_INTERACTIVE if !SD_BOOT
1344 Support for NXP LS1088AQDS platform.
1345 The LS1088A Development System (QDS) is a high-performance
1346 development platform that supports the QorIQ LS1088A
1347 Layerscape Architecture processor.
1349 config TARGET_LS2080AQDS
1350 bool "Support ls2080aqds"
1353 select ARMV8_MULTIENTRY
1354 select ARCH_SUPPORT_TFABOOT
1355 select BOARD_LATE_INIT
1356 select GPIO_EXTRA_HEADER
1361 select FSL_DDR_INTERACTIVE if !SPL
1363 Support for Freescale LS2080AQDS platform.
1364 The LS2080A Development System (QDS) is a high-performance
1365 development platform that supports the QorIQ LS2080A
1366 Layerscape Architecture processor.
1368 config TARGET_LS2080ARDB
1369 bool "Support ls2080ardb"
1372 select ARMV8_MULTIENTRY
1373 select ARCH_SUPPORT_TFABOOT
1374 select BOARD_LATE_INIT
1377 select FSL_DDR_INTERACTIVE if !SPL
1378 select GPIO_EXTRA_HEADER
1382 Support for Freescale LS2080ARDB platform.
1383 The LS2080A Reference design board (RDB) is a high-performance
1384 development platform that supports the QorIQ LS2080A
1385 Layerscape Architecture processor.
1387 config TARGET_LS2081ARDB
1388 bool "Support ls2081ardb"
1391 select ARMV8_MULTIENTRY
1392 select BOARD_LATE_INIT
1393 select GPIO_EXTRA_HEADER
1396 Support for Freescale LS2081ARDB platform.
1397 The LS2081A Reference design board (RDB) is a high-performance
1398 development platform that supports the QorIQ LS2081A/LS2041A
1399 Layerscape Architecture processor.
1401 config TARGET_LX2160ARDB
1402 bool "Support lx2160ardb"
1405 select ARMV8_MULTIENTRY
1406 select ARCH_SUPPORT_TFABOOT
1407 select BOARD_LATE_INIT
1408 select GPIO_EXTRA_HEADER
1410 Support for NXP LX2160ARDB platform.
1411 The lx2160ardb (LX2160A Reference design board (RDB)
1412 is a high-performance development platform that supports the
1413 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1415 config TARGET_LX2160AQDS
1416 bool "Support lx2160aqds"
1419 select ARMV8_MULTIENTRY
1420 select ARCH_SUPPORT_TFABOOT
1421 select BOARD_LATE_INIT
1422 select GPIO_EXTRA_HEADER
1424 Support for NXP LX2160AQDS platform.
1425 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1426 is a high-performance development platform that supports the
1427 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1429 config TARGET_LX2162AQDS
1430 bool "Support lx2162aqds"
1432 select ARCH_MISC_INIT
1434 select ARMV8_MULTIENTRY
1435 select ARCH_SUPPORT_TFABOOT
1436 select BOARD_LATE_INIT
1437 select GPIO_EXTRA_HEADER
1439 Support for NXP LX2162AQDS platform.
1440 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1443 bool "Support HiKey 96boards Consumer Edition Platform"
1448 select GPIO_EXTRA_HEADER
1451 select SPECIFY_CONSOLE_INDEX
1454 Support for HiKey 96boards platform. It features a HI6220
1455 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1457 config TARGET_HIKEY960
1458 bool "Support HiKey960 96boards Consumer Edition Platform"
1462 select GPIO_EXTRA_HEADER
1467 Support for HiKey960 96boards platform. It features a HI3660
1468 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1470 config TARGET_POPLAR
1471 bool "Support Poplar 96boards Enterprise Edition Platform"
1475 select GPIO_EXTRA_HEADER
1480 Support for Poplar 96boards EE platform. It features a HI3798cv200
1481 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1482 making it capable of running any commercial set-top solution based on
1485 config TARGET_LS1012AQDS
1486 bool "Support ls1012aqds"
1489 select ARCH_SUPPORT_TFABOOT
1490 select BOARD_LATE_INIT
1491 select GPIO_EXTRA_HEADER
1493 Support for Freescale LS1012AQDS platform.
1494 The LS1012A Development System (QDS) is a high-performance
1495 development platform that supports the QorIQ LS1012A
1496 Layerscape Architecture processor.
1498 config TARGET_LS1012ARDB
1499 bool "Support ls1012ardb"
1502 select ARCH_SUPPORT_TFABOOT
1503 select BOARD_LATE_INIT
1504 select GPIO_EXTRA_HEADER
1508 Support for Freescale LS1012ARDB platform.
1509 The LS1012A Reference design board (RDB) is a high-performance
1510 development platform that supports the QorIQ LS1012A
1511 Layerscape Architecture processor.
1513 config TARGET_LS1012A2G5RDB
1514 bool "Support ls1012a2g5rdb"
1517 select ARCH_SUPPORT_TFABOOT
1518 select BOARD_LATE_INIT
1519 select GPIO_EXTRA_HEADER
1522 Support for Freescale LS1012A2G5RDB platform.
1523 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1524 development platform that supports the QorIQ LS1012A
1525 Layerscape Architecture processor.
1527 config TARGET_LS1012AFRWY
1528 bool "Support ls1012afrwy"
1531 select ARCH_SUPPORT_TFABOOT
1532 select BOARD_LATE_INIT
1533 select GPIO_EXTRA_HEADER
1537 Support for Freescale LS1012AFRWY platform.
1538 The LS1012A FRWY board (FRWY) is a high-performance
1539 development platform that supports the QorIQ LS1012A
1540 Layerscape Architecture processor.
1542 config TARGET_LS1012AFRDM
1543 bool "Support ls1012afrdm"
1546 select ARCH_SUPPORT_TFABOOT
1547 select GPIO_EXTRA_HEADER
1549 Support for Freescale LS1012AFRDM platform.
1550 The LS1012A Freedom board (FRDM) is a high-performance
1551 development platform that supports the QorIQ LS1012A
1552 Layerscape Architecture processor.
1554 config TARGET_LS1028AQDS
1555 bool "Support ls1028aqds"
1558 select ARMV8_MULTIENTRY
1559 select ARCH_SUPPORT_TFABOOT
1560 select BOARD_LATE_INIT
1561 select GPIO_EXTRA_HEADER
1563 Support for Freescale LS1028AQDS platform
1564 The LS1028A Development System (QDS) is a high-performance
1565 development platform that supports the QorIQ LS1028A
1566 Layerscape Architecture processor.
1568 config TARGET_LS1028ARDB
1569 bool "Support ls1028ardb"
1572 select ARMV8_MULTIENTRY
1573 select ARCH_SUPPORT_TFABOOT
1574 select BOARD_LATE_INIT
1575 select GPIO_EXTRA_HEADER
1577 Support for Freescale LS1028ARDB platform
1578 The LS1028A Development System (RDB) is a high-performance
1579 development platform that supports the QorIQ LS1028A
1580 Layerscape Architecture processor.
1582 config TARGET_LS1088ARDB
1583 bool "Support ls1088ardb"
1586 select ARMV8_MULTIENTRY
1587 select ARCH_SUPPORT_TFABOOT
1588 select BOARD_LATE_INIT
1590 select FSL_DDR_INTERACTIVE if !SD_BOOT
1591 select GPIO_EXTRA_HEADER
1593 Support for NXP LS1088ARDB platform.
1594 The LS1088A Reference design board (RDB) is a high-performance
1595 development platform that supports the QorIQ LS1088A
1596 Layerscape Architecture processor.
1598 config TARGET_LS1021AQDS
1599 bool "Support ls1021aqds"
1601 select ARCH_SUPPORT_PSCI
1602 select BOARD_EARLY_INIT_F
1603 select BOARD_LATE_INIT
1605 select CPU_V7_HAS_NONSEC
1606 select CPU_V7_HAS_VIRT
1607 select LS1_DEEP_SLEEP
1608 select PEN_ADDR_BIG_ENDIAN
1611 select FSL_DDR_INTERACTIVE
1612 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1613 select GPIO_EXTRA_HEADER
1614 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1617 config TARGET_LS1021ATWR
1618 bool "Support ls1021atwr"
1620 select ARCH_SUPPORT_PSCI
1621 select BOARD_EARLY_INIT_F
1622 select BOARD_LATE_INIT
1624 select CPU_V7_HAS_NONSEC
1625 select CPU_V7_HAS_VIRT
1626 select LS1_DEEP_SLEEP
1627 select PEN_ADDR_BIG_ENDIAN
1629 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1630 select GPIO_EXTRA_HEADER
1633 config TARGET_PG_WCOM_SELI8
1634 bool "Support Hitachi-Powergrids SELI8 service unit card"
1636 select ARCH_SUPPORT_PSCI
1637 select BOARD_EARLY_INIT_F
1638 select BOARD_LATE_INIT
1640 select CPU_V7_HAS_NONSEC
1641 select CPU_V7_HAS_VIRT
1643 select FSL_DDR_INTERACTIVE
1644 select GPIO_EXTRA_HEADER
1648 Support for Hitachi-Powergrids SELI8 service unit card.
1649 SELI8 is a QorIQ LS1021a based service unit card used
1650 in XMC20 and FOX615 product families.
1652 config TARGET_PG_WCOM_EXPU1
1653 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1655 select ARCH_SUPPORT_PSCI
1656 select BOARD_EARLY_INIT_F
1657 select BOARD_LATE_INIT
1659 select CPU_V7_HAS_NONSEC
1660 select CPU_V7_HAS_VIRT
1662 select FSL_DDR_INTERACTIVE
1666 Support for Hitachi-Powergrids EXPU1 service unit card.
1667 EXPU1 is a QorIQ LS1021a based service unit card used
1668 in XMC20 and FOX615 product families.
1670 config TARGET_LS1021ATSN
1671 bool "Support ls1021atsn"
1673 select ARCH_SUPPORT_PSCI
1674 select BOARD_EARLY_INIT_F
1675 select BOARD_LATE_INIT
1677 select CPU_V7_HAS_NONSEC
1678 select CPU_V7_HAS_VIRT
1679 select LS1_DEEP_SLEEP
1681 select GPIO_EXTRA_HEADER
1684 config TARGET_LS1021AIOT
1685 bool "Support ls1021aiot"
1687 select ARCH_SUPPORT_PSCI
1688 select BOARD_LATE_INIT
1690 select CPU_V7_HAS_NONSEC
1691 select CPU_V7_HAS_VIRT
1692 select PEN_ADDR_BIG_ENDIAN
1694 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1695 select GPIO_EXTRA_HEADER
1698 Support for Freescale LS1021AIOT platform.
1699 The LS1021A Freescale board (IOT) is a high-performance
1700 development platform that supports the QorIQ LS1021A
1701 Layerscape Architecture processor.
1703 config TARGET_LS1043AQDS
1704 bool "Support ls1043aqds"
1707 select ARMV8_MULTIENTRY
1708 select ARCH_SUPPORT_TFABOOT
1709 select BOARD_EARLY_INIT_F
1710 select BOARD_LATE_INIT
1712 select FSL_DDR_INTERACTIVE if !SPL
1713 select FSL_DSPI if !SPL_NO_DSPI
1714 select DM_SPI_FLASH if FSL_DSPI
1715 select GPIO_EXTRA_HEADER
1719 Support for Freescale LS1043AQDS platform.
1721 config TARGET_LS1043ARDB
1722 bool "Support ls1043ardb"
1725 select ARMV8_MULTIENTRY
1726 select ARCH_SUPPORT_TFABOOT
1727 select BOARD_EARLY_INIT_F
1728 select BOARD_LATE_INIT
1730 select FSL_DSPI if !SPL_NO_DSPI
1731 select DM_SPI_FLASH if FSL_DSPI
1732 select GPIO_EXTRA_HEADER
1734 Support for Freescale LS1043ARDB platform.
1736 config TARGET_LS1046AQDS
1737 bool "Support ls1046aqds"
1740 select ARMV8_MULTIENTRY
1741 select ARCH_SUPPORT_TFABOOT
1742 select BOARD_EARLY_INIT_F
1743 select BOARD_LATE_INIT
1744 select DM_SPI_FLASH if DM_SPI
1746 select FSL_DDR_BIST if !SPL
1747 select FSL_DDR_INTERACTIVE if !SPL
1748 select FSL_DDR_INTERACTIVE if !SPL
1749 select GPIO_EXTRA_HEADER
1752 Support for Freescale LS1046AQDS platform.
1753 The LS1046A Development System (QDS) is a high-performance
1754 development platform that supports the QorIQ LS1046A
1755 Layerscape Architecture processor.
1757 config TARGET_LS1046ARDB
1758 bool "Support ls1046ardb"
1761 select ARMV8_MULTIENTRY
1762 select ARCH_SUPPORT_TFABOOT
1763 select BOARD_EARLY_INIT_F
1764 select BOARD_LATE_INIT
1765 select DM_SPI_FLASH if DM_SPI
1766 select POWER_MC34VR500
1769 select FSL_DDR_INTERACTIVE if !SPL
1770 select GPIO_EXTRA_HEADER
1773 Support for Freescale LS1046ARDB platform.
1774 The LS1046A Reference Design Board (RDB) is a high-performance
1775 development platform that supports the QorIQ LS1046A
1776 Layerscape Architecture processor.
1778 config TARGET_LS1046AFRWY
1779 bool "Support ls1046afrwy"
1782 select ARMV8_MULTIENTRY
1783 select ARCH_SUPPORT_TFABOOT
1784 select BOARD_EARLY_INIT_F
1785 select BOARD_LATE_INIT
1786 select DM_SPI_FLASH if DM_SPI
1787 select GPIO_EXTRA_HEADER
1790 Support for Freescale LS1046AFRWY platform.
1791 The LS1046A Freeway Board (FRWY) is a high-performance
1792 development platform that supports the QorIQ LS1046A
1793 Layerscape Architecture processor.
1799 select ARMV8_MULTIENTRY
1814 select GPIO_EXTRA_HEADER
1815 select SPL_DM if SPL
1816 select SPL_DM_SPI if SPL
1817 select SPL_DM_SPI_FLASH if SPL
1818 select SPL_DM_I2C if SPL
1819 select SPL_DM_MMC if SPL
1820 select SPL_DM_SERIAL if SPL
1822 Support for Kontron SMARC-sAL28 board.
1825 bool "Support ten64"
1827 select ARCH_MISC_INIT
1829 select ARMV8_MULTIENTRY
1830 select ARCH_SUPPORT_TFABOOT
1831 select BOARD_LATE_INIT
1833 select FSL_DDR_INTERACTIVE if !SD_BOOT
1834 select GPIO_EXTRA_HEADER
1836 Support for Traverse Technologies Ten64 board, based
1839 config ARCH_UNIPHIER
1840 bool "Socionext UniPhier SoCs"
1841 select BOARD_LATE_INIT
1849 select OF_BOARD_SETUP
1853 select SPL_BOARD_INIT if SPL
1854 select SPL_DM if SPL
1855 select SPL_LIBCOMMON_SUPPORT if SPL
1856 select SPL_LIBGENERIC_SUPPORT if SPL
1857 select SPL_OF_CONTROL if SPL
1858 select SPL_PINCTRL if SPL
1861 imply DISTRO_DEFAULTS
1864 Support for UniPhier SoC family developed by Socionext Inc.
1865 (formerly, System LSI Business Division of Panasonic Corporation)
1867 config ARCH_SYNQUACER
1868 bool "Socionext SynQuacer SoCs"
1874 select SYSRESET_PSCI
1877 Support for SynQuacer SoC family developed by Socionext Inc.
1878 This SoC is used on 96boards EE DeveloperBox.
1881 bool "Support STMicroelectronics STM32 MCU with cortex M"
1888 bool "Support STMicroelectronics SoCs"
1897 Support for STMicroelectronics STiH407/10 SoC family.
1898 This SoC is used on Linaro 96Board STiH410-B2260
1901 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1902 select ARCH_MISC_INIT
1903 select ARCH_SUPPORT_TFABOOT
1904 select BOARD_LATE_INIT
1913 select OF_SYSTEM_SETUP
1918 select SYS_THUMB_BUILD
1922 imply OF_LIBFDT_OVERLAY
1923 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1927 Support for STM32MP SoC family developed by STMicroelectronics,
1928 MPUs based on ARM cortex A core
1929 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1930 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1932 SPL is the unsecure FSBL for the basic boot chain.
1934 config ARCH_ROCKCHIP
1935 bool "Support Rockchip SoCs"
1937 select BINMAN if SPL_OPTEE || SPL
1947 select ENABLE_ARM_SOC_BOOT0_HOOK
1950 select SPL_DM if SPL
1951 select SPL_DM_SPI if SPL
1952 select SPL_DM_SPI_FLASH if SPL
1954 select SYS_THUMB_BUILD if !ARM64
1957 imply DEBUG_UART_BOARD_INIT
1958 imply DISTRO_DEFAULTS if !ROCKCHIP_RK3399
1960 imply SARADC_ROCKCHIP
1962 imply SPL_SYS_MALLOC_SIMPLE
1965 imply USB_FUNCTION_FASTBOOT
1967 config ARCH_OCTEONTX
1968 bool "Support OcteonTX SoCs"
1971 select GPIO_EXTRA_HEADER
1975 select BOARD_LATE_INIT
1976 select SYS_CACHE_SHIFT_7
1977 select SYS_PCI_64BIT if PCI
1978 imply OF_HAS_PRIOR_STAGE
1980 config ARCH_OCTEONTX2
1981 bool "Support OcteonTX2 SoCs"
1984 select GPIO_EXTRA_HEADER
1988 select BOARD_LATE_INIT
1989 select SYS_CACHE_SHIFT_7
1990 select SYS_PCI_64BIT if PCI
1991 imply OF_HAS_PRIOR_STAGE
1993 config TARGET_THUNDERX_88XX
1994 bool "Support ThunderX 88xx"
1996 select GPIO_EXTRA_HEADER
1999 select SYS_CACHE_SHIFT_7
2002 bool "Support Aspeed SoCs"
2007 config TARGET_DURIAN
2008 bool "Support Phytium Durian Platform"
2010 select GPIO_EXTRA_HEADER
2012 Support for durian platform.
2013 It has 2GB Sdram, uart and pcie.
2015 config TARGET_POMELO
2016 bool "Support Phytium Pomelo Platform"
2030 Support for pomelo platform.
2031 It has 8GB Sdram, uart and pcie.
2033 config TARGET_PRESIDIO_ASIC
2034 bool "Support Cortina Presidio ASIC Platform"
2038 config TARGET_XENGUEST_ARM64
2039 bool "Xen guest ARM64"
2043 select LINUX_KERNEL_IMAGE_HEADER
2046 imply OF_HAS_PRIOR_STAGE
2049 bool "Support HPE GXP SoCs"
2056 config SUPPORT_PASSING_ATAGS
2057 bool "Support pre-devicetree ATAG-based booting"
2059 imply SETUP_MEMORY_TAGS
2061 Support for booting older Linux kernels, using ATAGs rather than
2062 passing a devicetree. This is option is rarely used, and the
2063 semantics are defined at
2064 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2066 config SETUP_MEMORY_TAGS
2067 bool "Pass memory size information via ATAG"
2068 depends on SUPPORT_PASSING_ATAGS
2071 bool "Pass Linux kernel cmdline via ATAG"
2072 depends on SUPPORT_PASSING_ATAGS
2075 bool "Pass initrd starting point and size via ATAG"
2076 depends on SUPPORT_PASSING_ATAGS
2079 bool "Pass system revision via ATAG"
2080 depends on SUPPORT_PASSING_ATAGS
2083 bool "Pass system serial number via ATAG"
2084 depends on SUPPORT_PASSING_ATAGS
2086 config STATIC_MACH_TYPE
2087 bool "Statically define the Machine ID number"
2088 default y if TARGET_DS109 || TARGET_NOKIA_RX51 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2090 When booting via ATAGs, enable this option if we know the correct
2091 machine ID number to use at compile time. Some systems will be
2092 passed the number dynamically by whatever loads U-Boot.
2095 int "Machine ID number"
2096 depends on STATIC_MACH_TYPE
2097 default 527 if TARGET_DS109
2098 default 1955 if TARGET_NOKIA_RX51
2099 default 3036 if TARGET_DS414
2100 default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2102 When booting via ATAGs, the machine type must be passed as a number.
2103 For the full list see https://www.arm.linux.org.uk/developer/machines
2105 config ARCH_SUPPORT_TFABOOT
2109 bool "Support for booting from TF-A"
2110 depends on ARCH_SUPPORT_TFABOOT
2112 Some platforms support the setup of secure registers (for instance
2113 for CPU errata handling) or provide secure services like PSCI.
2114 Those services could also be provided by other firmware parts
2115 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2116 does not need to (and cannot) execute this code.
2117 Enabling this option will make a U-Boot binary that is relying
2118 on other firmware layers to provide secure functionality.
2120 config TI_SECURE_DEVICE
2121 bool "HS Device Type Support"
2122 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2124 If a high secure (HS) device type is being used, this config
2125 must be set. This option impacts various aspects of the
2126 build system (to create signed boot images that can be
2127 authenticated) and the code. See the doc/README.ti-secure
2128 file for further details.
2130 config SYS_KWD_CONFIG
2131 string "kwbimage config file path"
2132 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2133 default "arch/arm/mach-mvebu/kwbimage.cfg"
2135 Path within the source directory to the kwbimage.cfg file to use
2136 when packaging the U-Boot image for use.
2138 source "arch/arm/mach-apple/Kconfig"
2140 source "arch/arm/mach-aspeed/Kconfig"
2142 source "arch/arm/mach-at91/Kconfig"
2144 source "arch/arm/mach-bcm283x/Kconfig"
2146 source "arch/arm/mach-bcmbca/Kconfig"
2148 source "arch/arm/mach-bcmstb/Kconfig"
2150 source "arch/arm/mach-davinci/Kconfig"
2152 source "arch/arm/mach-exynos/Kconfig"
2154 source "arch/arm/mach-hpe/gxp/Kconfig"
2156 source "arch/arm/mach-highbank/Kconfig"
2158 source "arch/arm/mach-integrator/Kconfig"
2160 source "arch/arm/mach-ipq40xx/Kconfig"
2162 source "arch/arm/mach-k3/Kconfig"
2164 source "arch/arm/mach-keystone/Kconfig"
2166 source "arch/arm/mach-kirkwood/Kconfig"
2168 source "arch/arm/mach-lpc32xx/Kconfig"
2170 source "arch/arm/mach-mvebu/Kconfig"
2172 source "arch/arm/mach-octeontx/Kconfig"
2174 source "arch/arm/mach-octeontx2/Kconfig"
2176 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2178 source "arch/arm/mach-imx/mx3/Kconfig"
2180 source "arch/arm/mach-imx/mx5/Kconfig"
2182 source "arch/arm/mach-imx/mx6/Kconfig"
2184 source "arch/arm/mach-imx/mx7/Kconfig"
2186 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2188 source "arch/arm/mach-imx/imx8/Kconfig"
2190 source "arch/arm/mach-imx/imx8m/Kconfig"
2192 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2194 source "arch/arm/mach-imx/imx9/Kconfig"
2196 source "arch/arm/mach-imx/imxrt/Kconfig"
2198 source "arch/arm/mach-imx/mxs/Kconfig"
2200 source "arch/arm/mach-omap2/Kconfig"
2202 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2204 source "arch/arm/mach-orion5x/Kconfig"
2206 source "arch/arm/mach-owl/Kconfig"
2208 source "arch/arm/mach-rmobile/Kconfig"
2210 source "arch/arm/mach-meson/Kconfig"
2212 source "arch/arm/mach-mediatek/Kconfig"
2214 source "arch/arm/mach-qemu/Kconfig"
2216 source "arch/arm/mach-rockchip/Kconfig"
2218 source "arch/arm/mach-s5pc1xx/Kconfig"
2220 source "arch/arm/mach-snapdragon/Kconfig"
2222 source "arch/arm/mach-socfpga/Kconfig"
2224 source "arch/arm/mach-sti/Kconfig"
2226 source "arch/arm/mach-stm32/Kconfig"
2228 source "arch/arm/mach-stm32mp/Kconfig"
2230 source "arch/arm/mach-sunxi/Kconfig"
2232 source "arch/arm/mach-tegra/Kconfig"
2234 source "arch/arm/mach-u8500/Kconfig"
2236 source "arch/arm/mach-uniphier/Kconfig"
2238 source "arch/arm/cpu/armv7/vf610/Kconfig"
2240 source "arch/arm/mach-zynq/Kconfig"
2242 source "arch/arm/mach-zynqmp/Kconfig"
2244 source "arch/arm/mach-versal/Kconfig"
2246 source "arch/arm/mach-versal-net/Kconfig"
2248 source "arch/arm/mach-zynqmp-r5/Kconfig"
2250 source "arch/arm/cpu/armv7/Kconfig"
2252 source "arch/arm/cpu/armv8/Kconfig"
2254 source "arch/arm/mach-imx/Kconfig"
2256 source "arch/arm/mach-nexell/Kconfig"
2258 source "arch/arm/mach-npcm/Kconfig"
2260 source "board/armltd/total_compute/Kconfig"
2261 source "board/armltd/corstone1000/Kconfig"
2262 source "board/bosch/shc/Kconfig"
2263 source "board/bosch/guardian/Kconfig"
2264 source "board/Marvell/octeontx/Kconfig"
2265 source "board/Marvell/octeontx2/Kconfig"
2266 source "board/armltd/vexpress/Kconfig"
2267 source "board/armltd/vexpress64/Kconfig"
2268 source "board/cortina/presidio-asic/Kconfig"
2269 source "board/broadcom/bcmns3/Kconfig"
2270 source "board/cavium/thunderx/Kconfig"
2271 source "board/eets/pdu001/Kconfig"
2272 source "board/emulation/qemu-arm/Kconfig"
2273 source "board/freescale/ls2080aqds/Kconfig"
2274 source "board/freescale/ls2080ardb/Kconfig"
2275 source "board/freescale/ls1088a/Kconfig"
2276 source "board/freescale/ls1028a/Kconfig"
2277 source "board/freescale/ls1021aqds/Kconfig"
2278 source "board/freescale/ls1043aqds/Kconfig"
2279 source "board/freescale/ls1021atwr/Kconfig"
2280 source "board/freescale/ls1021atsn/Kconfig"
2281 source "board/freescale/ls1021aiot/Kconfig"
2282 source "board/freescale/ls1046aqds/Kconfig"
2283 source "board/freescale/ls1043ardb/Kconfig"
2284 source "board/freescale/ls1046ardb/Kconfig"
2285 source "board/freescale/ls1046afrwy/Kconfig"
2286 source "board/freescale/ls1012aqds/Kconfig"
2287 source "board/freescale/ls1012ardb/Kconfig"
2288 source "board/freescale/ls1012afrdm/Kconfig"
2289 source "board/freescale/lx2160a/Kconfig"
2290 source "board/grinn/chiliboard/Kconfig"
2291 source "board/hisilicon/hikey/Kconfig"
2292 source "board/hisilicon/hikey960/Kconfig"
2293 source "board/hisilicon/poplar/Kconfig"
2294 source "board/isee/igep003x/Kconfig"
2295 source "board/kontron/sl28/Kconfig"
2296 source "board/myir/mys_6ulx/Kconfig"
2297 source "board/samsung/common/Kconfig"
2298 source "board/siemens/common/Kconfig"
2299 source "board/seeed/npi_imx6ull/Kconfig"
2300 source "board/socionext/developerbox/Kconfig"
2301 source "board/st/stv0991/Kconfig"
2302 source "board/tcl/sl50/Kconfig"
2303 source "board/traverse/ten64/Kconfig"
2304 source "board/variscite/dart_6ul/Kconfig"
2305 source "board/vscom/baltos/Kconfig"
2306 source "board/phytium/durian/Kconfig"
2307 source "board/phytium/pomelo/Kconfig"
2308 source "board/xen/xenguest_arm64/Kconfig"
2310 source "arch/arm/Kconfig.debug"