1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
11 imply SPL_SEPARATE_BSS
14 bool "Enable support for CRC32 instruction"
18 ARMv8 implements dedicated crc32 instruction for crc32 calculation.
19 This is faster than software crc32 calculation. This instruction may
20 not be present on all ARMv8.0, but is always present on ARMv8.1 and
23 config COUNTER_FREQUENCY
24 int "Timer clock frequency"
25 depends on ARM64 || CPU_V7A
26 default 8000000 if IMX8 || MX7 || MX6UL || MX6ULL
27 default 24000000 if ARCH_SUNXI || ARCH_EXYNOS || ROCKCHIP_RK3128 || \
28 ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
29 default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
30 default 100000000 if ARCH_ZYNQMP
33 For platforms with ARMv8-A and ARMv7-A which features a system
34 counter, those platforms needs software to program the counter
35 frequency. Setup time clock frequency for certain platform.
36 0 means no need to configure the system counter frequency.
37 For platforms needs the frequency set in U-Boot with a
38 pre-defined value, should have the macro defined as a non-zero value.
40 config POSITION_INDEPENDENT
41 bool "Generate position-independent pre-relocation code"
42 depends on ARM64 || CPU_V7A
44 U-Boot expects to be linked to a specific hard-coded address, and to
45 be loaded to and run from that address. This option lifts that
46 restriction, thus allowing the code to be loaded to and executed from
47 almost any 4K aligned address. This logic relies on the relocation
48 information that is embedded in the binary to support U-Boot
49 relocating itself to the top-of-RAM later during execution.
51 config INIT_SP_RELATIVE
52 bool "Specify the early stack pointer relative to the .bss section"
54 default n if ARCH_QEMU
55 default y if POSITION_INDEPENDENT
57 U-Boot typically uses a hard-coded value for the stack pointer
58 before relocation. Enable this option to instead calculate the
59 initial SP at run-time. This is useful to avoid hard-coding addresses
60 into U-Boot, so that it can be loaded and executed at arbitrary
61 addresses and thus avoid using arbitrary addresses at runtime.
63 If this option is enabled, the early stack pointer is set to
64 &_bss_start with a offset value added. The offset is specified by
65 SYS_INIT_SP_BSS_OFFSET.
67 config SYS_INIT_SP_BSS_OFFSET
68 int "Early stack offset from the .bss base address"
70 depends on INIT_SP_RELATIVE
73 This option's value is the offset added to &_bss_start in order to
74 calculate the stack pointer. This offset should be large enough so
75 that the early malloc region, global data (gd), and early stack usage
76 do not overlap any appended DTB.
78 config SPL_SYS_NO_VECTOR_TABLE
82 config LINUX_KERNEL_IMAGE_HEADER
86 Place a Linux kernel image header at the start of the U-Boot binary.
87 The format of the header is described in the Linux kernel source at
88 Documentation/arm64/booting.txt. This feature is useful since the
89 image header reports the amount of memory (BSS and similar) that
90 U-Boot needs to use, but which isn't part of the binary.
92 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
93 depends on LINUX_KERNEL_IMAGE_HEADER
96 The value subtracted from CONFIG_TEXT_BASE to calculate the
97 TEXT_OFFSET value written to the Linux kernel image header.
109 ARM GICV3 Interrupt translation service (ITS).
110 Basic support for programming locality specific peripheral
111 interrupts (LPI) configuration tables and enable LPI tables.
112 LPI configuration table can be used by u-boot or Linux.
113 ARM GICV3 has limitation, once the LPI table is enabled, LPI
114 configuration table can not be re-programmed, unless GICV3 reset.
120 config DMA_ADDR_T_64BIT
130 config GPIO_EXTRA_HEADER
133 # Used for compatibility with asm files copied from the kernel
134 config ARM_ASM_UNIFIED
138 # Used for compatibility with asm files copied from the kernel
142 config SYS_ICACHE_OFF
143 bool "Do not enable icache"
145 Do not enable instruction cache in U-Boot.
147 config SPL_SYS_ICACHE_OFF
148 bool "Do not enable icache in SPL"
150 default SYS_ICACHE_OFF
152 Do not enable instruction cache in SPL.
154 config SYS_DCACHE_OFF
155 bool "Do not enable dcache"
157 Do not enable data cache in U-Boot.
159 config SPL_SYS_DCACHE_OFF
160 bool "Do not enable dcache in SPL"
162 default SYS_DCACHE_OFF
164 Do not enable data cache in SPL.
166 config SYS_ARM_CACHE_CP15
167 bool "CP15 based cache enabling support"
169 Select this if your processor suports enabling caches by using
173 bool "MMU-based Paged Memory Management Support"
174 select SYS_ARM_CACHE_CP15
176 Select if you want MMU-based virtualised addressing space
177 support via paged memory management.
180 bool 'Use the ARM v7 PMSA Compliant MPU'
182 Some ARM systems without an MMU have instead a Memory Protection
183 Unit (MPU) that defines the type and permissions for regions of
185 If your CPU has an MPU then you should choose 'y' here unless you
186 know that you do not want to use the MPU.
188 # If set, the workarounds for these ARM errata are applied early during U-Boot
189 # startup. Note that in general these options force the workarounds to be
190 # applied; no CPU-type/version detection exists, unlike the similar options in
191 # the Linux kernel. Do not set these options unless they apply! Also note that
192 # the following can be machine-specific errata. These do have ability to
193 # provide rudimentary version and machine-specific checks, but expect no
195 # CONFIG_ARM_ERRATA_430973
196 # CONFIG_ARM_ERRATA_454179
197 # CONFIG_ARM_ERRATA_621766
198 # CONFIG_ARM_ERRATA_798870
199 # CONFIG_ARM_ERRATA_801819
200 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
201 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
203 config ARM_ERRATA_430973
206 config ARM_ERRATA_454179
209 config ARM_ERRATA_621766
212 config ARM_ERRATA_716044
215 config ARM_ERRATA_725233
218 config ARM_ERRATA_742230
221 config ARM_ERRATA_743622
224 config ARM_ERRATA_751472
227 config ARM_ERRATA_761320
230 config ARM_ERRATA_773022
233 config ARM_ERRATA_774769
236 config ARM_ERRATA_794072
239 config ARM_ERRATA_798870
242 config ARM_ERRATA_801819
245 config ARM_ERRATA_826974
248 config ARM_ERRATA_828024
251 config ARM_ERRATA_829520
254 config ARM_ERRATA_833069
257 config ARM_ERRATA_833471
260 config ARM_ERRATA_845369
263 config ARM_ERRATA_852421
266 config ARM_ERRATA_852423
269 config ARM_ERRATA_855873
272 config ARM_CORTEX_A8_CVE_2017_5715
275 config ARM_CORTEX_A15_CVE_2017_5715
280 select SYS_CACHE_SHIFT_5
285 select SYS_CACHE_SHIFT_5
290 select SYS_CACHE_SHIFT_5
292 imply SPL_SEPARATE_BSS
296 select SYS_CACHE_SHIFT_5
301 select SYS_CACHE_SHIFT_5
303 imply SPL_SEPARATE_BSS
308 select SYS_CACHE_SHIFT_5
315 select SYS_CACHE_SHIFT_6
322 select SYS_CACHE_SHIFT_5
323 select SYS_THUMB_BUILD
329 select SYS_ARM_CACHE_CP15
331 select SYS_CACHE_SHIFT_6
334 default "arm720t" if CPU_ARM720T
335 default "arm920t" if CPU_ARM920T
336 default "arm926ejs" if CPU_ARM926EJS
337 default "arm946es" if CPU_ARM946ES
338 default "arm1136" if CPU_ARM1136
339 default "arm1176" if CPU_ARM1176
340 default "armv7" if CPU_V7A
341 default "armv7" if CPU_V7R
342 default "armv7m" if CPU_V7M
343 default "armv8" if ARM64
347 default 4 if CPU_ARM720T
348 default 4 if CPU_ARM920T
349 default 5 if CPU_ARM926EJS
350 default 5 if CPU_ARM946ES
351 default 6 if CPU_ARM1136
352 default 6 if CPU_ARM1176
359 prompt "Select the ARM data write cache policy"
360 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || RZA1
361 default SYS_ARM_CACHE_WRITEBACK
363 config SYS_ARM_CACHE_WRITEBACK
364 bool "Write-back (WB)"
366 A write updates the cache only and marks the cache line as dirty.
367 External memory is updated only when the line is evicted or explicitly
370 config SYS_ARM_CACHE_WRITETHROUGH
371 bool "Write-through (WT)"
373 A write updates both the cache and the external memory system.
374 This does not mark the cache line as dirty.
376 config SYS_ARM_CACHE_WRITEALLOC
377 bool "Write allocation (WA)"
379 A cache line is allocated on a write miss. This means that executing a
380 store instruction on the processor might cause a burst read to occur.
381 There is a linefill to obtain the data for the cache line, before the
385 config ARCH_VERY_EARLY_INIT
388 config SPL_ARCH_VERY_EARLY_INIT
392 bool "Enable ARCH_CPU_INIT"
394 Some architectures require a call to arch_cpu_init().
395 Say Y here to enable it
397 config SYS_ARCH_TIMER
398 bool "ARM Generic Timer support"
399 depends on CPU_V7A || ARM64
402 The ARM Generic Timer (aka arch-timer) provides an architected
403 interface to a timer source on an SoC.
404 It is mandatory for ARMv8 implementation and widely available
408 bool "Support for ARM SMC Calling Convention (SMCCC)"
409 depends on CPU_V7A || ARM64
412 Say Y here if you want to enable ARM SMC Calling Convention.
413 This should be enabled if U-Boot needs to communicate with system
414 firmware (for example, PSCI) according to SMCCC.
417 bool "Support ARM semihosting"
419 Semihosting is a method for a target to communicate with a host
420 debugger. It uses special instructions which the debugger will trap
421 on and interpret. This allows U-Boot to read/write files, print to
422 the console, and execute arbitrary commands on the host system.
424 Enabling this option will add support for reading and writing files
425 on the host system. If you don't have a debugger attached then trying
426 to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
428 config SEMIHOSTING_FALLBACK
429 bool "Recover gracefully when semihosting fails"
430 depends on SEMIHOSTING && ARM64
433 Normally, if U-Boot makes a semihosting call and no debugger is
434 attached, then it will panic due to a synchronous abort
435 exception. This config adds an exception handler which will allow
436 U-Boot to recover. Say 'y' if unsure.
438 config SPL_SEMIHOSTING
439 bool "Support ARM semihosting in SPL"
442 Semihosting is a method for a target to communicate with a host
443 debugger. It uses special instructions which the debugger will trap
444 on and interpret. This allows U-Boot to read/write files, print to
445 the console, and execute arbitrary commands on the host system.
447 Enabling this option will add support for reading and writing files
448 on the host system. If you don't have a debugger attached then trying
449 to do this will likely cause U-Boot to hang. Say 'n' if you are unsure.
451 config SPL_SEMIHOSTING_FALLBACK
452 bool "Recover gracefully when semihosting fails in SPL"
453 depends on SPL_SEMIHOSTING && ARM64
454 select ARMV8_SPL_EXCEPTION_VECTORS
457 Normally, if U-Boot makes a semihosting call and no debugger is
458 attached, then it will panic due to a synchronous abort
459 exception. This config adds an exception handler which will allow
460 U-Boot to recover. Say 'y' if unsure.
462 config SYS_THUMB_BUILD
463 bool "Build U-Boot using the Thumb instruction set"
466 Use this flag to build U-Boot using the Thumb instruction set for
467 ARM architectures. Thumb instruction set provides better code
468 density. For ARM architectures that support Thumb2 this flag will
469 result in Thumb2 code generated by GCC.
471 config SPL_SYS_THUMB_BUILD
472 bool "Build SPL using the Thumb instruction set"
473 default y if SYS_THUMB_BUILD
474 depends on !ARM64 && SPL
476 Use this flag to build SPL using the Thumb instruction set for
477 ARM architectures. Thumb instruction set provides better code
478 density. For ARM architectures that support Thumb2 this flag will
479 result in Thumb2 code generated by GCC.
481 config TPL_SYS_THUMB_BUILD
482 bool "Build TPL using the Thumb instruction set"
483 default y if SYS_THUMB_BUILD
484 depends on TPL && !ARM64
486 Use this flag to build TPL using the Thumb instruction set for
487 ARM architectures. Thumb instruction set provides better code
488 density. For ARM architectures that support Thumb2 this flag will
489 result in Thumb2 code generated by GCC.
492 bool "ARM PL310 L2 cache controller"
494 Enable support for ARM PL310 L2 cache controller in U-Boot
496 config SPL_SYS_L2_PL310
497 bool "ARM PL310 L2 cache controller in SPL"
499 Enable support for ARM PL310 L2 cache controller in SPL
501 config SYS_L2CACHE_OFF
504 If SoC does not support L2CACHE or one does not want to enable
505 L2CACHE, choose this option.
507 config ENABLE_ARM_SOC_BOOT0_HOOK
508 bool "prepare BOOT0 header"
510 If the SoC's BOOT0 requires a header area filled with (magic)
511 values, then choose this option, and create a file included as
512 <asm/arch/boot0.h> which contains the required assembler code.
514 config USE_ARCH_MEMCPY
515 bool "Use an assembly optimized implementation of memcpy"
517 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
519 Enable the generation of an optimized version of memcpy.
520 Such an implementation may be faster under some conditions
521 but may increase the binary size.
523 config SPL_USE_ARCH_MEMCPY
524 bool "Use an assembly optimized implementation of memcpy for SPL"
525 default y if USE_ARCH_MEMCPY
528 Enable the generation of an optimized version of memcpy.
529 Such an implementation may be faster under some conditions
530 but may increase the binary size.
532 config TPL_USE_ARCH_MEMCPY
533 bool "Use an assembly optimized implementation of memcpy for TPL"
534 default y if USE_ARCH_MEMCPY
537 Enable the generation of an optimized version of memcpy.
538 Such an implementation may be faster under some conditions
539 but may increase the binary size.
541 config USE_ARCH_MEMMOVE
542 bool "Use an assembly optimized implementation of memmove" if !ARM64
543 default USE_ARCH_MEMCPY if ARM64
546 Enable the generation of an optimized version of memmove.
547 Such an implementation may be faster under some conditions
548 but may increase the binary size.
550 config SPL_USE_ARCH_MEMMOVE
551 bool "Use an assembly optimized implementation of memmove for SPL" if !ARM64
552 default SPL_USE_ARCH_MEMCPY if ARM64
553 depends on SPL && ARM64
555 Enable the generation of an optimized version of memmove.
556 Such an implementation may be faster under some conditions
557 but may increase the binary size.
559 config TPL_USE_ARCH_MEMMOVE
560 bool "Use an assembly optimized implementation of memmove for TPL" if !ARM64
561 default TPL_USE_ARCH_MEMCPY if ARM64
562 depends on TPL && ARM64
564 Enable the generation of an optimized version of memmove.
565 Such an implementation may be faster under some conditions
566 but may increase the binary size.
568 config USE_ARCH_MEMSET
569 bool "Use an assembly optimized implementation of memset"
571 depends on !ARM64 || (ARM64 && (GCC_VERSION >= 90400))
573 Enable the generation of an optimized version of memset.
574 Such an implementation may be faster under some conditions
575 but may increase the binary size.
577 config SPL_USE_ARCH_MEMSET
578 bool "Use an assembly optimized implementation of memset for SPL"
579 default y if USE_ARCH_MEMSET
582 Enable the generation of an optimized version of memset.
583 Such an implementation may be faster under some conditions
584 but may increase the binary size.
586 config TPL_USE_ARCH_MEMSET
587 bool "Use an assembly optimized implementation of memset for TPL"
588 default y if USE_ARCH_MEMSET
591 Enable the generation of an optimized version of memset.
592 Such an implementation may be faster under some conditions
593 but may increase the binary size.
595 config ARM64_SUPPORT_AARCH32
596 bool "ARM64 system support AArch32 execution state"
598 default y if !TARGET_THUNDERX_88XX
600 This ARM64 system supports AArch32 execution state.
603 def_bool y if ARCH_EXYNOS || ARCH_S5PC1XX
606 prompt "Target select"
611 select GPIO_EXTRA_HEADER
612 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
613 select SPL_SEPARATE_BSS if SPL
618 select GPIO_EXTRA_HEADER
619 select SPL_DM_SPI if SPL
622 Support for TI's DaVinci platform.
625 bool "Marvell Kirkwood"
626 select ARCH_MISC_INIT
627 select BOARD_EARLY_INIT_F
629 select GPIO_EXTRA_HEADER
633 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
639 select GPIO_EXTRA_HEADER
640 select SPL_DM_SPI if SPL
641 select SPL_DM_SPI_FLASH if SPL
642 select SPL_TIMER if SPL
652 select GPIO_EXTRA_HEADER
653 select SPL_SEPARATE_BSS if SPL
656 config TARGET_STV0991
657 bool "Support stv0991"
663 select GPIO_EXTRA_HEADER
670 bool "Broadcom BCM283X family"
674 select GPIO_EXTRA_HEADER
677 select SERIAL_SEARCH_ALL
682 bool "Broadcom BCM7XXX family"
685 select GPIO_EXTRA_HEADER
688 imply OF_HAS_PRIOR_STAGE
690 This enables support for Broadcom ARM-based set-top box
691 chipsets, including the 7445 family of chips.
694 bool "Broadcom broadband chip family"
699 config TARGET_VEXPRESS_CA9X4
700 bool "Support vexpress_ca9x4"
704 config TARGET_BCMCYGNUS
705 bool "Support bcmcygnus"
707 select GPIO_EXTRA_HEADER
709 imply BCM_SF2_ETH_GMAC
717 bool "Support Broadcom Northstar2"
719 select GPIO_EXTRA_HEADER
721 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
722 ARMv8 Cortex-A57 processors targeting a broad range of networking
726 bool "Support Broadcom NS3"
728 select BOARD_LATE_INIT
730 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
731 ARMv8 Cortex-A72 processors targeting a broad range of networking
735 bool "Samsung EXYNOS"
745 select GPIO_EXTRA_HEADER
746 imply SYS_THUMB_BUILD
751 bool "Samsung S5PC1XX"
757 select GPIO_EXTRA_HEADER
761 bool "Calxeda Highbank"
774 imply OF_HAS_PRIOR_STAGE
776 config ARCH_INTEGRATOR
777 bool "ARM Ltd. Integrator family"
780 select GPIO_EXTRA_HEADER
785 bool "Qualcomm IPQ40xx SoCs"
791 select GPIO_EXTRA_HEADER
805 select SYS_ARCH_TIMER
806 select SYS_THUMB_BUILD
812 bool "Texas Instruments' K3 Architecture"
817 config ARCH_OMAP2PLUS
820 select GPIO_EXTRA_HEADER
821 select SPL_BOARD_INIT if SPL
822 select SPL_STACK_R if SPL
824 imply TI_SYSC if DM && OF_CONTROL
827 imply SPL_SEPARATE_BSS
831 select GPIO_EXTRA_HEADER
832 imply DISTRO_DEFAULTS
835 Support for the Meson SoC family developed by Amlogic Inc.,
836 targeted at media players and tablet computers. We currently
837 support the S905 (GXBaby) 64-bit SoC.
842 select GPIO_EXTRA_HEADER
845 select SPL_LIBCOMMON_SUPPORT if SPL
846 select SPL_LIBGENERIC_SUPPORT if SPL
847 select SPL_OF_CONTROL if SPL
850 Support for the MediaTek SoCs family developed by MediaTek Inc.
851 Please refer to doc/README.mediatek for more information.
854 bool "NXP LPC32xx platform"
859 select GPIO_EXTRA_HEADER
865 bool "NXP i.MX8 platform"
867 select SYS_FSL_HAS_SEC
868 select SYS_FSL_SEC_COMPAT_4
869 select SYS_FSL_SEC_LE
871 select GPIO_EXTRA_HEADER
874 select ENABLE_ARM_SOC_BOOT0_HOOK
878 bool "NXP i.MX8M platform"
880 select GPIO_EXTRA_HEADER
882 select SYS_FSL_HAS_SEC
883 select SYS_FSL_SEC_COMPAT_4
884 select SYS_FSL_SEC_LE
892 bool "NXP i.MX8ULP platform"
898 select GPIO_EXTRA_HEADER
905 bool "NXP i.MX9 platform"
910 select GPIO_EXTRA_HEADER
917 bool "NXP i.MXRT platform"
921 select GPIO_EXTRA_HEADER
927 bool "NXP i.MX23 family"
929 select GPIO_EXTRA_HEADER
935 bool "NXP i.MX28 family"
937 select GPIO_EXTRA_HEADER
943 bool "NXP i.MX31 family"
945 select GPIO_EXTRA_HEADER
950 select BOARD_POSTCLK_INIT
952 select GPIO_EXTRA_HEADER
954 select SYS_FSL_HAS_SEC
955 select SYS_FSL_SEC_COMPAT_4
956 select SYS_FSL_SEC_LE
957 select ROM_UNIFIED_SECTIONS
959 imply SYS_THUMB_BUILD
963 select ARCH_MISC_INIT
965 select GPIO_EXTRA_HEADER
967 select SYS_FSL_HAS_SEC
968 select SYS_FSL_SEC_COMPAT_4
969 select SYS_FSL_SEC_LE
970 imply BOARD_EARLY_INIT_F
972 imply SYS_THUMB_BUILD
976 select BOARD_POSTCLK_INIT
978 select GPIO_EXTRA_HEADER
980 select SYS_FSL_HAS_SEC
981 select SYS_FSL_SEC_COMPAT_4
982 select SYS_FSL_SEC_LE
983 select SYS_L2_PL310 if !SYS_L2CACHE_OFF
985 imply SYS_THUMB_BUILD
986 imply SPL_SEPARATE_BSS
990 select BOARD_EARLY_INIT_F
992 select GPIO_EXTRA_HEADER
997 bool "Nexell S5P4418/S5P6818 SoC"
998 select ENABLE_ARM_SOC_BOOT0_HOOK
1000 select GPIO_EXTRA_HEADER
1003 bool "Support Nuvoton SoCs"
1023 select LINUX_KERNEL_IMAGE_HEADER
1024 select OF_BOARD_SETUP
1027 select POSITION_INDEPENDENT
1033 select SYSRESET_WATCHDOG
1034 select SYSRESET_WATCHDOG_AUTO
1038 imply DISTRO_DEFAULTS
1039 imply OF_HAS_PRIOR_STAGE
1042 bool "Actions Semi OWL SoCs"
1046 select GPIO_EXTRA_HEADER
1051 select SYS_RELOC_GD_ENV_ADDR
1055 bool "QEMU Virtual Platform"
1064 imply OF_HAS_PRIOR_STAGE
1067 bool "Renesas ARM SoCs"
1070 select GPIO_EXTRA_HEADER
1071 imply BOARD_EARLY_INIT_F
1074 imply SYS_THUMB_BUILD
1075 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
1077 config ARCH_SNAPDRAGON
1078 bool "Qualcomm Snapdragon SoCs"
1083 select GPIO_EXTRA_HEADER
1092 bool "Altera SOCFPGA family"
1093 select ARCH_EARLY_INIT_R
1094 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
1095 select ARM64 if TARGET_SOCFPGA_SOC64
1096 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1100 select GPIO_EXTRA_HEADER
1101 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1103 select SPL_DM_RESET if DM_RESET
1104 select SPL_DM_SERIAL
1105 select SPL_LIBCOMMON_SUPPORT
1106 select SPL_LIBGENERIC_SUPPORT
1107 select SPL_OF_CONTROL
1108 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
1114 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1116 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
1117 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
1127 imply SPL_DM_SPI_FLASH
1128 imply SPL_LIBDISK_SUPPORT
1130 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
1131 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
1132 imply SPL_SPI_FLASH_SUPPORT
1137 bool "Support sunxi (Allwinner) SoCs"
1140 select CMD_MMC if MMC
1141 select CMD_USB if DISTRO_DEFAULTS && USB_HOST
1146 select DM_I2C if I2C
1147 select DM_SPI if SPI
1148 select DM_SPI_FLASH if SPI
1150 select DM_MMC if MMC
1151 select DM_SCSI if SCSI
1153 select GPIO_EXTRA_HEADER
1154 select OF_BOARD_SETUP
1158 select SPECIFY_CONSOLE_INDEX
1159 select SPL_SEPARATE_BSS if SPL
1160 select SPL_STACK_R if SPL
1161 select SPL_SYS_MALLOC_SIMPLE if SPL
1162 select SPL_SYS_THUMB_BUILD if !ARM64
1165 select SYS_THUMB_BUILD if !ARM64
1166 select USB if DISTRO_DEFAULTS
1167 select USB_KEYBOARD if DISTRO_DEFAULTS && USB_HOST
1168 select USB_STORAGE if DISTRO_DEFAULTS && USB_HOST
1169 select SPL_USE_TINY_PRINTF
1171 select SYS_RELOC_GD_ENV_ADDR
1172 imply BOARD_LATE_INIT
1175 imply CMD_UBI if MTD_RAW_NAND
1176 imply DISTRO_DEFAULTS
1179 imply OF_LIBFDT_OVERLAY
1180 imply PRE_CONSOLE_BUFFER
1182 imply SPL_LIBCOMMON_SUPPORT
1183 imply SPL_LIBGENERIC_SUPPORT
1184 imply SPL_MMC if MMC
1188 imply SYSRESET_WATCHDOG
1189 imply SYSRESET_WATCHDOG_AUTO
1194 bool "ST-Ericsson U8500 Series"
1198 select DM_MMC if MMC
1200 select DM_USB_GADGET if DM_USB
1204 imply AB8500_USB_PHY
1205 imply ARM_PL180_MMCI
1210 imply NOMADIK_MTU_TIMER
1215 imply SYS_THUMB_BUILD
1216 imply SYSRESET_SYSCON
1219 bool "Support Xilinx Versal Platform"
1223 select DM_ETH if NET
1224 select DM_MMC if MMC
1229 imply BOARD_LATE_INIT
1230 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1232 config ARCH_VERSAL_NET
1233 bool "Support Xilinx Keystone Platform"
1237 select DM_ETH if NET
1238 select DM_MMC if MMC
1241 imply BOARD_LATE_INIT
1242 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1245 bool "Freescale Vybrid"
1247 select GPIO_EXTRA_HEADER
1249 select SYS_FSL_ERRATUM_ESDHC111
1254 bool "Xilinx Zynq based platform"
1255 select ARM_TWD_TIMER
1259 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1261 select DM_ETH if NET
1262 select DM_MMC if MMC
1268 select SPL_BOARD_INIT if SPL
1269 select SPL_CLK if SPL
1270 select SPL_DM if SPL
1271 select SPL_DM_SPI if SPL
1272 select SPL_DM_SPI_FLASH if SPL
1273 select SPL_OF_CONTROL if SPL
1274 select SPL_SEPARATE_BSS if SPL
1275 select SPL_TIMER if SPL
1278 imply ARCH_EARLY_INIT_R
1279 imply BOARD_LATE_INIT
1283 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1286 config ARCH_ZYNQMP_R5
1287 bool "Xilinx ZynqMP R5 based platform"
1291 select DM_ETH if NET
1292 select DM_MMC if MMC
1299 bool "Xilinx ZynqMP based platform"
1303 select DEBUG_UART_BOARD_INIT if SPL && DEBUG_UART
1304 select DM_ETH if NET
1306 select DM_MMC if MMC
1308 select DM_SPI if SPI
1309 select DM_SPI_FLASH if DM_SPI
1313 select SPL_BOARD_INIT if SPL
1314 select SPL_CLK if SPL
1315 select SPL_DM if SPL
1316 select SPL_DM_SPI if SPI && SPL_DM
1317 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1318 select SPL_DM_MAILBOX if SPL
1319 imply SPL_FIRMWARE if SPL
1320 select SPL_SEPARATE_BSS if SPL
1324 imply BOARD_LATE_INIT
1326 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1330 imply ZYNQMP_GPIO_MODEPIN if DM_GPIO && USB
1334 select GPIO_EXTRA_HEADER
1335 imply DISTRO_DEFAULTS
1338 config ARCH_VEXPRESS64
1339 bool "Support ARMv8 Arm Ltd. VExpress based boards and models"
1347 select MTD_NOR_FLASH if MTD
1348 select FLASH_CFI_DRIVER if MTD
1349 select ENV_IS_IN_FLASH if MTD
1350 imply DISTRO_DEFAULTS
1352 config TARGET_CORSTONE1000
1353 bool "Support Corstone1000 Platform"
1358 config TARGET_TOTAL_COMPUTE
1359 bool "Support Total Compute Platform"
1367 config TARGET_LS2080A_EMU
1368 bool "Support ls2080a_emu"
1371 select ARMV8_MULTIENTRY
1372 select FSL_DDR_SYNC_REFRESH
1373 select GPIO_EXTRA_HEADER
1375 Support for Freescale LS2080A_EMU platform.
1376 The LS2080A Development System (EMULATOR) is a pre-silicon
1377 development platform that supports the QorIQ LS2080A
1378 Layerscape Architecture processor.
1380 config TARGET_LS1088AQDS
1381 bool "Support ls1088aqds"
1384 select ARMV8_MULTIENTRY
1385 select ARCH_SUPPORT_TFABOOT
1386 select BOARD_LATE_INIT
1387 select GPIO_EXTRA_HEADER
1389 select FSL_DDR_INTERACTIVE if !SD_BOOT
1391 Support for NXP LS1088AQDS platform.
1392 The LS1088A Development System (QDS) is a high-performance
1393 development platform that supports the QorIQ LS1088A
1394 Layerscape Architecture processor.
1396 config TARGET_LS2080AQDS
1397 bool "Support ls2080aqds"
1400 select ARMV8_MULTIENTRY
1401 select ARCH_SUPPORT_TFABOOT
1402 select BOARD_LATE_INIT
1403 select GPIO_EXTRA_HEADER
1408 select FSL_DDR_INTERACTIVE if !SPL
1410 Support for Freescale LS2080AQDS platform.
1411 The LS2080A Development System (QDS) is a high-performance
1412 development platform that supports the QorIQ LS2080A
1413 Layerscape Architecture processor.
1415 config TARGET_LS2080ARDB
1416 bool "Support ls2080ardb"
1419 select ARMV8_MULTIENTRY
1420 select ARCH_SUPPORT_TFABOOT
1421 select BOARD_LATE_INIT
1424 select FSL_DDR_INTERACTIVE if !SPL
1425 select GPIO_EXTRA_HEADER
1429 Support for Freescale LS2080ARDB platform.
1430 The LS2080A Reference design board (RDB) is a high-performance
1431 development platform that supports the QorIQ LS2080A
1432 Layerscape Architecture processor.
1434 config TARGET_LS2081ARDB
1435 bool "Support ls2081ardb"
1438 select ARMV8_MULTIENTRY
1439 select BOARD_LATE_INIT
1440 select GPIO_EXTRA_HEADER
1443 Support for Freescale LS2081ARDB platform.
1444 The LS2081A Reference design board (RDB) is a high-performance
1445 development platform that supports the QorIQ LS2081A/LS2041A
1446 Layerscape Architecture processor.
1448 config TARGET_LX2160ARDB
1449 bool "Support lx2160ardb"
1452 select ARMV8_MULTIENTRY
1453 select ARCH_SUPPORT_TFABOOT
1454 select BOARD_LATE_INIT
1455 select GPIO_EXTRA_HEADER
1457 Support for NXP LX2160ARDB platform.
1458 The lx2160ardb (LX2160A Reference design board (RDB)
1459 is a high-performance development platform that supports the
1460 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1462 config TARGET_LX2160AQDS
1463 bool "Support lx2160aqds"
1466 select ARMV8_MULTIENTRY
1467 select ARCH_SUPPORT_TFABOOT
1468 select BOARD_LATE_INIT
1469 select GPIO_EXTRA_HEADER
1471 Support for NXP LX2160AQDS platform.
1472 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1473 is a high-performance development platform that supports the
1474 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1476 config TARGET_LX2162AQDS
1477 bool "Support lx2162aqds"
1479 select ARCH_MISC_INIT
1481 select ARMV8_MULTIENTRY
1482 select ARCH_SUPPORT_TFABOOT
1483 select BOARD_LATE_INIT
1484 select GPIO_EXTRA_HEADER
1486 Support for NXP LX2162AQDS platform.
1487 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1490 bool "Support HiKey 96boards Consumer Edition Platform"
1495 select GPIO_EXTRA_HEADER
1498 select SPECIFY_CONSOLE_INDEX
1501 Support for HiKey 96boards platform. It features a HI6220
1502 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1504 config TARGET_HIKEY960
1505 bool "Support HiKey960 96boards Consumer Edition Platform"
1509 select GPIO_EXTRA_HEADER
1514 Support for HiKey960 96boards platform. It features a HI3660
1515 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1517 config TARGET_POPLAR
1518 bool "Support Poplar 96boards Enterprise Edition Platform"
1522 select GPIO_EXTRA_HEADER
1527 Support for Poplar 96boards EE platform. It features a HI3798cv200
1528 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1529 making it capable of running any commercial set-top solution based on
1532 config TARGET_LS1012AQDS
1533 bool "Support ls1012aqds"
1536 select ARCH_SUPPORT_TFABOOT
1537 select BOARD_LATE_INIT
1538 select GPIO_EXTRA_HEADER
1540 Support for Freescale LS1012AQDS platform.
1541 The LS1012A Development System (QDS) is a high-performance
1542 development platform that supports the QorIQ LS1012A
1543 Layerscape Architecture processor.
1545 config TARGET_LS1012ARDB
1546 bool "Support ls1012ardb"
1549 select ARCH_SUPPORT_TFABOOT
1550 select BOARD_LATE_INIT
1551 select GPIO_EXTRA_HEADER
1555 Support for Freescale LS1012ARDB platform.
1556 The LS1012A Reference design board (RDB) is a high-performance
1557 development platform that supports the QorIQ LS1012A
1558 Layerscape Architecture processor.
1560 config TARGET_LS1012A2G5RDB
1561 bool "Support ls1012a2g5rdb"
1564 select ARCH_SUPPORT_TFABOOT
1565 select BOARD_LATE_INIT
1566 select GPIO_EXTRA_HEADER
1569 Support for Freescale LS1012A2G5RDB platform.
1570 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1571 development platform that supports the QorIQ LS1012A
1572 Layerscape Architecture processor.
1574 config TARGET_LS1012AFRWY
1575 bool "Support ls1012afrwy"
1578 select ARCH_SUPPORT_TFABOOT
1579 select BOARD_LATE_INIT
1580 select GPIO_EXTRA_HEADER
1584 Support for Freescale LS1012AFRWY platform.
1585 The LS1012A FRWY board (FRWY) is a high-performance
1586 development platform that supports the QorIQ LS1012A
1587 Layerscape Architecture processor.
1589 config TARGET_LS1012AFRDM
1590 bool "Support ls1012afrdm"
1593 select ARCH_SUPPORT_TFABOOT
1594 select GPIO_EXTRA_HEADER
1596 Support for Freescale LS1012AFRDM platform.
1597 The LS1012A Freedom board (FRDM) is a high-performance
1598 development platform that supports the QorIQ LS1012A
1599 Layerscape Architecture processor.
1601 config TARGET_LS1028AQDS
1602 bool "Support ls1028aqds"
1605 select ARMV8_MULTIENTRY
1606 select ARCH_SUPPORT_TFABOOT
1607 select BOARD_LATE_INIT
1608 select GPIO_EXTRA_HEADER
1610 Support for Freescale LS1028AQDS platform
1611 The LS1028A Development System (QDS) is a high-performance
1612 development platform that supports the QorIQ LS1028A
1613 Layerscape Architecture processor.
1615 config TARGET_LS1028ARDB
1616 bool "Support ls1028ardb"
1619 select ARMV8_MULTIENTRY
1620 select ARCH_SUPPORT_TFABOOT
1621 select BOARD_LATE_INIT
1622 select GPIO_EXTRA_HEADER
1624 Support for Freescale LS1028ARDB platform
1625 The LS1028A Development System (RDB) is a high-performance
1626 development platform that supports the QorIQ LS1028A
1627 Layerscape Architecture processor.
1629 config TARGET_LS1088ARDB
1630 bool "Support ls1088ardb"
1633 select ARMV8_MULTIENTRY
1634 select ARCH_SUPPORT_TFABOOT
1635 select BOARD_LATE_INIT
1637 select FSL_DDR_INTERACTIVE if !SD_BOOT
1638 select GPIO_EXTRA_HEADER
1640 Support for NXP LS1088ARDB platform.
1641 The LS1088A Reference design board (RDB) is a high-performance
1642 development platform that supports the QorIQ LS1088A
1643 Layerscape Architecture processor.
1645 config TARGET_LS1021AQDS
1646 bool "Support ls1021aqds"
1648 select ARCH_SUPPORT_PSCI
1649 select BOARD_EARLY_INIT_F
1650 select BOARD_LATE_INIT
1652 select CPU_V7_HAS_NONSEC
1653 select CPU_V7_HAS_VIRT
1654 select LS1_DEEP_SLEEP
1657 select FSL_DDR_INTERACTIVE
1658 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1659 select GPIO_EXTRA_HEADER
1660 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1663 config TARGET_LS1021ATWR
1664 bool "Support ls1021atwr"
1666 select ARCH_SUPPORT_PSCI
1667 select BOARD_EARLY_INIT_F
1668 select BOARD_LATE_INIT
1670 select CPU_V7_HAS_NONSEC
1671 select CPU_V7_HAS_VIRT
1672 select LS1_DEEP_SLEEP
1674 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1675 select GPIO_EXTRA_HEADER
1678 config TARGET_PG_WCOM_SELI8
1679 bool "Support Hitachi-Powergrids SELI8 service unit card"
1681 select ARCH_SUPPORT_PSCI
1682 select BOARD_EARLY_INIT_F
1683 select BOARD_LATE_INIT
1685 select CPU_V7_HAS_NONSEC
1686 select CPU_V7_HAS_VIRT
1688 select FSL_DDR_INTERACTIVE
1689 select GPIO_EXTRA_HEADER
1693 Support for Hitachi-Powergrids SELI8 service unit card.
1694 SELI8 is a QorIQ LS1021a based service unit card used
1695 in XMC20 and FOX615 product families.
1697 config TARGET_PG_WCOM_EXPU1
1698 bool "Support Hitachi-Powergrids EXPU1 service unit card"
1700 select ARCH_SUPPORT_PSCI
1701 select BOARD_EARLY_INIT_F
1702 select BOARD_LATE_INIT
1704 select CPU_V7_HAS_NONSEC
1705 select CPU_V7_HAS_VIRT
1707 select FSL_DDR_INTERACTIVE
1711 Support for Hitachi-Powergrids EXPU1 service unit card.
1712 EXPU1 is a QorIQ LS1021a based service unit card used
1713 in XMC20 and FOX615 product families.
1715 config TARGET_LS1021ATSN
1716 bool "Support ls1021atsn"
1718 select ARCH_SUPPORT_PSCI
1719 select BOARD_EARLY_INIT_F
1720 select BOARD_LATE_INIT
1722 select CPU_V7_HAS_NONSEC
1723 select CPU_V7_HAS_VIRT
1724 select LS1_DEEP_SLEEP
1726 select GPIO_EXTRA_HEADER
1729 config TARGET_LS1021AIOT
1730 bool "Support ls1021aiot"
1732 select ARCH_SUPPORT_PSCI
1733 select BOARD_LATE_INIT
1735 select CPU_V7_HAS_NONSEC
1736 select CPU_V7_HAS_VIRT
1738 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1739 select GPIO_EXTRA_HEADER
1742 Support for Freescale LS1021AIOT platform.
1743 The LS1021A Freescale board (IOT) is a high-performance
1744 development platform that supports the QorIQ LS1021A
1745 Layerscape Architecture processor.
1747 config TARGET_LS1043AQDS
1748 bool "Support ls1043aqds"
1751 select ARMV8_MULTIENTRY
1752 select ARCH_SUPPORT_TFABOOT
1753 select BOARD_EARLY_INIT_F
1754 select BOARD_LATE_INIT
1756 select FSL_DDR_INTERACTIVE if !SPL
1757 select FSL_DSPI if !SPL_NO_DSPI
1758 select DM_SPI_FLASH if FSL_DSPI
1759 select GPIO_EXTRA_HEADER
1763 Support for Freescale LS1043AQDS platform.
1765 config TARGET_LS1043ARDB
1766 bool "Support ls1043ardb"
1769 select ARMV8_MULTIENTRY
1770 select ARCH_SUPPORT_TFABOOT
1771 select BOARD_EARLY_INIT_F
1772 select BOARD_LATE_INIT
1774 select FSL_DSPI if !SPL_NO_DSPI
1775 select DM_SPI_FLASH if FSL_DSPI
1776 select GPIO_EXTRA_HEADER
1778 Support for Freescale LS1043ARDB platform.
1780 config TARGET_LS1046AQDS
1781 bool "Support ls1046aqds"
1784 select ARMV8_MULTIENTRY
1785 select ARCH_SUPPORT_TFABOOT
1786 select BOARD_EARLY_INIT_F
1787 select BOARD_LATE_INIT
1788 select DM_SPI_FLASH if DM_SPI
1790 select FSL_DDR_BIST if !SPL
1791 select FSL_DDR_INTERACTIVE if !SPL
1792 select FSL_DDR_INTERACTIVE if !SPL
1793 select GPIO_EXTRA_HEADER
1796 Support for Freescale LS1046AQDS platform.
1797 The LS1046A Development System (QDS) is a high-performance
1798 development platform that supports the QorIQ LS1046A
1799 Layerscape Architecture processor.
1801 config TARGET_LS1046ARDB
1802 bool "Support ls1046ardb"
1805 select ARMV8_MULTIENTRY
1806 select ARCH_SUPPORT_TFABOOT
1807 select BOARD_EARLY_INIT_F
1808 select BOARD_LATE_INIT
1809 select DM_SPI_FLASH if DM_SPI
1810 select POWER_MC34VR500
1813 select FSL_DDR_INTERACTIVE if !SPL
1814 select GPIO_EXTRA_HEADER
1817 Support for Freescale LS1046ARDB platform.
1818 The LS1046A Reference Design Board (RDB) is a high-performance
1819 development platform that supports the QorIQ LS1046A
1820 Layerscape Architecture processor.
1822 config TARGET_LS1046AFRWY
1823 bool "Support ls1046afrwy"
1826 select ARMV8_MULTIENTRY
1827 select ARCH_SUPPORT_TFABOOT
1828 select BOARD_EARLY_INIT_F
1829 select BOARD_LATE_INIT
1830 select DM_SPI_FLASH if DM_SPI
1831 select GPIO_EXTRA_HEADER
1834 Support for Freescale LS1046AFRWY platform.
1835 The LS1046A Freeway Board (FRWY) is a high-performance
1836 development platform that supports the QorIQ LS1046A
1837 Layerscape Architecture processor.
1843 select ARMV8_MULTIENTRY
1859 select GPIO_EXTRA_HEADER
1860 select SPL_DM if SPL
1861 select SPL_DM_SPI if SPL
1862 select SPL_DM_SPI_FLASH if SPL
1863 select SPL_DM_I2C if SPL
1864 select SPL_DM_MMC if SPL
1865 select SPL_DM_SERIAL if SPL
1867 Support for Kontron SMARC-sAL28 board.
1870 bool "Support ten64"
1872 select ARCH_MISC_INIT
1874 select ARMV8_MULTIENTRY
1875 select ARCH_SUPPORT_TFABOOT
1876 select BOARD_LATE_INIT
1878 select FSL_DDR_INTERACTIVE if !SD_BOOT
1879 select GPIO_EXTRA_HEADER
1881 Support for Traverse Technologies Ten64 board, based
1884 config ARCH_UNIPHIER
1885 bool "Socionext UniPhier SoCs"
1886 select BOARD_LATE_INIT
1895 select OF_BOARD_SETUP
1899 select SPL_BOARD_INIT if SPL
1900 select SPL_DM if SPL
1901 select SPL_LIBCOMMON_SUPPORT if SPL
1902 select SPL_LIBGENERIC_SUPPORT if SPL
1903 select SPL_OF_CONTROL if SPL
1904 select SPL_PINCTRL if SPL
1907 imply DISTRO_DEFAULTS
1910 Support for UniPhier SoC family developed by Socionext Inc.
1911 (formerly, System LSI Business Division of Panasonic Corporation)
1913 config ARCH_SYNQUACER
1914 bool "Socionext SynQuacer SoCs"
1920 select SYSRESET_PSCI
1923 Support for SynQuacer SoC family developed by Socionext Inc.
1924 This SoC is used on 96boards EE DeveloperBox.
1927 bool "Support STMicroelectronics STM32 MCU with cortex M"
1934 bool "Support STMicroelectronics SoCs"
1943 Support for STMicroelectronics STiH407/10 SoC family.
1944 This SoC is used on Linaro 96Board STiH410-B2260
1947 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1948 select ARCH_MISC_INIT
1949 select ARCH_SUPPORT_TFABOOT
1950 select BOARD_LATE_INIT
1959 select OF_SYSTEM_SETUP
1964 select SYS_THUMB_BUILD
1968 imply OF_LIBFDT_OVERLAY
1969 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1973 Support for STM32MP SoC family developed by STMicroelectronics,
1974 MPUs based on ARM cortex A core
1975 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1976 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1978 SPL is the unsecure FSBL for the basic boot chain.
1980 config ARCH_ROCKCHIP
1981 bool "Support Rockchip SoCs"
1983 select BINMAN if SPL_OPTEE || SPL
1993 select ENABLE_ARM_SOC_BOOT0_HOOK
1996 select SPL_DM if SPL
1997 select SPL_DM_SPI if SPL
1998 select SPL_DM_SPI_FLASH if SPL
2000 select SYS_THUMB_BUILD if !ARM64
2003 imply DEBUG_UART_BOARD_INIT
2004 imply DISTRO_DEFAULTS
2006 imply SARADC_ROCKCHIP
2008 imply SPL_SYS_MALLOC_SIMPLE
2011 imply USB_FUNCTION_FASTBOOT
2013 config ARCH_OCTEONTX
2014 bool "Support OcteonTX SoCs"
2017 select GPIO_EXTRA_HEADER
2021 select BOARD_LATE_INIT
2022 select SYS_CACHE_SHIFT_7
2023 select SYS_PCI_64BIT if PCI
2024 imply OF_HAS_PRIOR_STAGE
2026 config ARCH_OCTEONTX2
2027 bool "Support OcteonTX2 SoCs"
2030 select GPIO_EXTRA_HEADER
2034 select BOARD_LATE_INIT
2035 select SYS_CACHE_SHIFT_7
2036 select SYS_PCI_64BIT if PCI
2037 imply OF_HAS_PRIOR_STAGE
2039 config TARGET_THUNDERX_88XX
2040 bool "Support ThunderX 88xx"
2042 select GPIO_EXTRA_HEADER
2045 select SYS_CACHE_SHIFT_7
2048 bool "Support Aspeed SoCs"
2053 config TARGET_DURIAN
2054 bool "Support Phytium Durian Platform"
2056 select GPIO_EXTRA_HEADER
2058 Support for durian platform.
2059 It has 2GB Sdram, uart and pcie.
2061 config TARGET_POMELO
2062 bool "Support Phytium Pomelo Platform"
2074 select DM_ETH if NET
2077 Support for pomelo platform.
2078 It has 8GB Sdram, uart and pcie.
2080 config TARGET_PRESIDIO_ASIC
2081 bool "Support Cortina Presidio ASIC Platform"
2085 config TARGET_XENGUEST_ARM64
2086 bool "Xen guest ARM64"
2090 select LINUX_KERNEL_IMAGE_HEADER
2093 imply OF_HAS_PRIOR_STAGE
2096 bool "Support HPE GXP SoCs"
2103 config SUPPORT_PASSING_ATAGS
2104 bool "Support pre-devicetree ATAG-based booting"
2106 imply SETUP_MEMORY_TAGS
2108 Support for booting older Linux kernels, using ATAGs rather than
2109 passing a devicetree. This is option is rarely used, and the
2110 semantics are defined at
2111 https://www.kernel.org/doc/Documentation/arm/Booting at section 4a.
2113 config SETUP_MEMORY_TAGS
2114 bool "Pass memory size information via ATAG"
2115 depends on SUPPORT_PASSING_ATAGS
2118 bool "Pass Linux kernel cmdline via ATAG"
2119 depends on SUPPORT_PASSING_ATAGS
2122 bool "Pass initrd starting point and size via ATAG"
2123 depends on SUPPORT_PASSING_ATAGS
2126 bool "Pass system revision via ATAG"
2127 depends on SUPPORT_PASSING_ATAGS
2130 bool "Pass system serial number via ATAG"
2131 depends on SUPPORT_PASSING_ATAGS
2133 config STATIC_MACH_TYPE
2134 bool "Statically define the Machine ID number"
2135 default y if TARGET_DS109 || TARGET_NOKIA_RX51 || TARGET_DS414 || DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2137 When booting via ATAGs, enable this option if we know the correct
2138 machine ID number to use at compile time. Some systems will be
2139 passed the number dynamically by whatever loads U-Boot.
2142 int "Machine ID number"
2143 depends on STATIC_MACH_TYPE
2144 default 527 if TARGET_DS109
2145 default 1955 if TARGET_NOKIA_RX51
2146 default 3036 if TARGET_DS414
2147 default 4283 if DEFAULT_DEVICE_TREE = "sun7i-a20-icnova-swac"
2149 When booting via ATAGs, the machine type must be passed as a number.
2150 For the full list see https://www.arm.linux.org.uk/developer/machines
2152 config ARCH_SUPPORT_TFABOOT
2156 bool "Support for booting from TF-A"
2157 depends on ARCH_SUPPORT_TFABOOT
2159 Some platforms support the setup of secure registers (for instance
2160 for CPU errata handling) or provide secure services like PSCI.
2161 Those services could also be provided by other firmware parts
2162 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
2163 does not need to (and cannot) execute this code.
2164 Enabling this option will make a U-Boot binary that is relying
2165 on other firmware layers to provide secure functionality.
2167 config TI_SECURE_DEVICE
2168 bool "HS Device Type Support"
2169 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
2171 If a high secure (HS) device type is being used, this config
2172 must be set. This option impacts various aspects of the
2173 build system (to create signed boot images that can be
2174 authenticated) and the code. See the doc/README.ti-secure
2175 file for further details.
2177 config SYS_KWD_CONFIG
2178 string "kwbimage config file path"
2179 depends on ARCH_KIRKWOOD || ARCH_MVEBU
2180 default "arch/arm/mach-mvebu/kwbimage.cfg"
2182 Path within the source directory to the kwbimage.cfg file to use
2183 when packaging the U-Boot image for use.
2185 source "arch/arm/mach-apple/Kconfig"
2187 source "arch/arm/mach-aspeed/Kconfig"
2189 source "arch/arm/mach-at91/Kconfig"
2191 source "arch/arm/mach-bcm283x/Kconfig"
2193 source "arch/arm/mach-bcmbca/Kconfig"
2195 source "arch/arm/mach-bcmstb/Kconfig"
2197 source "arch/arm/mach-davinci/Kconfig"
2199 source "arch/arm/mach-exynos/Kconfig"
2201 source "arch/arm/mach-hpe/gxp/Kconfig"
2203 source "arch/arm/mach-highbank/Kconfig"
2205 source "arch/arm/mach-integrator/Kconfig"
2207 source "arch/arm/mach-ipq40xx/Kconfig"
2209 source "arch/arm/mach-k3/Kconfig"
2211 source "arch/arm/mach-keystone/Kconfig"
2213 source "arch/arm/mach-kirkwood/Kconfig"
2215 source "arch/arm/mach-lpc32xx/Kconfig"
2217 source "arch/arm/mach-mvebu/Kconfig"
2219 source "arch/arm/mach-octeontx/Kconfig"
2221 source "arch/arm/mach-octeontx2/Kconfig"
2223 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
2225 source "arch/arm/mach-imx/mx3/Kconfig"
2227 source "arch/arm/mach-imx/mx5/Kconfig"
2229 source "arch/arm/mach-imx/mx6/Kconfig"
2231 source "arch/arm/mach-imx/mx7/Kconfig"
2233 source "arch/arm/mach-imx/mx7ulp/Kconfig"
2235 source "arch/arm/mach-imx/imx8/Kconfig"
2237 source "arch/arm/mach-imx/imx8m/Kconfig"
2239 source "arch/arm/mach-imx/imx8ulp/Kconfig"
2241 source "arch/arm/mach-imx/imx9/Kconfig"
2243 source "arch/arm/mach-imx/imxrt/Kconfig"
2245 source "arch/arm/mach-imx/mxs/Kconfig"
2247 source "arch/arm/mach-omap2/Kconfig"
2249 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
2251 source "arch/arm/mach-orion5x/Kconfig"
2253 source "arch/arm/mach-owl/Kconfig"
2255 source "arch/arm/mach-rmobile/Kconfig"
2257 source "arch/arm/mach-meson/Kconfig"
2259 source "arch/arm/mach-mediatek/Kconfig"
2261 source "arch/arm/mach-qemu/Kconfig"
2263 source "arch/arm/mach-rockchip/Kconfig"
2265 source "arch/arm/mach-s5pc1xx/Kconfig"
2267 source "arch/arm/mach-snapdragon/Kconfig"
2269 source "arch/arm/mach-socfpga/Kconfig"
2271 source "arch/arm/mach-sti/Kconfig"
2273 source "arch/arm/mach-stm32/Kconfig"
2275 source "arch/arm/mach-stm32mp/Kconfig"
2277 source "arch/arm/mach-sunxi/Kconfig"
2279 source "arch/arm/mach-tegra/Kconfig"
2281 source "arch/arm/mach-u8500/Kconfig"
2283 source "arch/arm/mach-uniphier/Kconfig"
2285 source "arch/arm/cpu/armv7/vf610/Kconfig"
2287 source "arch/arm/mach-zynq/Kconfig"
2289 source "arch/arm/mach-zynqmp/Kconfig"
2291 source "arch/arm/mach-versal/Kconfig"
2293 source "arch/arm/mach-versal-net/Kconfig"
2295 source "arch/arm/mach-zynqmp-r5/Kconfig"
2297 source "arch/arm/cpu/armv7/Kconfig"
2299 source "arch/arm/cpu/armv8/Kconfig"
2301 source "arch/arm/mach-imx/Kconfig"
2303 source "arch/arm/mach-nexell/Kconfig"
2305 source "arch/arm/mach-npcm/Kconfig"
2307 source "board/armltd/total_compute/Kconfig"
2308 source "board/armltd/corstone1000/Kconfig"
2309 source "board/bosch/shc/Kconfig"
2310 source "board/bosch/guardian/Kconfig"
2311 source "board/Marvell/octeontx/Kconfig"
2312 source "board/Marvell/octeontx2/Kconfig"
2313 source "board/armltd/vexpress/Kconfig"
2314 source "board/armltd/vexpress64/Kconfig"
2315 source "board/cortina/presidio-asic/Kconfig"
2316 source "board/broadcom/bcmns3/Kconfig"
2317 source "board/cavium/thunderx/Kconfig"
2318 source "board/eets/pdu001/Kconfig"
2319 source "board/emulation/qemu-arm/Kconfig"
2320 source "board/freescale/ls2080aqds/Kconfig"
2321 source "board/freescale/ls2080ardb/Kconfig"
2322 source "board/freescale/ls1088a/Kconfig"
2323 source "board/freescale/ls1028a/Kconfig"
2324 source "board/freescale/ls1021aqds/Kconfig"
2325 source "board/freescale/ls1043aqds/Kconfig"
2326 source "board/freescale/ls1021atwr/Kconfig"
2327 source "board/freescale/ls1021atsn/Kconfig"
2328 source "board/freescale/ls1021aiot/Kconfig"
2329 source "board/freescale/ls1046aqds/Kconfig"
2330 source "board/freescale/ls1043ardb/Kconfig"
2331 source "board/freescale/ls1046ardb/Kconfig"
2332 source "board/freescale/ls1046afrwy/Kconfig"
2333 source "board/freescale/ls1012aqds/Kconfig"
2334 source "board/freescale/ls1012ardb/Kconfig"
2335 source "board/freescale/ls1012afrdm/Kconfig"
2336 source "board/freescale/lx2160a/Kconfig"
2337 source "board/grinn/chiliboard/Kconfig"
2338 source "board/hisilicon/hikey/Kconfig"
2339 source "board/hisilicon/hikey960/Kconfig"
2340 source "board/hisilicon/poplar/Kconfig"
2341 source "board/isee/igep003x/Kconfig"
2342 source "board/kontron/sl28/Kconfig"
2343 source "board/myir/mys_6ulx/Kconfig"
2344 source "board/siemens/common/Kconfig"
2345 source "board/seeed/npi_imx6ull/Kconfig"
2346 source "board/socionext/developerbox/Kconfig"
2347 source "board/st/stv0991/Kconfig"
2348 source "board/tcl/sl50/Kconfig"
2349 source "board/traverse/ten64/Kconfig"
2350 source "board/variscite/dart_6ul/Kconfig"
2351 source "board/vscom/baltos/Kconfig"
2352 source "board/phytium/durian/Kconfig"
2353 source "board/phytium/pomelo/Kconfig"
2354 source "board/xen/xenguest_arm64/Kconfig"
2356 source "arch/arm/Kconfig.debug"