5 select HAVE_DMA_API_DEBUG
6 select HAVE_IDE if PCI || ISA || PCMCIA
9 select SYS_SUPPORTS_APM_EMULATION
10 select GENERIC_ATOMIC64 if (CPU_V6 || !CPU_32v6K || !AEABI)
11 select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
13 select HAVE_KPROBES if !XIP_KERNEL
14 select HAVE_KRETPROBES if (HAVE_KPROBES)
15 select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
16 select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
17 select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
18 select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
19 select HAVE_GENERIC_DMA_COHERENT
20 select HAVE_KERNEL_GZIP
21 select HAVE_KERNEL_LZO
22 select HAVE_KERNEL_LZMA
24 select HAVE_PERF_EVENTS
25 select PERF_USE_VMALLOC
26 select HAVE_REGS_AND_STACK_ACCESS_API
27 select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
28 select HAVE_C_RECORDMCOUNT
29 select HAVE_GENERIC_HARDIRQS
30 select HAVE_SPARSE_IRQ
31 select GENERIC_IRQ_SHOW
32 select CPU_PM if (SUSPEND || CPU_IDLE)
34 The ARM series is a line of low-power-consumption RISC chip designs
35 licensed by ARM Ltd and targeted at embedded applications and
36 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
37 manufactured, but legacy ARM-based PC hardware remains popular in
38 Europe. There is an ARM Linux project with a web page at
39 <http://www.arm.linux.org.uk/>.
41 config ARM_HAS_SG_CHAIN
50 config SYS_SUPPORTS_APM_EMULATION
53 config HAVE_SCHED_CLOCK
59 config ARCH_USES_GETTIMEOFFSET
63 config GENERIC_CLOCKEVENTS
66 config GENERIC_CLOCKEVENTS_BROADCAST
68 depends on GENERIC_CLOCKEVENTS
77 select GENERIC_ALLOCATOR
88 The Extended Industry Standard Architecture (EISA) bus was
89 developed as an open alternative to the IBM MicroChannel bus.
91 The EISA bus provided some of the features of the IBM MicroChannel
92 bus while maintaining backward compatibility with cards made for
93 the older ISA bus. The EISA bus saw limited use between 1988 and
94 1995 when it was made obsolete by the PCI bus.
96 Say Y here if you are building a kernel for an EISA-based machine.
106 MicroChannel Architecture is found in some IBM PS/2 machines and
107 laptops. It is a bus system similar to PCI or ISA. See
108 <file:Documentation/mca.txt> (and especially the web page given
109 there) before attempting to build an MCA bus kernel.
111 config STACKTRACE_SUPPORT
115 config HAVE_LATENCYTOP_SUPPORT
120 config LOCKDEP_SUPPORT
124 config TRACE_IRQFLAGS_SUPPORT
128 config HARDIRQS_SW_RESEND
132 config GENERIC_IRQ_PROBE
136 config GENERIC_LOCKBREAK
139 depends on SMP && PREEMPT
141 config RWSEM_GENERIC_SPINLOCK
145 config RWSEM_XCHGADD_ALGORITHM
148 config ARCH_HAS_ILOG2_U32
151 config ARCH_HAS_ILOG2_U64
154 config ARCH_HAS_CPUFREQ
157 Internal node to signify that the ARCH has CPUFREQ support
158 and that the relevant menu configurations are displayed for
161 config ARCH_HAS_CPU_IDLE_WAIT
164 config GENERIC_HWEIGHT
168 config GENERIC_CALIBRATE_DELAY
172 config ARCH_MAY_HAVE_PC_FDC
178 config NEED_DMA_MAP_STATE
181 config GENERIC_ISA_DMA
192 default 0xffff0000 if MMU || CPU_HIGH_VECTOR
193 default DRAM_BASE if REMAP_VECTORS_TO_RAM
196 The base address of exception vectors.
198 config ARM_PATCH_PHYS_VIRT
199 bool "Patch physical to virtual translations at runtime" if EMBEDDED
201 depends on !XIP_KERNEL && MMU
202 depends on !ARCH_REALVIEW || !SPARSEMEM
204 Patch phys-to-virt and virt-to-phys translation functions at
205 boot and module load time according to the position of the
206 kernel in system memory.
208 This can only be used with non-XIP MMU kernels where the base
209 of physical memory is at a 16MB boundary.
211 Only disable this option if you know that you do not require
212 this feature (eg, building a kernel for a single machine) and
213 you need to shrink the kernel to the minimal size.
215 config NEED_MACH_MEMORY_H
218 Select this when mach/memory.h is required to provide special
219 definitions for this platform. The need for mach/memory.h should
220 be avoided when possible.
223 hex "Physical address of main memory" if MMU
224 depends on !ARM_PATCH_PHYS_VIRT && !NEED_MACH_MEMORY_H
225 default DRAM_BASE if !MMU
227 Please provide the physical address corresponding to the
228 location of main memory in your system.
234 source "init/Kconfig"
236 source "kernel/Kconfig.freezer"
241 bool "MMU-based Paged Memory Management Support"
244 Select if you want MMU-based virtualised addressing space
245 support by paged memory management. If unsure, say 'Y'.
248 # The "ARM system type" choice list is ordered alphabetically by option
249 # text. Please add new entries in the option alphabetic order.
252 prompt "ARM system type"
253 default ARCH_VERSATILE
255 config ARCH_INTEGRATOR
256 bool "ARM Ltd. Integrator family"
258 select ARCH_HAS_CPUFREQ
260 select HAVE_MACH_CLKDEV
263 select GENERIC_CLOCKEVENTS
264 select PLAT_VERSATILE
265 select PLAT_VERSATILE_FPGA_IRQ
266 select NEED_MACH_MEMORY_H
268 Support for ARM's Integrator platform.
271 bool "ARM Ltd. RealView family"
274 select HAVE_MACH_CLKDEV
276 select GENERIC_CLOCKEVENTS
277 select ARCH_WANT_OPTIONAL_GPIOLIB
278 select PLAT_VERSATILE
279 select PLAT_VERSATILE_CLCD
280 select ARM_TIMER_SP804
281 select GPIO_PL061 if GPIOLIB
282 select NEED_MACH_MEMORY_H
284 This enables support for ARM Ltd RealView boards.
286 config ARCH_VERSATILE
287 bool "ARM Ltd. Versatile family"
291 select HAVE_MACH_CLKDEV
293 select GENERIC_CLOCKEVENTS
294 select ARCH_WANT_OPTIONAL_GPIOLIB
295 select PLAT_VERSATILE
296 select PLAT_VERSATILE_CLCD
297 select PLAT_VERSATILE_FPGA_IRQ
298 select ARM_TIMER_SP804
300 This enables support for ARM Ltd Versatile board.
303 bool "ARM Ltd. Versatile Express family"
304 select ARCH_WANT_OPTIONAL_GPIOLIB
306 select ARM_TIMER_SP804
308 select HAVE_MACH_CLKDEV
309 select GENERIC_CLOCKEVENTS
311 select HAVE_PATA_PLATFORM
313 select PLAT_VERSATILE
314 select PLAT_VERSATILE_CLCD
316 This enables support for the ARM Ltd Versatile Express boards.
320 select ARCH_REQUIRE_GPIOLIB
324 This enables support for systems based on the Atmel AT91RM9200,
325 AT91SAM9 and AT91CAP9 processors.
328 bool "Broadcom BCMRING"
332 select ARM_TIMER_SP804
334 select GENERIC_CLOCKEVENTS
335 select ARCH_WANT_OPTIONAL_GPIOLIB
337 Support for Broadcom's BCMRing platform.
340 bool "Calxeda Highbank-based"
341 select ARCH_WANT_OPTIONAL_GPIOLIB
344 select ARM_TIMER_SP804
347 select GENERIC_CLOCKEVENTS
351 Support for the Calxeda Highbank SoC based boards.
354 bool "Cirrus Logic CLPS711x/EP721x-based"
356 select ARCH_USES_GETTIMEOFFSET
357 select NEED_MACH_MEMORY_H
359 Support for Cirrus Logic 711x/721x based boards.
362 bool "Cavium Networks CNS3XXX family"
364 select GENERIC_CLOCKEVENTS
366 select MIGHT_HAVE_PCI
367 select PCI_DOMAINS if PCI
369 Support for Cavium Networks CNS3XXX platform.
372 bool "Cortina Systems Gemini"
374 select ARCH_REQUIRE_GPIOLIB
375 select ARCH_USES_GETTIMEOFFSET
377 Support for the Cortina Systems Gemini family SoCs
380 bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
383 select GENERIC_CLOCKEVENTS
385 select GENERIC_IRQ_CHIP
389 Support for CSR SiRFSoC ARM Cortex A9 Platform
396 select ARCH_USES_GETTIMEOFFSET
397 select NEED_MACH_MEMORY_H
399 This is an evaluation board for the StrongARM processor available
400 from Digital. It has limited hardware on-board, including an
401 Ethernet interface, two PCMCIA sockets, two serial ports and a
410 select ARCH_REQUIRE_GPIOLIB
411 select ARCH_HAS_HOLES_MEMORYMODEL
412 select ARCH_USES_GETTIMEOFFSET
413 select NEED_MACH_MEMORY_H
415 This enables support for the Cirrus EP93xx series of CPUs.
417 config ARCH_FOOTBRIDGE
421 select GENERIC_CLOCKEVENTS
423 select NEED_MACH_MEMORY_H
425 Support for systems based on the DC21285 companion chip
426 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
429 bool "Freescale MXC/iMX-based"
430 select GENERIC_CLOCKEVENTS
431 select ARCH_REQUIRE_GPIOLIB
434 select GENERIC_IRQ_CHIP
435 select HAVE_SCHED_CLOCK
436 select MULTI_IRQ_HANDLER
438 Support for Freescale MXC/iMX-based family of processors
441 bool "Freescale MXS-based"
442 select GENERIC_CLOCKEVENTS
443 select ARCH_REQUIRE_GPIOLIB
447 Support for Freescale MXS-based family of processors
450 bool "Hilscher NetX based"
454 select GENERIC_CLOCKEVENTS
456 This enables support for systems based on the Hilscher NetX Soc
459 bool "Hynix HMS720x-based"
462 select ARCH_USES_GETTIMEOFFSET
464 This enables support for systems based on the Hynix HMS720x
472 select ARCH_SUPPORTS_MSI
474 select NEED_MACH_MEMORY_H
476 Support for Intel's IOP13XX (XScale) family of processors.
484 select ARCH_REQUIRE_GPIOLIB
486 Support for Intel's 80219 and IOP32X (XScale) family of
495 select ARCH_REQUIRE_GPIOLIB
497 Support for Intel's IOP33X (XScale) family of processors.
504 select ARCH_USES_GETTIMEOFFSET
505 select NEED_MACH_MEMORY_H
507 Support for Intel's IXP23xx (XScale) family of processors.
510 bool "IXP2400/2800-based"
514 select ARCH_USES_GETTIMEOFFSET
515 select NEED_MACH_MEMORY_H
517 Support for Intel's IXP2400/2800 (XScale) family of processors.
525 select GENERIC_CLOCKEVENTS
526 select HAVE_SCHED_CLOCK
527 select MIGHT_HAVE_PCI
528 select DMABOUNCE if PCI
530 Support for Intel's IXP4XX (XScale) family of processors.
536 select ARCH_REQUIRE_GPIOLIB
537 select GENERIC_CLOCKEVENTS
540 Support for the Marvell Dove SoC 88AP510
543 bool "Marvell Kirkwood"
546 select ARCH_REQUIRE_GPIOLIB
547 select GENERIC_CLOCKEVENTS
550 Support for the following Marvell Kirkwood series SoCs:
551 88F6180, 88F6192 and 88F6281.
557 select ARCH_REQUIRE_GPIOLIB
560 select USB_ARCH_HAS_OHCI
562 select GENERIC_CLOCKEVENTS
564 Support for the NXP LPC32XX family of processors
567 bool "Marvell MV78xx0"
570 select ARCH_REQUIRE_GPIOLIB
571 select GENERIC_CLOCKEVENTS
574 Support for the following Marvell MV78xx0 series SoCs:
582 select ARCH_REQUIRE_GPIOLIB
583 select GENERIC_CLOCKEVENTS
586 Support for the following Marvell Orion 5x series SoCs:
587 Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
588 Orion-2 (5281), Orion-1-90 (6183).
591 bool "Marvell PXA168/910/MMP2"
593 select ARCH_REQUIRE_GPIOLIB
595 select GENERIC_CLOCKEVENTS
596 select HAVE_SCHED_CLOCK
600 select GENERIC_ALLOCATOR
602 Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
605 bool "Micrel/Kendin KS8695"
607 select ARCH_REQUIRE_GPIOLIB
608 select ARCH_USES_GETTIMEOFFSET
609 select NEED_MACH_MEMORY_H
611 Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
612 System-on-Chip devices.
615 bool "Nuvoton W90X900 CPU"
617 select ARCH_REQUIRE_GPIOLIB
620 select GENERIC_CLOCKEVENTS
622 Support for Nuvoton (Winbond logic dept.) ARM9 processor,
623 At present, the w90x900 has been renamed nuc900, regarding
624 the ARM series product line, you can login the following
625 link address to know more.
627 <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
628 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
634 select GENERIC_CLOCKEVENTS
637 select HAVE_SCHED_CLOCK
638 select ARCH_HAS_CPUFREQ
640 This enables support for NVIDIA Tegra based systems (Tegra APX,
641 Tegra 6xx and Tegra 2 series).
643 config ARCH_PICOXCELL
644 bool "Picochip picoXcell"
645 select ARCH_REQUIRE_GPIOLIB
646 select ARM_PATCH_PHYS_VIRT
650 select GENERIC_CLOCKEVENTS
652 select HAVE_SCHED_CLOCK
657 This enables support for systems based on the Picochip picoXcell
658 family of Femtocell devices. The picoxcell support requires device tree
662 bool "Philips Nexperia PNX4008 Mobile"
665 select ARCH_USES_GETTIMEOFFSET
667 This enables support for Philips PNX4008 mobile platform.
670 bool "PXA2xx/PXA3xx-based"
673 select ARCH_HAS_CPUFREQ
676 select ARCH_REQUIRE_GPIOLIB
677 select GENERIC_CLOCKEVENTS
678 select HAVE_SCHED_CLOCK
683 select MULTI_IRQ_HANDLER
684 select ARM_CPU_SUSPEND if PM
687 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
692 select GENERIC_CLOCKEVENTS
693 select ARCH_REQUIRE_GPIOLIB
696 Support for Qualcomm MSM/QSD based systems. This runs on the
697 apps processor of the MSM/QSD and depends on a shared memory
698 interface to the modem processor which runs the baseband
699 stack and controls some vital subsystems
700 (clock and power control, etc).
703 bool "Renesas SH-Mobile / R-Mobile"
706 select HAVE_MACH_CLKDEV
707 select GENERIC_CLOCKEVENTS
710 select MULTI_IRQ_HANDLER
711 select PM_GENERIC_DOMAINS if PM
712 select NEED_MACH_MEMORY_H
714 Support for Renesas's SH-Mobile and R-Mobile ARM platforms.
721 select ARCH_MAY_HAVE_PC_FDC
722 select HAVE_PATA_PLATFORM
725 select ARCH_SPARSEMEM_ENABLE
726 select ARCH_USES_GETTIMEOFFSET
728 select NEED_MACH_MEMORY_H
730 On the Acorn Risc-PC, Linux can support the internal IDE disk and
731 CD-ROM interface, serial and parallel port, and the floppy drive.
738 select ARCH_SPARSEMEM_ENABLE
740 select ARCH_HAS_CPUFREQ
742 select GENERIC_CLOCKEVENTS
744 select HAVE_SCHED_CLOCK
746 select ARCH_REQUIRE_GPIOLIB
748 select NEED_MACH_MEMORY_H
750 Support for StrongARM 11x0 based boards.
753 bool "Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443, S3C2450"
755 select ARCH_HAS_CPUFREQ
758 select ARCH_USES_GETTIMEOFFSET
759 select HAVE_S3C2410_I2C if I2C
761 Samsung S3C2410X CPU based systems, such as the Simtec Electronics
762 BAST (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or
763 the Samsung SMDK2410 development board (and derivatives).
765 Note, the S3C2416 and the S3C2450 are so close that they even share
766 the same SoC ID code. This means that there is no separate machine
767 directory (no arch/arm/mach-s3c2450) as the S3C2416 was first.
770 bool "Samsung S3C64XX"
778 select ARCH_USES_GETTIMEOFFSET
779 select ARCH_HAS_CPUFREQ
780 select ARCH_REQUIRE_GPIOLIB
781 select SAMSUNG_CLKSRC
782 select SAMSUNG_IRQ_VIC_TIMER
783 select S3C_GPIO_TRACK
785 select USB_ARCH_HAS_OHCI
786 select SAMSUNG_GPIOLIB_4BIT
787 select HAVE_S3C2410_I2C if I2C
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
790 Samsung S3C64XX series based systems
793 bool "Samsung S5P6440 S5P6450"
799 select HAVE_S3C2410_WATCHDOG if WATCHDOG
800 select GENERIC_CLOCKEVENTS
801 select HAVE_SCHED_CLOCK
802 select HAVE_S3C2410_I2C if I2C
803 select HAVE_S3C_RTC if RTC_CLASS
805 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
809 bool "Samsung S5PC100"
814 select ARM_L1_CACHE_SHIFT_6
815 select ARCH_USES_GETTIMEOFFSET
816 select HAVE_S3C2410_I2C if I2C
817 select HAVE_S3C_RTC if RTC_CLASS
818 select HAVE_S3C2410_WATCHDOG if WATCHDOG
820 Samsung S5PC100 series based systems
823 bool "Samsung S5PV210/S5PC110"
825 select ARCH_SPARSEMEM_ENABLE
826 select ARCH_HAS_HOLES_MEMORYMODEL
831 select ARM_L1_CACHE_SHIFT_6
832 select ARCH_HAS_CPUFREQ
833 select GENERIC_CLOCKEVENTS
834 select HAVE_SCHED_CLOCK
835 select HAVE_S3C2410_I2C if I2C
836 select HAVE_S3C_RTC if RTC_CLASS
837 select HAVE_S3C2410_WATCHDOG if WATCHDOG
838 select NEED_MACH_MEMORY_H
840 Samsung S5PV210/S5PC110 series based systems
843 bool "SAMSUNG EXYNOS"
845 select ARCH_SPARSEMEM_ENABLE
846 select ARCH_HAS_HOLES_MEMORYMODEL
850 select ARCH_HAS_CPUFREQ
851 select GENERIC_CLOCKEVENTS
852 select HAVE_S3C_RTC if RTC_CLASS
853 select HAVE_S3C2410_I2C if I2C
854 select HAVE_S3C2410_WATCHDOG if WATCHDOG
855 select NEED_MACH_MEMORY_H
857 Support for SAMSUNG's EXYNOS SoCs (EXYNOS4/5)
866 select ARCH_USES_GETTIMEOFFSET
867 select NEED_MACH_MEMORY_H
869 Support for the StrongARM based Digital DNARD machine, also known
870 as "Shark" (<http://www.shark-linux.de/shark.html>).
873 bool "Telechips TCC ARM926-based systems"
878 select GENERIC_CLOCKEVENTS
880 Support for Telechips TCC ARM926-based systems.
883 bool "ST-Ericsson U300 Series"
887 select HAVE_SCHED_CLOCK
890 select ARM_PATCH_PHYS_VIRT
892 select GENERIC_CLOCKEVENTS
894 select HAVE_MACH_CLKDEV
896 select ARCH_REQUIRE_GPIOLIB
897 select NEED_MACH_MEMORY_H
899 Support for ST-Ericsson U300 series mobile platforms.
902 bool "ST-Ericsson U8500 Series"
905 select GENERIC_CLOCKEVENTS
907 select ARCH_REQUIRE_GPIOLIB
908 select ARCH_HAS_CPUFREQ
910 Support for ST-Ericsson's Ux500 architecture
913 bool "STMicroelectronics Nomadik"
918 select GENERIC_CLOCKEVENTS
919 select ARCH_REQUIRE_GPIOLIB
921 Support for the Nomadik platform by ST-Ericsson
925 select GENERIC_CLOCKEVENTS
926 select ARCH_REQUIRE_GPIOLIB
930 select GENERIC_ALLOCATOR
931 select GENERIC_IRQ_CHIP
932 select ARCH_HAS_HOLES_MEMORYMODEL
934 Support for TI's DaVinci platform.
939 select ARCH_REQUIRE_GPIOLIB
940 select ARCH_HAS_CPUFREQ
942 select GENERIC_CLOCKEVENTS
943 select HAVE_SCHED_CLOCK
944 select ARCH_HAS_HOLES_MEMORYMODEL
946 Support for TI's OMAP platform (OMAP1/2/3/4).
951 select ARCH_REQUIRE_GPIOLIB
954 select GENERIC_CLOCKEVENTS
957 Support for ST's SPEAr platform (SPEAr3xx, SPEAr6xx and SPEAr13xx).
960 bool "VIA/WonderMedia 85xx"
963 select ARCH_HAS_CPUFREQ
964 select GENERIC_CLOCKEVENTS
965 select ARCH_REQUIRE_GPIOLIB
968 Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
971 bool "Xilinx Zynq ARM Cortex A9 Platform"
973 select GENERIC_CLOCKEVENTS
980 Support for Xilinx Zynq ARM Cortex A9 Platform
984 # This is sorted alphabetically by mach-* pathname. However, plat-*
985 # Kconfigs may be included either alphabetically (according to the
986 # plat- suffix) or along side the corresponding mach-* source.
988 source "arch/arm/mach-at91/Kconfig"
990 source "arch/arm/mach-bcmring/Kconfig"
992 source "arch/arm/mach-clps711x/Kconfig"
994 source "arch/arm/mach-cns3xxx/Kconfig"
996 source "arch/arm/mach-davinci/Kconfig"
998 source "arch/arm/mach-dove/Kconfig"
1000 source "arch/arm/mach-ep93xx/Kconfig"
1002 source "arch/arm/mach-footbridge/Kconfig"
1004 source "arch/arm/mach-gemini/Kconfig"
1006 source "arch/arm/mach-h720x/Kconfig"
1008 source "arch/arm/mach-integrator/Kconfig"
1010 source "arch/arm/mach-iop32x/Kconfig"
1012 source "arch/arm/mach-iop33x/Kconfig"
1014 source "arch/arm/mach-iop13xx/Kconfig"
1016 source "arch/arm/mach-ixp4xx/Kconfig"
1018 source "arch/arm/mach-ixp2000/Kconfig"
1020 source "arch/arm/mach-ixp23xx/Kconfig"
1022 source "arch/arm/mach-kirkwood/Kconfig"
1024 source "arch/arm/mach-ks8695/Kconfig"
1026 source "arch/arm/mach-lpc32xx/Kconfig"
1028 source "arch/arm/mach-msm/Kconfig"
1030 source "arch/arm/mach-mv78xx0/Kconfig"
1032 source "arch/arm/plat-mxc/Kconfig"
1034 source "arch/arm/mach-mxs/Kconfig"
1036 source "arch/arm/mach-netx/Kconfig"
1038 source "arch/arm/mach-nomadik/Kconfig"
1039 source "arch/arm/plat-nomadik/Kconfig"
1041 source "arch/arm/plat-omap/Kconfig"
1043 source "arch/arm/mach-omap1/Kconfig"
1045 source "arch/arm/mach-omap2/Kconfig"
1047 source "arch/arm/mach-orion5x/Kconfig"
1049 source "arch/arm/mach-pxa/Kconfig"
1050 source "arch/arm/plat-pxa/Kconfig"
1052 source "arch/arm/mach-mmp/Kconfig"
1054 source "arch/arm/mach-realview/Kconfig"
1056 source "arch/arm/mach-sa1100/Kconfig"
1058 source "arch/arm/plat-samsung/Kconfig"
1059 source "arch/arm/plat-s3c24xx/Kconfig"
1060 source "arch/arm/plat-s5p/Kconfig"
1062 source "arch/arm/plat-spear/Kconfig"
1064 source "arch/arm/plat-tcc/Kconfig"
1067 source "arch/arm/mach-s3c2410/Kconfig"
1068 source "arch/arm/mach-s3c2412/Kconfig"
1069 source "arch/arm/mach-s3c2416/Kconfig"
1070 source "arch/arm/mach-s3c2440/Kconfig"
1071 source "arch/arm/mach-s3c2443/Kconfig"
1075 source "arch/arm/mach-s3c64xx/Kconfig"
1078 source "arch/arm/mach-s5p64x0/Kconfig"
1080 source "arch/arm/mach-s5pc100/Kconfig"
1082 source "arch/arm/mach-s5pv210/Kconfig"
1084 source "arch/arm/mach-exynos/Kconfig"
1086 source "arch/arm/mach-shmobile/Kconfig"
1088 source "arch/arm/mach-tegra/Kconfig"
1090 source "arch/arm/mach-u300/Kconfig"
1092 source "arch/arm/mach-ux500/Kconfig"
1094 source "arch/arm/mach-versatile/Kconfig"
1096 source "arch/arm/mach-vexpress/Kconfig"
1097 source "arch/arm/plat-versatile/Kconfig"
1099 source "arch/arm/mach-vt8500/Kconfig"
1101 source "arch/arm/mach-w90x900/Kconfig"
1103 # Definitions to make life easier
1109 select GENERIC_CLOCKEVENTS
1110 select HAVE_SCHED_CLOCK
1115 select GENERIC_IRQ_CHIP
1116 select HAVE_SCHED_CLOCK
1121 config PLAT_VERSATILE
1124 config ARM_TIMER_SP804
1128 source arch/arm/mm/Kconfig
1132 default 16 if ARCH_EP93XX
1136 bool "Enable iWMMXt support"
1137 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4
1138 default y if PXA27x || PXA3xx || PXA95x || ARCH_MMP
1140 Enable support for iWMMXt context switching at run time if
1141 running on a CPU that supports it.
1143 # bool 'Use XScale PMU as timer source' CONFIG_XSCALE_PMU_TIMER
1146 depends on CPU_XSCALE && !XSCALE_PMU_TIMER
1150 depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
1151 (!ARCH_OMAP3 || OMAP3_EMU)
1155 config MULTI_IRQ_HANDLER
1158 Allow each machine to specify it's own IRQ handler at run time.
1161 source "arch/arm/Kconfig-nommu"
1164 config ARM_ERRATA_411920
1165 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1166 depends on CPU_V6 || CPU_V6K
1168 Invalidation of the Instruction Cache operation can
1169 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1170 It does not affect the MPCore. This option enables the ARM Ltd.
1171 recommended workaround.
1173 config ARM_ERRATA_430973
1174 bool "ARM errata: Stale prediction on replaced interworking branch"
1177 This option enables the workaround for the 430973 Cortex-A8
1178 (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1179 interworking branch is replaced with another code sequence at the
1180 same virtual address, whether due to self-modifying code or virtual
1181 to physical address re-mapping, Cortex-A8 does not recover from the
1182 stale interworking branch prediction. This results in Cortex-A8
1183 executing the new code sequence in the incorrect ARM or Thumb state.
1184 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1185 and also flushes the branch target cache at every context switch.
1186 Note that setting specific bits in the ACTLR register may not be
1187 available in non-secure mode.
1189 config ARM_ERRATA_458693
1190 bool "ARM errata: Processor deadlock when a false hazard is created"
1193 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1194 erratum. For very specific sequences of memory operations, it is
1195 possible for a hazard condition intended for a cache line to instead
1196 be incorrectly associated with a different cache line. This false
1197 hazard might then cause a processor deadlock. The workaround enables
1198 the L1 caching of the NEON accesses and disables the PLD instruction
1199 in the ACTLR register. Note that setting specific bits in the ACTLR
1200 register may not be available in non-secure mode.
1202 config ARM_ERRATA_460075
1203 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1206 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1207 erratum. Any asynchronous access to the L2 cache may encounter a
1208 situation in which recent store transactions to the L2 cache are lost
1209 and overwritten with stale memory contents from external memory. The
1210 workaround disables the write-allocate mode for the L2 cache via the
1211 ACTLR register. Note that setting specific bits in the ACTLR register
1212 may not be available in non-secure mode.
1214 config ARM_ERRATA_742230
1215 bool "ARM errata: DMB operation may be faulty"
1216 depends on CPU_V7 && SMP
1218 This option enables the workaround for the 742230 Cortex-A9
1219 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1220 between two write operations may not ensure the correct visibility
1221 ordering of the two writes. This workaround sets a specific bit in
1222 the diagnostic register of the Cortex-A9 which causes the DMB
1223 instruction to behave as a DSB, ensuring the correct behaviour of
1226 config ARM_ERRATA_742231
1227 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1228 depends on CPU_V7 && SMP
1230 This option enables the workaround for the 742231 Cortex-A9
1231 (r2p0..r2p2) erratum. Under certain conditions, specific to the
1232 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1233 accessing some data located in the same cache line, may get corrupted
1234 data due to bad handling of the address hazard when the line gets
1235 replaced from one of the CPUs at the same time as another CPU is
1236 accessing it. This workaround sets specific bits in the diagnostic
1237 register of the Cortex-A9 which reduces the linefill issuing
1238 capabilities of the processor.
1240 config PL310_ERRATA_588369
1241 bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
1242 depends on CACHE_L2X0
1244 The PL310 L2 cache controller implements three types of Clean &
1245 Invalidate maintenance operations: by Physical Address
1246 (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
1247 They are architecturally defined to behave as the execution of a
1248 clean operation followed immediately by an invalidate operation,
1249 both performing to the same memory location. This functionality
1250 is not correctly implemented in PL310 as clean lines are not
1251 invalidated as a result of these operations.
1253 config ARM_ERRATA_720789
1254 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1257 This option enables the workaround for the 720789 Cortex-A9 (prior to
1258 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1259 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1260 As a consequence of this erratum, some TLB entries which should be
1261 invalidated are not, resulting in an incoherency in the system page
1262 tables. The workaround changes the TLB flushing routines to invalidate
1263 entries regardless of the ASID.
1265 config PL310_ERRATA_727915
1266 bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
1267 depends on CACHE_L2X0
1269 PL310 implements the Clean & Invalidate by Way L2 cache maintenance
1270 operation (offset 0x7FC). This operation runs in background so that
1271 PL310 can handle normal accesses while it is in progress. Under very
1272 rare circumstances, due to this erratum, write data can be lost when
1273 PL310 treats a cacheable write transaction during a Clean &
1274 Invalidate by Way operation.
1276 config ARM_ERRATA_743622
1277 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1280 This option enables the workaround for the 743622 Cortex-A9
1281 (r2p0..r2p2) erratum. Under very rare conditions, a faulty
1282 optimisation in the Cortex-A9 Store Buffer may lead to data
1283 corruption. This workaround sets a specific bit in the diagnostic
1284 register of the Cortex-A9 which disables the Store Buffer
1285 optimisation, preventing the defect from occurring. This has no
1286 visible impact on the overall performance or power consumption of the
1289 config ARM_ERRATA_751472
1290 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1293 This option enables the workaround for the 751472 Cortex-A9 (prior
1294 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1295 completion of a following broadcasted operation if the second
1296 operation is received by a CPU before the ICIALLUIS has completed,
1297 potentially leading to corrupted entries in the cache or TLB.
1299 config PL310_ERRATA_753970
1300 bool "PL310 errata: cache sync operation may be faulty"
1301 depends on CACHE_PL310
1303 This option enables the workaround for the 753970 PL310 (r3p0) erratum.
1305 Under some condition the effect of cache sync operation on
1306 the store buffer still remains when the operation completes.
1307 This means that the store buffer is always asked to drain and
1308 this prevents it from merging any further writes. The workaround
1309 is to replace the normal offset of cache sync operation (0x730)
1310 by another offset targeting an unmapped PL310 register 0x740.
1311 This has the same effect as the cache sync operation: store buffer
1312 drain and waiting for all buffers empty.
1314 config ARM_ERRATA_754322
1315 bool "ARM errata: possible faulty MMU translations following an ASID switch"
1318 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1319 r3p*) erratum. A speculative memory access may cause a page table walk
1320 which starts prior to an ASID switch but completes afterwards. This
1321 can populate the micro-TLB with a stale entry which may be hit with
1322 the new ASID. This workaround places two dsb instructions in the mm
1323 switching code so that no page table walks can cross the ASID switch.
1325 config ARM_ERRATA_754327
1326 bool "ARM errata: no automatic Store Buffer drain"
1327 depends on CPU_V7 && SMP
1329 This option enables the workaround for the 754327 Cortex-A9 (prior to
1330 r2p0) erratum. The Store Buffer does not have any automatic draining
1331 mechanism and therefore a livelock may occur if an external agent
1332 continuously polls a memory location waiting to observe an update.
1333 This workaround defines cpu_relax() as smp_mb(), preventing correctly
1334 written polling loops from denying visibility of updates to memory.
1336 config ARM_ERRATA_364296
1337 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1338 depends on CPU_V6 && !SMP
1340 This options enables the workaround for the 364296 ARM1136
1341 r0p2 erratum (possible cache data corruption with
1342 hit-under-miss enabled). It sets the undocumented bit 31 in
1343 the auxiliary control register and the FI bit in the control
1344 register, thus disabling hit-under-miss without putting the
1345 processor into full low interrupt latency mode. ARM11MPCore
1348 config ARM_ERRATA_764369
1349 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1350 depends on CPU_V7 && SMP
1352 This option enables the workaround for erratum 764369
1353 affecting Cortex-A9 MPCore with two or more processors (all
1354 current revisions). Under certain timing circumstances, a data
1355 cache line maintenance operation by MVA targeting an Inner
1356 Shareable memory region may fail to proceed up to either the
1357 Point of Coherency or to the Point of Unification of the
1358 system. This workaround adds a DSB instruction before the
1359 relevant cache maintenance functions and sets a specific bit
1360 in the diagnostic control register of the SCU.
1362 config PL310_ERRATA_769419
1363 bool "PL310 errata: no automatic Store Buffer drain"
1364 depends on CACHE_L2X0
1366 On revisions of the PL310 prior to r3p2, the Store Buffer does
1367 not automatically drain. This can cause normal, non-cacheable
1368 writes to be retained when the memory system is idle, leading
1369 to suboptimal I/O performance for drivers using coherent DMA.
1370 This option adds a write barrier to the cpu_idle loop so that,
1371 on systems with an outer cache, the store buffer is drained
1376 source "arch/arm/common/Kconfig"
1386 Find out whether you have ISA slots on your motherboard. ISA is the
1387 name of a bus system, i.e. the way the CPU talks to the other stuff
1388 inside your box. Other bus systems are PCI, EISA, MicroChannel
1389 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1390 newer boards don't support it. If you have ISA, say Y, otherwise N.
1392 # Select ISA DMA controller support
1397 # Select ISA DMA interface
1402 bool "PCI support" if MIGHT_HAVE_PCI
1404 Find out whether you have a PCI motherboard. PCI is the name of a
1405 bus system, i.e. the way the CPU talks to the other stuff inside
1406 your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1407 VESA. If you have PCI, say Y, otherwise N.
1413 config PCI_NANOENGINE
1414 bool "BSE nanoEngine PCI support"
1415 depends on SA1100_NANOENGINE
1417 Enable PCI on the BSE nanoEngine board.
1422 # Select the host bridge type
1423 config PCI_HOST_VIA82C505
1425 depends on PCI && ARCH_SHARK
1428 config PCI_HOST_ITE8152
1430 depends on PCI && MACH_ARMCORE
1434 source "drivers/pci/Kconfig"
1436 source "drivers/pcmcia/Kconfig"
1440 menu "Kernel Features"
1442 source "kernel/time/Kconfig"
1445 bool "Symmetric Multi-Processing"
1446 depends on CPU_V6K || CPU_V7
1447 depends on GENERIC_CLOCKEVENTS
1448 depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
1449 MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
1450 ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
1451 ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_HIGHBANK || SOC_IMX6Q
1453 select USE_GENERIC_SMP_HELPERS
1454 select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
1456 This enables support for systems with more than one CPU. If you have
1457 a system with only one CPU, like most personal computers, say N. If
1458 you have a system with more than one CPU, say Y.
1460 If you say N here, the kernel will run on single and multiprocessor
1461 machines, but will use only one CPU of a multiprocessor machine. If
1462 you say Y here, the kernel will run on many, but not all, single
1463 processor machines. On a single processor machine, the kernel will
1464 run faster if you say N here.
1466 See also <file:Documentation/x86/i386/IO-APIC.txt>,
1467 <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1468 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1470 If you don't know what to do here, say N.
1473 bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1474 depends on EXPERIMENTAL
1475 depends on SMP && !XIP_KERNEL
1478 SMP kernels contain instructions which fail on non-SMP processors.
1479 Enabling this option allows the kernel to modify itself to make
1480 these instructions safe. Disabling it allows about 1K of space
1483 If you don't know what to do here, say Y.
1485 config ARM_CPU_TOPOLOGY
1486 bool "Support cpu topology definition"
1487 depends on SMP && CPU_V7
1490 Support ARM cpu topology definition. The MPIDR register defines
1491 affinity between processors which is then used to describe the cpu
1492 topology of an ARM System.
1495 bool "Multi-core scheduler support"
1496 depends on ARM_CPU_TOPOLOGY
1498 Multi-core scheduler support improves the CPU scheduler's decision
1499 making when dealing with multi-core CPU chips at a cost of slightly
1500 increased overhead in some places. If unsure say N here.
1503 bool "SMT scheduler support"
1504 depends on ARM_CPU_TOPOLOGY
1506 Improves the CPU scheduler's decision making when dealing with
1507 MultiThreading at a cost of slightly increased overhead in some
1508 places. If unsure say N here.
1513 This option enables support for the ARM system coherency unit
1520 This options enables support for the ARM timer and watchdog unit
1523 prompt "Memory split"
1526 Select the desired split between kernel and user memory.
1528 If you are not absolutely sure what you are doing, leave this
1532 bool "3G/1G user/kernel split"
1534 bool "2G/2G user/kernel split"
1536 bool "1G/3G user/kernel split"
1541 default 0x40000000 if VMSPLIT_1G
1542 default 0x80000000 if VMSPLIT_2G
1546 int "Maximum number of CPUs (2-32)"
1552 bool "Support for hot-pluggable CPUs (EXPERIMENTAL)"
1553 depends on SMP && HOTPLUG && EXPERIMENTAL
1555 Say Y here to experiment with turning CPUs off and on. CPUs
1556 can be controlled through /sys/devices/system/cpu.
1559 bool "Use local timer interrupts"
1562 select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
1564 Enable support for local timers on SMP platforms, rather then the
1565 legacy IPI broadcast method. Local timers allows the system
1566 accounting to be spread across the timer interval, preventing a
1567 "thundering herd" at every timer tick.
1571 default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1572 default 350 if ARCH_U8500
1575 Maximum number of GPIOs in the system.
1577 If unsure, leave the default value.
1579 source kernel/Kconfig.preempt
1583 default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
1584 ARCH_S5PV210 || ARCH_EXYNOS4
1585 default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
1586 default AT91_TIMER_HZ if ARCH_AT91
1587 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
1590 config THUMB2_KERNEL
1591 bool "Compile the kernel in Thumb-2 mode (EXPERIMENTAL)"
1592 depends on CPU_V7 && !CPU_V6 && !CPU_V6K && EXPERIMENTAL
1594 select ARM_ASM_UNIFIED
1597 By enabling this option, the kernel will be compiled in
1598 Thumb-2 mode. A compiler/assembler that understand the unified
1599 ARM-Thumb syntax is needed.
1603 config THUMB2_AVOID_R_ARM_THM_JUMP11
1604 bool "Work around buggy Thumb-2 short branch relocations in gas"
1605 depends on THUMB2_KERNEL && MODULES
1608 Various binutils versions can resolve Thumb-2 branches to
1609 locally-defined, preemptible global symbols as short-range "b.n"
1610 branch instructions.
1612 This is a problem, because there's no guarantee the final
1613 destination of the symbol, or any candidate locations for a
1614 trampoline, are within range of the branch. For this reason, the
1615 kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1616 relocation in modules at all, and it makes little sense to add
1619 The symptom is that the kernel fails with an "unsupported
1620 relocation" error when loading some modules.
1622 Until fixed tools are available, passing
1623 -fno-optimize-sibling-calls to gcc should prevent gcc generating
1624 code which hits this problem, at the cost of a bit of extra runtime
1625 stack usage in some cases.
1627 The problem is described in more detail at:
1628 https://bugs.launchpad.net/binutils-linaro/+bug/725126
1630 Only Thumb-2 kernels are affected.
1632 Unless you are sure your tools don't have this problem, say Y.
1634 config ARM_ASM_UNIFIED
1638 bool "Use the ARM EABI to compile the kernel"
1640 This option allows for the kernel to be compiled using the latest
1641 ARM ABI (aka EABI). This is only useful if you are using a user
1642 space environment that is also compiled with EABI.
1644 Since there are major incompatibilities between the legacy ABI and
1645 EABI, especially with regard to structure member alignment, this
1646 option also changes the kernel syscall calling convention to
1647 disambiguate both ABIs and allow for backward compatibility support
1648 (selected with CONFIG_OABI_COMPAT).
1650 To use this you need GCC version 4.0.0 or later.
1653 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1654 depends on AEABI && EXPERIMENTAL && !THUMB2_KERNEL
1657 This option preserves the old syscall interface along with the
1658 new (ARM EABI) one. It also provides a compatibility layer to
1659 intercept syscalls that have structure arguments which layout
1660 in memory differs between the legacy ABI and the new ARM EABI
1661 (only for non "thumb" binaries). This option adds a tiny
1662 overhead to all syscalls and produces a slightly larger kernel.
1663 If you know you'll be using only pure EABI user space then you
1664 can say N here. If this option is not selected and you attempt
1665 to execute a legacy ABI binary then the result will be
1666 UNPREDICTABLE (in fact it can be predicted that it won't work
1667 at all). If in doubt say Y.
1669 config ARCH_HAS_HOLES_MEMORYMODEL
1672 config ARCH_SPARSEMEM_ENABLE
1675 config ARCH_SPARSEMEM_DEFAULT
1676 def_bool ARCH_SPARSEMEM_ENABLE
1678 config ARCH_SELECT_MEMORY_MODEL
1679 def_bool ARCH_SPARSEMEM_ENABLE
1681 config HAVE_ARCH_PFN_VALID
1682 def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1685 bool "High Memory Support"
1688 The address space of ARM processors is only 4 Gigabytes large
1689 and it has to accommodate user address space, kernel address
1690 space as well as some memory mapped IO. That means that, if you
1691 have a large amount of physical memory and/or IO, not all of the
1692 memory can be "permanently mapped" by the kernel. The physical
1693 memory that is not permanently mapped is called "high memory".
1695 Depending on the selected kernel/user memory split, minimum
1696 vmalloc space and actual amount of RAM, you may not need this
1697 option which should result in a slightly faster kernel.
1702 bool "Allocate 2nd-level pagetables from highmem"
1705 config HW_PERF_EVENTS
1706 bool "Enable hardware performance counter support for perf events"
1707 depends on PERF_EVENTS && CPU_HAS_PMU
1710 Enable hardware performance counter support for perf events. If
1711 disabled, perf events will use software events only.
1715 config FORCE_MAX_ZONEORDER
1716 int "Maximum zone order" if ARCH_SHMOBILE
1717 range 11 64 if ARCH_SHMOBILE
1718 default "9" if SA1111
1721 The kernel memory allocator divides physically contiguous memory
1722 blocks into "zones", where each zone is a power of two number of
1723 pages. This option selects the largest power of two that the kernel
1724 keeps in the memory allocator. If you need to allocate very large
1725 blocks of physically contiguous memory, then you may need to
1726 increase this value.
1728 This config option is actually maximum order plus one. For example,
1729 a value of 11 means that the largest free memory block is 2^10 pages.
1732 bool "Timer and CPU usage LEDs"
1733 depends on ARCH_CDB89712 || ARCH_EBSA110 || \
1734 ARCH_EBSA285 || ARCH_INTEGRATOR || \
1735 ARCH_LUBBOCK || MACH_MAINSTONE || ARCH_NETWINDER || \
1736 ARCH_OMAP || ARCH_P720T || ARCH_PXA_IDP || \
1737 ARCH_SA1100 || ARCH_SHARK || ARCH_VERSATILE || \
1738 ARCH_AT91 || ARCH_DAVINCI || \
1739 ARCH_KS8695 || MACH_RD88F5182 || ARCH_REALVIEW
1741 If you say Y here, the LEDs on your machine will be used
1742 to provide useful information about your current system status.
1744 If you are compiling a kernel for a NetWinder or EBSA-285, you will
1745 be able to select which LEDs are active using the options below. If
1746 you are compiling a kernel for the EBSA-110 or the LART however, the
1747 red LED will simply flash regularly to indicate that the system is
1748 still functional. It is safe to say Y here if you have a CATS
1749 system, but the driver will do nothing.
1752 bool "Timer LED" if (!ARCH_CDB89712 && !ARCH_OMAP) || \
1753 OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1754 || MACH_OMAP_PERSEUS2
1756 depends on !GENERIC_CLOCKEVENTS
1757 default y if ARCH_EBSA110
1759 If you say Y here, one of the system LEDs (the green one on the
1760 NetWinder, the amber one on the EBSA285, or the red one on the LART)
1761 will flash regularly to indicate that the system is still
1762 operational. This is mainly useful to kernel hackers who are
1763 debugging unstable kernels.
1765 The LART uses the same LED for both Timer LED and CPU usage LED
1766 functions. You may choose to use both, but the Timer LED function
1767 will overrule the CPU usage LED.
1770 bool "CPU usage LED" if (!ARCH_CDB89712 && !ARCH_EBSA110 && \
1772 || OMAP_OSK_MISTRAL || MACH_OMAP_H2 \
1773 || MACH_OMAP_PERSEUS2
1776 If you say Y here, the red LED will be used to give a good real
1777 time indication of CPU usage, by lighting whenever the idle task
1778 is not currently executing.
1780 The LART uses the same LED for both Timer LED and CPU usage LED
1781 functions. You may choose to use both, but the Timer LED function
1782 will overrule the CPU usage LED.
1784 config ALIGNMENT_TRAP
1786 depends on CPU_CP15_MMU
1787 default y if !ARCH_EBSA110
1788 select HAVE_PROC_CPU if PROC_FS
1790 ARM processors cannot fetch/store information which is not
1791 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1792 address divisible by 4. On 32-bit ARM processors, these non-aligned
1793 fetch/store instructions will be emulated in software if you say
1794 here, which has a severe performance impact. This is necessary for
1795 correct operation of some network protocols. With an IP-only
1796 configuration it is safe to say N, otherwise say Y.
1798 config UACCESS_WITH_MEMCPY
1799 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user() (EXPERIMENTAL)"
1800 depends on MMU && EXPERIMENTAL
1801 default y if CPU_FEROCEON
1803 Implement faster copy_to_user and clear_user methods for CPU
1804 cores where a 8-word STM instruction give significantly higher
1805 memory write throughput than a sequence of individual 32bit stores.
1807 A possible side effect is a slight increase in scheduling latency
1808 between threads sharing the same address space if they invoke
1809 such copy operations with large buffers.
1811 However, if the CPU data cache is using a write-allocate mode,
1812 this option is unlikely to provide any performance gain.
1816 prompt "Enable seccomp to safely compute untrusted bytecode"
1818 This kernel feature is useful for number crunching applications
1819 that may need to compute untrusted bytecode during their
1820 execution. By using pipes or other transports made available to
1821 the process as file descriptors supporting the read/write
1822 syscalls, it's possible to isolate those applications in
1823 their own address space using seccomp. Once seccomp is
1824 enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1825 and the task is only allowed to execute a few safe syscalls
1826 defined by each seccomp mode.
1828 config CC_STACKPROTECTOR
1829 bool "Enable -fstack-protector buffer overflow detection (EXPERIMENTAL)"
1830 depends on EXPERIMENTAL
1832 This option turns on the -fstack-protector GCC feature. This
1833 feature puts, at the beginning of functions, a canary value on
1834 the stack just before the return address, and validates
1835 the value just before actually returning. Stack based buffer
1836 overflows (that need to overwrite this return address) now also
1837 overwrite the canary, which gets detected and the attack is then
1838 neutralized via a kernel panic.
1839 This feature requires gcc version 4.2 or above.
1841 config DEPRECATED_PARAM_STRUCT
1842 bool "Provide old way to pass kernel parameters"
1844 This was deprecated in 2001 and announced to live on for 5 years.
1845 Some old boot loaders still use this way.
1852 bool "Flattened Device Tree support"
1854 select OF_EARLY_FLATTREE
1857 Include support for flattened device tree machine descriptions.
1859 # Compressed boot loader in ROM. Yes, we really want to ask about
1860 # TEXT and BSS so we preserve their values in the config files.
1861 config ZBOOT_ROM_TEXT
1862 hex "Compressed ROM boot loader base address"
1865 The physical address at which the ROM-able zImage is to be
1866 placed in the target. Platforms which normally make use of
1867 ROM-able zImage formats normally set this to a suitable
1868 value in their defconfig file.
1870 If ZBOOT_ROM is not enabled, this has no effect.
1872 config ZBOOT_ROM_BSS
1873 hex "Compressed ROM boot loader BSS address"
1876 The base address of an area of read/write memory in the target
1877 for the ROM-able zImage which must be available while the
1878 decompressor is running. It must be large enough to hold the
1879 entire decompressed kernel plus an additional 128 KiB.
1880 Platforms which normally make use of ROM-able zImage formats
1881 normally set this to a suitable value in their defconfig file.
1883 If ZBOOT_ROM is not enabled, this has no effect.
1886 bool "Compressed boot loader in ROM/flash"
1887 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1889 Say Y here if you intend to execute your compressed kernel image
1890 (zImage) directly from ROM or flash. If unsure, say N.
1893 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1894 depends on ZBOOT_ROM && ARCH_SH7372 && EXPERIMENTAL
1895 default ZBOOT_ROM_NONE
1897 Include experimental SD/MMC loading code in the ROM-able zImage.
1898 With this enabled it is possible to write the the ROM-able zImage
1899 kernel image to an MMC or SD card and boot the kernel straight
1900 from the reset vector. At reset the processor Mask ROM will load
1901 the first part of the the ROM-able zImage which in turn loads the
1902 rest the kernel image to RAM.
1904 config ZBOOT_ROM_NONE
1905 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1907 Do not load image from SD or MMC
1909 config ZBOOT_ROM_MMCIF
1910 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1912 Load image from MMCIF hardware block.
1914 config ZBOOT_ROM_SH_MOBILE_SDHI
1915 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1917 Load image from SDHI hardware block
1921 config ARM_APPENDED_DTB
1922 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1923 depends on OF && !ZBOOT_ROM && EXPERIMENTAL
1925 With this option, the boot code will look for a device tree binary
1926 (DTB) appended to zImage
1927 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1929 This is meant as a backward compatibility convenience for those
1930 systems with a bootloader that can't be upgraded to accommodate
1931 the documented boot protocol using a device tree.
1933 Beware that there is very little in terms of protection against
1934 this option being confused by leftover garbage in memory that might
1935 look like a DTB header after a reboot if no actual DTB is appended
1936 to zImage. Do not leave this option active in a production kernel
1937 if you don't intend to always append a DTB. Proper passing of the
1938 location into r2 of a bootloader provided DTB is always preferable
1941 config ARM_ATAG_DTB_COMPAT
1942 bool "Supplement the appended DTB with traditional ATAG information"
1943 depends on ARM_APPENDED_DTB
1945 Some old bootloaders can't be updated to a DTB capable one, yet
1946 they provide ATAGs with memory configuration, the ramdisk address,
1947 the kernel cmdline string, etc. Such information is dynamically
1948 provided by the bootloader and can't always be stored in a static
1949 DTB. To allow a device tree enabled kernel to be used with such
1950 bootloaders, this option allows zImage to extract the information
1951 from the ATAG list and store it at run time into the appended DTB.
1954 string "Default kernel command string"
1957 On some architectures (EBSA110 and CATS), there is currently no way
1958 for the boot loader to pass arguments to the kernel. For these
1959 architectures, you should supply some command-line options at build
1960 time by entering them here. As a minimum, you should specify the
1961 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1964 prompt "Kernel command line type" if CMDLINE != ""
1965 default CMDLINE_FROM_BOOTLOADER
1967 config CMDLINE_FROM_BOOTLOADER
1968 bool "Use bootloader kernel arguments if available"
1970 Uses the command-line options passed by the boot loader. If
1971 the boot loader doesn't provide any, the default kernel command
1972 string provided in CMDLINE will be used.
1974 config CMDLINE_EXTEND
1975 bool "Extend bootloader kernel arguments"
1977 The command-line arguments provided by the boot loader will be
1978 appended to the default kernel command string.
1980 config CMDLINE_FORCE
1981 bool "Always use the default kernel command string"
1983 Always use the default kernel command string, even if the boot
1984 loader passes other arguments to the kernel.
1985 This is useful if you cannot or don't want to change the
1986 command-line options your boot loader passes to the kernel.
1990 bool "Kernel Execute-In-Place from ROM"
1991 depends on !ZBOOT_ROM
1993 Execute-In-Place allows the kernel to run from non-volatile storage
1994 directly addressable by the CPU, such as NOR flash. This saves RAM
1995 space since the text section of the kernel is not loaded from flash
1996 to RAM. Read-write sections, such as the data section and stack,
1997 are still copied to RAM. The XIP kernel is not compressed since
1998 it has to run directly from flash, so it will take more space to
1999 store it. The flash address used to link the kernel object files,
2000 and for storing it, is configuration dependent. Therefore, if you
2001 say Y here, you must know the proper physical address where to
2002 store the kernel image depending on your own flash memory usage.
2004 Also note that the make target becomes "make xipImage" rather than
2005 "make zImage" or "make Image". The final kernel binary to put in
2006 ROM memory will be arch/arm/boot/xipImage.
2010 config XIP_PHYS_ADDR
2011 hex "XIP Kernel Physical Location"
2012 depends on XIP_KERNEL
2013 default "0x00080000"
2015 This is the physical address in your flash memory the kernel will
2016 be linked for and stored to. This address is dependent on your
2020 bool "Kexec system call (EXPERIMENTAL)"
2021 depends on EXPERIMENTAL
2023 kexec is a system call that implements the ability to shutdown your
2024 current kernel, and to start another kernel. It is like a reboot
2025 but it is independent of the system firmware. And like a reboot
2026 you can start any kernel with it, not just Linux.
2028 It is an ongoing process to be certain the hardware in a machine
2029 is properly shutdown, so do not be surprised if this code does not
2030 initially work for you. It may help to enable device hotplugging
2034 bool "Export atags in procfs"
2038 Should the atags used to boot the kernel be exported in an "atags"
2039 file in procfs. Useful with kexec.
2042 bool "Build kdump crash kernel (EXPERIMENTAL)"
2043 depends on EXPERIMENTAL
2045 Generate crash dump after being started by kexec. This should
2046 be normally only set in special crash dump kernels which are
2047 loaded in the main kernel with kexec-tools into a specially
2048 reserved region and then later executed after a crash by
2049 kdump/kexec. The crash dump kernel must be compiled to a
2050 memory address not used by the main kernel
2052 For more details see Documentation/kdump/kdump.txt
2054 config AUTO_ZRELADDR
2055 bool "Auto calculation of the decompressed kernel image address"
2056 depends on !ZBOOT_ROM && !ARCH_U300
2058 ZRELADDR is the physical address where the decompressed kernel
2059 image will be placed. If AUTO_ZRELADDR is selected, the address
2060 will be determined at run-time by masking the current IP with
2061 0xf8000000. This assumes the zImage being placed in the first 128MB
2062 from start of memory.
2066 menu "CPU Power Management"
2070 source "drivers/cpufreq/Kconfig"
2073 tristate "CPUfreq driver for i.MX CPUs"
2074 depends on ARCH_MXC && CPU_FREQ
2076 This enables the CPUfreq driver for i.MX CPUs.
2078 config CPU_FREQ_SA1100
2081 config CPU_FREQ_SA1110
2084 config CPU_FREQ_INTEGRATOR
2085 tristate "CPUfreq driver for ARM Integrator CPUs"
2086 depends on ARCH_INTEGRATOR && CPU_FREQ
2089 This enables the CPUfreq driver for ARM Integrator CPUs.
2091 For details, take a look at <file:Documentation/cpu-freq>.
2097 depends on CPU_FREQ && ARCH_PXA && PXA25x
2099 select CPU_FREQ_TABLE
2100 select CPU_FREQ_DEFAULT_GOV_USERSPACE
2105 Internal configuration node for common cpufreq on Samsung SoC
2107 config CPU_FREQ_S3C24XX
2108 bool "CPUfreq driver for Samsung S3C24XX series CPUs (EXPERIMENTAL)"
2109 depends on ARCH_S3C2410 && CPU_FREQ && EXPERIMENTAL
2112 This enables the CPUfreq driver for the Samsung S3C24XX family
2115 For details, take a look at <file:Documentation/cpu-freq>.
2119 config CPU_FREQ_S3C24XX_PLL
2120 bool "Support CPUfreq changing of PLL frequency (EXPERIMENTAL)"
2121 depends on CPU_FREQ_S3C24XX && EXPERIMENTAL
2123 Compile in support for changing the PLL frequency from the
2124 S3C24XX series CPUfreq driver. The PLL takes time to settle
2125 after a frequency change, so by default it is not enabled.
2127 This also means that the PLL tables for the selected CPU(s) will
2128 be built which may increase the size of the kernel image.
2130 config CPU_FREQ_S3C24XX_DEBUG
2131 bool "Debug CPUfreq Samsung driver core"
2132 depends on CPU_FREQ_S3C24XX
2134 Enable s3c_freq_dbg for the Samsung S3C CPUfreq core
2136 config CPU_FREQ_S3C24XX_IODEBUG
2137 bool "Debug CPUfreq Samsung driver IO timing"
2138 depends on CPU_FREQ_S3C24XX
2140 Enable s3c_freq_iodbg for the Samsung S3C CPUfreq core
2142 config CPU_FREQ_S3C24XX_DEBUGFS
2143 bool "Export debugfs for CPUFreq"
2144 depends on CPU_FREQ_S3C24XX && DEBUG_FS
2146 Export status information via debugfs.
2150 source "drivers/cpuidle/Kconfig"
2154 menu "Floating point emulation"
2156 comment "At least one emulation must be selected"
2159 bool "NWFPE math emulation"
2160 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2162 Say Y to include the NWFPE floating point emulator in the kernel.
2163 This is necessary to run most binaries. Linux does not currently
2164 support floating point hardware so you need to say Y here even if
2165 your machine has an FPA or floating point co-processor podule.
2167 You may say N here if you are going to load the Acorn FPEmulator
2168 early in the bootup.
2171 bool "Support extended precision"
2172 depends on FPE_NWFPE
2174 Say Y to include 80-bit support in the kernel floating-point
2175 emulator. Otherwise, only 32 and 64-bit support is compiled in.
2176 Note that gcc does not generate 80-bit operations by default,
2177 so in most cases this option only enlarges the size of the
2178 floating point emulator without any good reason.
2180 You almost surely want to say N here.
2183 bool "FastFPE math emulation (EXPERIMENTAL)"
2184 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3 && EXPERIMENTAL
2186 Say Y here to include the FAST floating point emulator in the kernel.
2187 This is an experimental much faster emulator which now also has full
2188 precision for the mantissa. It does not support any exceptions.
2189 It is very simple, and approximately 3-6 times faster than NWFPE.
2191 It should be sufficient for most programs. It may be not suitable
2192 for scientific calculations, but you have to check this for yourself.
2193 If you do not feel you need a faster FP emulation you should better
2197 bool "VFP-format floating point maths"
2198 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2200 Say Y to include VFP support code in the kernel. This is needed
2201 if your hardware includes a VFP unit.
2203 Please see <file:Documentation/arm/VFP/release-notes.txt> for
2204 release notes and additional status information.
2206 Say N if your target does not have VFP hardware.
2214 bool "Advanced SIMD (NEON) Extension support"
2215 depends on VFPv3 && CPU_V7
2217 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2222 menu "Userspace binary formats"
2224 source "fs/Kconfig.binfmt"
2227 tristate "RISC OS personality"
2230 Say Y here to include the kernel code necessary if you want to run
2231 Acorn RISC OS/Arthur binaries under Linux. This code is still very
2232 experimental; if this sounds frightening, say N and sleep in peace.
2233 You can also say M here to compile this support as a module (which
2234 will be called arthur).
2238 menu "Power management options"
2240 source "kernel/power/Kconfig"
2242 config ARCH_SUSPEND_POSSIBLE
2243 depends on !ARCH_S5PC100
2244 depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
2245 CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
2248 config ARM_CPU_SUSPEND
2253 source "net/Kconfig"
2255 source "drivers/Kconfig"
2259 source "arch/arm/Kconfig.debug"
2261 source "security/Kconfig"
2263 source "crypto/Kconfig"
2265 source "lib/Kconfig"