1 menu "ARM architecture"
10 select SYS_CACHE_SHIFT_6
13 config POSITION_INDEPENDENT
14 bool "Generate position-independent pre-relocation code"
16 U-Boot expects to be linked to a specific hard-coded address, and to
17 be loaded to and run from that address. This option lifts that
18 restriction, thus allowing the code to be loaded to and executed from
19 almost any 4K aligned address. This logic relies on the relocation
20 information that is embedded in the binary to support U-Boot
21 relocating itself to the top-of-RAM later during execution.
23 config INIT_SP_RELATIVE
24 bool "Specify the early stack pointer relative to the .bss section"
25 default n if ARCH_QEMU
26 default y if POSITION_INDEPENDENT
28 U-Boot typically uses a hard-coded value for the stack pointer
29 before relocation. Enable this option to instead calculate the
30 initial SP at run-time. This is useful to avoid hard-coding addresses
31 into U-Boot, so that it can be loaded and executed at arbitrary
32 addresses and thus avoid using arbitrary addresses at runtime.
34 If this option is enabled, the early stack pointer is set to
35 &_bss_start with a offset value added. The offset is specified by
36 SYS_INIT_SP_BSS_OFFSET.
38 config SYS_INIT_SP_BSS_OFFSET
39 int "Early stack offset from the .bss base address"
40 depends on INIT_SP_RELATIVE
43 This option's value is the offset added to &_bss_start in order to
44 calculate the stack pointer. This offset should be large enough so
45 that the early malloc region, global data (gd), and early stack usage
46 do not overlap any appended DTB.
48 config LINUX_KERNEL_IMAGE_HEADER
51 Place a Linux kernel image header at the start of the U-Boot binary.
52 The format of the header is described in the Linux kernel source at
53 Documentation/arm64/booting.txt. This feature is useful since the
54 image header reports the amount of memory (BSS and similar) that
55 U-Boot needs to use, but which isn't part of the binary.
57 if LINUX_KERNEL_IMAGE_HEADER
58 config LNX_KRNL_IMG_TEXT_OFFSET_BASE
61 The value subtracted from CONFIG_SYS_TEXT_BASE to calculate the
62 TEXT_OFFSET value written to the Linux kernel image header.
71 ARM GICV3 Interrupt translation service (ITS).
72 Basic support for programming locality specific peripheral
73 interrupts (LPI) configuration tables and enable LPI tables.
74 LPI configuration table can be used by u-boot or Linux.
75 ARM GICV3 has limitation, once the LPI table is enabled, LPI
76 configuration table can not be re-programmed, unless GICV3 reset.
82 config DMA_ADDR_T_64BIT
92 # Used for compatibility with asm files copied from the kernel
93 config ARM_ASM_UNIFIED
97 # Used for compatibility with asm files copied from the kernel
101 config SYS_ICACHE_OFF
102 bool "Do not enable icache"
105 Do not enable instruction cache in U-Boot.
107 config SPL_SYS_ICACHE_OFF
108 bool "Do not enable icache in SPL"
110 default SYS_ICACHE_OFF
112 Do not enable instruction cache in SPL.
114 config SYS_DCACHE_OFF
115 bool "Do not enable dcache"
118 Do not enable data cache in U-Boot.
120 config SPL_SYS_DCACHE_OFF
121 bool "Do not enable dcache in SPL"
123 default SYS_DCACHE_OFF
125 Do not enable data cache in SPL.
127 config SYS_ARM_CACHE_CP15
128 bool "CP15 based cache enabling support"
130 Select this if your processor suports enabling caches by using
134 bool "MMU-based Paged Memory Management Support"
135 select SYS_ARM_CACHE_CP15
137 Select if you want MMU-based virtualised addressing space
138 support via paged memory management.
141 bool 'Use the ARM v7 PMSA Compliant MPU'
143 Some ARM systems without an MMU have instead a Memory Protection
144 Unit (MPU) that defines the type and permissions for regions of
146 If your CPU has an MPU then you should choose 'y' here unless you
147 know that you do not want to use the MPU.
149 # If set, the workarounds for these ARM errata are applied early during U-Boot
150 # startup. Note that in general these options force the workarounds to be
151 # applied; no CPU-type/version detection exists, unlike the similar options in
152 # the Linux kernel. Do not set these options unless they apply! Also note that
153 # the following can be machine-specific errata. These do have ability to
154 # provide rudimentary version and machine-specific checks, but expect no
156 # CONFIG_ARM_ERRATA_430973
157 # CONFIG_ARM_ERRATA_454179
158 # CONFIG_ARM_ERRATA_621766
159 # CONFIG_ARM_ERRATA_798870
160 # CONFIG_ARM_ERRATA_801819
161 # CONFIG_ARM_CORTEX_A8_CVE_2017_5715
162 # CONFIG_ARM_CORTEX_A15_CVE_2017_5715
164 config ARM_ERRATA_430973
167 config ARM_ERRATA_454179
170 config ARM_ERRATA_621766
173 config ARM_ERRATA_716044
176 config ARM_ERRATA_725233
179 config ARM_ERRATA_742230
182 config ARM_ERRATA_743622
185 config ARM_ERRATA_751472
188 config ARM_ERRATA_761320
191 config ARM_ERRATA_773022
194 config ARM_ERRATA_774769
197 config ARM_ERRATA_794072
200 config ARM_ERRATA_798870
203 config ARM_ERRATA_801819
206 config ARM_ERRATA_826974
209 config ARM_ERRATA_828024
212 config ARM_ERRATA_829520
215 config ARM_ERRATA_833069
218 config ARM_ERRATA_833471
221 config ARM_ERRATA_845369
224 config ARM_ERRATA_852421
227 config ARM_ERRATA_852423
230 config ARM_ERRATA_855873
233 config ARM_CORTEX_A8_CVE_2017_5715
236 config ARM_CORTEX_A15_CVE_2017_5715
241 select SYS_CACHE_SHIFT_5
246 select SYS_CACHE_SHIFT_5
251 select SYS_CACHE_SHIFT_5
256 select SYS_CACHE_SHIFT_5
261 select SYS_CACHE_SHIFT_5
267 select SYS_CACHE_SHIFT_5
274 select SYS_CACHE_SHIFT_6
281 select SYS_CACHE_SHIFT_5
282 select SYS_THUMB_BUILD
288 select SYS_ARM_CACHE_CP15
290 select SYS_CACHE_SHIFT_6
294 select SYS_CACHE_SHIFT_5
299 select SYS_CACHE_SHIFT_5
303 default "arm720t" if CPU_ARM720T
304 default "arm920t" if CPU_ARM920T
305 default "arm926ejs" if CPU_ARM926EJS
306 default "arm946es" if CPU_ARM946ES
307 default "arm1136" if CPU_ARM1136
308 default "arm1176" if CPU_ARM1176
309 default "armv7" if CPU_V7A
310 default "armv7" if CPU_V7R
311 default "armv7m" if CPU_V7M
312 default "pxa" if CPU_PXA
313 default "sa1100" if CPU_SA1100
314 default "armv8" if ARM64
318 default 4 if CPU_ARM720T
319 default 4 if CPU_ARM920T
320 default 5 if CPU_ARM926EJS
321 default 5 if CPU_ARM946ES
322 default 6 if CPU_ARM1136
323 default 6 if CPU_ARM1176
328 default 4 if CPU_SA1100
331 config SYS_CACHE_SHIFT_5
334 config SYS_CACHE_SHIFT_6
337 config SYS_CACHE_SHIFT_7
340 config SYS_CACHELINE_SIZE
342 default 128 if SYS_CACHE_SHIFT_7
343 default 64 if SYS_CACHE_SHIFT_6
344 default 32 if SYS_CACHE_SHIFT_5
347 prompt "Select the ARM data write cache policy"
348 default SYS_ARM_CACHE_WRITETHROUGH if TARGET_BCMCYGNUS || \
350 default SYS_ARM_CACHE_WRITEBACK
352 config SYS_ARM_CACHE_WRITEBACK
353 bool "Write-back (WB)"
355 A write updates the cache only and marks the cache line as dirty.
356 External memory is updated only when the line is evicted or explicitly
359 config SYS_ARM_CACHE_WRITETHROUGH
360 bool "Write-through (WT)"
362 A write updates both the cache and the external memory system.
363 This does not mark the cache line as dirty.
365 config SYS_ARM_CACHE_WRITEALLOC
366 bool "Write allocation (WA)"
368 A cache line is allocated on a write miss. This means that executing a
369 store instruction on the processor might cause a burst read to occur.
370 There is a linefill to obtain the data for the cache line, before the
375 bool "Enable ARCH_CPU_INIT"
377 Some architectures require a call to arch_cpu_init().
378 Say Y here to enable it
380 config SYS_ARCH_TIMER
381 bool "ARM Generic Timer support"
382 depends on CPU_V7A || ARM64
385 The ARM Generic Timer (aka arch-timer) provides an architected
386 interface to a timer source on an SoC.
387 It is mandatory for ARMv8 implementation and widely available
391 bool "Support for ARM SMC Calling Convention (SMCCC)"
392 depends on CPU_V7A || ARM64
395 Say Y here if you want to enable ARM SMC Calling Convention.
396 This should be enabled if U-Boot needs to communicate with system
397 firmware (for example, PSCI) according to SMCCC.
400 bool "support boot from semihosting"
402 In emulated environments, semihosting is a way for
403 the hosted environment to call out to the emulator to
404 retrieve files from the host machine.
406 config SYS_THUMB_BUILD
407 bool "Build U-Boot using the Thumb instruction set"
410 Use this flag to build U-Boot using the Thumb instruction set for
411 ARM architectures. Thumb instruction set provides better code
412 density. For ARM architectures that support Thumb2 this flag will
413 result in Thumb2 code generated by GCC.
415 config SPL_SYS_THUMB_BUILD
416 bool "Build SPL using the Thumb instruction set"
417 default y if SYS_THUMB_BUILD
418 depends on !ARM64 && SPL
420 Use this flag to build SPL using the Thumb instruction set for
421 ARM architectures. Thumb instruction set provides better code
422 density. For ARM architectures that support Thumb2 this flag will
423 result in Thumb2 code generated by GCC.
425 config TPL_SYS_THUMB_BUILD
426 bool "Build TPL using the Thumb instruction set"
427 default y if SYS_THUMB_BUILD
428 depends on TPL && !ARM64
430 Use this flag to build TPL using the Thumb instruction set for
431 ARM architectures. Thumb instruction set provides better code
432 density. For ARM architectures that support Thumb2 this flag will
433 result in Thumb2 code generated by GCC.
436 config SYS_L2CACHE_OFF
439 If SoC does not support L2CACHE or one does not want to enable
440 L2CACHE, choose this option.
442 config ENABLE_ARM_SOC_BOOT0_HOOK
443 bool "prepare BOOT0 header"
445 If the SoC's BOOT0 requires a header area filled with (magic)
446 values, then choose this option, and create a file included as
447 <asm/arch/boot0.h> which contains the required assembler code.
449 config ARM_CORTEX_CPU_IS_UP
453 config USE_ARCH_MEMCPY
454 bool "Use an assembly optimized implementation of memcpy"
458 Enable the generation of an optimized version of memcpy.
459 Such an implementation may be faster under some conditions
460 but may increase the binary size.
462 config SPL_USE_ARCH_MEMCPY
463 bool "Use an assembly optimized implementation of memcpy for SPL"
464 default y if USE_ARCH_MEMCPY
465 depends on !ARM64 && SPL
467 Enable the generation of an optimized version of memcpy.
468 Such an implementation may be faster under some conditions
469 but may increase the binary size.
471 config TPL_USE_ARCH_MEMCPY
472 bool "Use an assembly optimized implementation of memcpy for TPL"
473 default y if USE_ARCH_MEMCPY
474 depends on !ARM64 && TPL
476 Enable the generation of an optimized version of memcpy.
477 Such an implementation may be faster under some conditions
478 but may increase the binary size.
480 config USE_ARCH_MEMSET
481 bool "Use an assembly optimized implementation of memset"
485 Enable the generation of an optimized version of memset.
486 Such an implementation may be faster under some conditions
487 but may increase the binary size.
489 config SPL_USE_ARCH_MEMSET
490 bool "Use an assembly optimized implementation of memset for SPL"
491 default y if USE_ARCH_MEMSET
492 depends on !ARM64 && SPL
494 Enable the generation of an optimized version of memset.
495 Such an implementation may be faster under some conditions
496 but may increase the binary size.
498 config TPL_USE_ARCH_MEMSET
499 bool "Use an assembly optimized implementation of memset for TPL"
500 default y if USE_ARCH_MEMSET
501 depends on !ARM64 && TPL
503 Enable the generation of an optimized version of memset.
504 Such an implementation may be faster under some conditions
505 but may increase the binary size.
507 config ARM64_SUPPORT_AARCH32
508 bool "ARM64 system support AArch32 execution state"
510 default y if !TARGET_THUNDERX_88XX
512 This ARM64 system supports AArch32 execution state.
515 prompt "Target select"
520 select SPL_BOARD_INIT if SPL && !TARGET_SMARTWEB
521 select SPL_SEPARATE_BSS if SPL
523 config TARGET_EDB93XX
524 bool "Support edb93xx"
528 config TARGET_ASPENITE
529 bool "Support aspenite"
533 bool "Support gplugd"
539 select SPL_DM_SPI if SPL
542 Support for TI's DaVinci platform.
545 bool "Marvell Kirkwood"
546 select ARCH_MISC_INIT
547 select BOARD_EARLY_INIT_F
551 bool "Marvell MVEBU family (Armada XP/375/38x/3700/7K/8K)"
557 select SPL_DM_SPI if SPL
558 select SPL_DM_SPI_FLASH if SPL
568 config TARGET_SPEAR300
569 bool "Support spear300"
570 select BOARD_EARLY_INIT_F
575 config TARGET_SPEAR310
576 bool "Support spear310"
577 select BOARD_EARLY_INIT_F
582 config TARGET_SPEAR320
583 bool "Support spear320"
584 select BOARD_EARLY_INIT_F
589 config TARGET_SPEAR600
590 bool "Support spear600"
591 select BOARD_EARLY_INIT_F
596 config TARGET_STV0991
597 bool "Support stv0991"
610 select BOARD_LATE_INIT
620 bool "Broadcom BCM283X family"
626 select SERIAL_SEARCH_ALL
631 bool "Broadcom BCM63158 family"
637 bool "Broadcom BCM68360 family"
643 bool "Broadcom BCM6858 family"
649 bool "Broadcom BCM7XXX family"
653 select OF_PRIOR_STAGE
656 This enables support for Broadcom ARM-based set-top box
657 chipsets, including the 7445 family of chips.
659 config TARGET_BCMCYGNUS
660 bool "Support bcmcygnus"
663 imply BCM_SF2_ETH_GMAC
671 bool "Support Broadcom Northstar2"
674 Support for Broadcom Northstar 2 SoCs. NS2 is a quad-core 64-bit
675 ARMv8 Cortex-A57 processors targeting a broad range of networking
679 bool "Support Broadcom NS3"
681 select BOARD_LATE_INIT
683 Support for Broadcom Northstar 3 SoCs. NS3 is a octo-core 64-bit
684 ARMv8 Cortex-A72 processors targeting a broad range of networking
688 bool "Samsung EXYNOS"
697 imply SYS_THUMB_BUILD
702 bool "Samsung S5PC1XX"
711 bool "Calxeda Highbank"
715 config ARCH_INTEGRATOR
716 bool "ARM Ltd. Integrator family"
723 bool "Qualcomm IPQ40xx SoCs"
741 select SYS_ARCH_TIMER
742 select SYS_THUMB_BUILD
748 bool "Texas Instruments' K3 Architecture"
753 config ARCH_OMAP2PLUS
756 select SPL_BOARD_INIT if SPL
757 select SPL_STACK_R if SPL
759 imply TI_SYSC if DM && OF_CONTROL
764 imply DISTRO_DEFAULTS
767 Support for the Meson SoC family developed by Amlogic Inc.,
768 targeted at media players and tablet computers. We currently
769 support the S905 (GXBaby) 64-bit SoC.
776 select SPL_LIBCOMMON_SUPPORT if SPL
777 select SPL_LIBGENERIC_SUPPORT if SPL
778 select SPL_OF_CONTROL if SPL
781 Support for the MediaTek SoCs family developed by MediaTek Inc.
782 Please refer to doc/README.mediatek for more information.
785 bool "NXP LPC32xx platform"
795 bool "NXP i.MX8 platform"
799 select ENABLE_ARM_SOC_BOOT0_HOOK
802 bool "NXP i.MX8M platform"
804 select SYS_FSL_HAS_SEC if IMX_HAB
805 select SYS_FSL_SEC_COMPAT_4
806 select SYS_FSL_SEC_LE
812 bool "NXP i.MXRT platform"
820 bool "NXP i.MX23 family"
831 bool "NXP i.MX28 family"
837 bool "NXP i.MX31 family"
843 select SYS_FSL_HAS_SEC if IMX_HAB
844 select SYS_FSL_SEC_COMPAT_4
845 select SYS_FSL_SEC_LE
846 select ROM_UNIFIED_SECTIONS
848 imply SYS_THUMB_BUILD
852 select ARCH_MISC_INIT
854 select SYS_FSL_HAS_SEC if IMX_HAB
855 select SYS_FSL_SEC_COMPAT_4
856 select SYS_FSL_SEC_LE
857 imply BOARD_EARLY_INIT_F
859 imply SYS_THUMB_BUILD
864 select SYS_FSL_HAS_SEC
865 select SYS_FSL_SEC_COMPAT_4
866 select SYS_FSL_SEC_LE
868 imply SYS_THUMB_BUILD
872 default "arch/arm/mach-omap2/u-boot-spl.lds"
877 select BOARD_EARLY_INIT_F
882 bool "Nexell S5P4418/S5P6818 SoC"
883 select ENABLE_ARM_SOC_BOOT0_HOOK
887 bool "Actions Semi OWL SoCs"
895 select SYS_RELOC_GD_ENV_ADDR
899 bool "QEMU Virtual Platform"
910 bool "Renesas ARM SoCs"
913 imply BOARD_EARLY_INIT_F
916 imply SYS_THUMB_BUILD
917 imply ARCH_MISC_INIT if DISPLAY_CPUINFO
919 config ARCH_SNAPDRAGON
920 bool "Qualcomm Snapdragon SoCs"
933 bool "Altera SOCFPGA family"
934 select ARCH_EARLY_INIT_R
935 select ARCH_MISC_INIT if !TARGET_SOCFPGA_ARRIA10
936 select ARM64 if TARGET_SOCFPGA_SOC64
937 select CPU_V7A if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
940 select ENABLE_ARM_SOC_BOOT0_HOOK if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
942 select SPL_DM_RESET if DM_RESET
944 select SPL_LIBCOMMON_SUPPORT
945 select SPL_LIBGENERIC_SUPPORT
946 select SPL_NAND_SUPPORT if SPL_NAND_DENALI
947 select SPL_OF_CONTROL
948 select SPL_SEPARATE_BSS if TARGET_SOCFPGA_SOC64
949 select SPL_SERIAL_SUPPORT
951 select SPL_WATCHDOG_SUPPORT
954 select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
956 select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
957 select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
967 imply SPL_DM_SPI_FLASH
968 imply SPL_LIBDISK_SUPPORT
969 imply SPL_MMC_SUPPORT
970 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION
971 imply SYS_MMCSD_RAW_MODE_U_BOOT_USE_PARTITION_TYPE
972 imply SPL_SPI_FLASH_SUPPORT
973 imply SPL_SPI_SUPPORT
977 bool "Support sunxi (Allwinner) SoCs"
980 select CMD_MMC if MMC
981 select CMD_USB if DISTRO_DEFAULTS
988 select DM_SCSI if SCSI
990 select DM_USB if DISTRO_DEFAULTS
991 select OF_BOARD_SETUP
994 select SPECIFY_CONSOLE_INDEX
995 select SPL_STACK_R if SPL
996 select SPL_SYS_MALLOC_SIMPLE if SPL
997 select SPL_SYS_THUMB_BUILD if !ARM64
1000 select SYS_THUMB_BUILD if !ARM64
1001 select USB if DISTRO_DEFAULTS
1002 select USB_KEYBOARD if DISTRO_DEFAULTS
1003 select USB_STORAGE if DISTRO_DEFAULTS
1004 select SPL_USE_TINY_PRINTF
1006 select SYS_RELOC_GD_ENV_ADDR
1007 imply BOARD_LATE_INIT
1010 imply CMD_UBI if MTD_RAW_NAND
1011 imply DISTRO_DEFAULTS
1014 imply OF_LIBFDT_OVERLAY
1015 imply PRE_CONSOLE_BUFFER
1016 imply SPL_GPIO_SUPPORT
1017 imply SPL_LIBCOMMON_SUPPORT
1018 imply SPL_LIBGENERIC_SUPPORT
1019 imply SPL_MMC_SUPPORT if MMC
1020 imply SPL_POWER_SUPPORT
1021 imply SPL_SERIAL_SUPPORT
1025 bool "ST-Ericsson U8500 Series"
1029 select DM_MMC if MMC
1031 select DM_USB if USB
1035 imply ARM_PL180_MMCI
1037 imply NOMADIK_MTU_TIMER
1040 imply SYSRESET_SYSCON
1043 bool "Support Xilinx Versal Platform"
1047 select DM_ETH if NET
1048 select DM_MMC if MMC
1051 imply BOARD_LATE_INIT
1052 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1055 bool "Freescale Vybrid"
1057 select SYS_FSL_ERRATUM_ESDHC111
1062 bool "Xilinx Zynq based platform"
1067 select DM_ETH if NET
1068 select DM_MMC if MMC
1072 select DM_USB if USB
1075 select SPL_BOARD_INIT if SPL
1076 select SPL_CLK if SPL
1077 select SPL_DM if SPL
1078 select SPL_DM_SPI if SPL
1079 select SPL_DM_SPI_FLASH if SPL
1080 select SPL_OF_CONTROL if SPL
1081 select SPL_SEPARATE_BSS if SPL
1083 imply ARCH_EARLY_INIT_R
1084 imply BOARD_LATE_INIT
1088 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1091 config ARCH_ZYNQMP_R5
1092 bool "Xilinx ZynqMP R5 based platform"
1096 select DM_ETH if NET
1097 select DM_MMC if MMC
1104 bool "Xilinx ZynqMP based platform"
1108 select DM_ETH if NET
1110 select DM_MMC if MMC
1112 select DM_SPI if SPI
1113 select DM_SPI_FLASH if DM_SPI
1114 select DM_USB if USB
1117 select SPL_BOARD_INIT if SPL
1118 select SPL_CLK if SPL
1119 select SPL_DM if SPL
1120 select SPL_DM_SPI if SPI && SPL_DM
1121 select SPL_DM_SPI_FLASH if SPL_DM_SPI
1122 select SPL_DM_MAILBOX if SPL
1123 select SPL_FIRMWARE if SPL
1124 select SPL_SEPARATE_BSS if SPL
1127 imply BOARD_LATE_INIT
1129 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1136 imply DISTRO_DEFAULTS
1139 config TARGET_VEXPRESS64_AEMV8A
1140 bool "Support vexpress_aemv8a"
1144 config TARGET_VEXPRESS64_BASE_FVP
1145 bool "Support Versatile Express ARMv8a FVP BASE model"
1150 config TARGET_VEXPRESS64_JUNO
1151 bool "Support Versatile Express Juno Development Platform"
1166 config TARGET_TOTAL_COMPUTE
1167 bool "Support Total Compute Platform"
1175 config TARGET_LS2080A_EMU
1176 bool "Support ls2080a_emu"
1179 select ARMV8_MULTIENTRY
1180 select FSL_DDR_SYNC_REFRESH
1182 Support for Freescale LS2080A_EMU platform.
1183 The LS2080A Development System (EMULATOR) is a pre-silicon
1184 development platform that supports the QorIQ LS2080A
1185 Layerscape Architecture processor.
1187 config TARGET_LS1088AQDS
1188 bool "Support ls1088aqds"
1191 select ARMV8_MULTIENTRY
1192 select ARCH_SUPPORT_TFABOOT
1193 select BOARD_LATE_INIT
1195 select FSL_DDR_INTERACTIVE if !SD_BOOT
1197 Support for NXP LS1088AQDS platform.
1198 The LS1088A Development System (QDS) is a high-performance
1199 development platform that supports the QorIQ LS1088A
1200 Layerscape Architecture processor.
1202 config TARGET_LS2080AQDS
1203 bool "Support ls2080aqds"
1206 select ARMV8_MULTIENTRY
1207 select ARCH_SUPPORT_TFABOOT
1208 select BOARD_LATE_INIT
1213 select FSL_DDR_INTERACTIVE if !SPL
1215 Support for Freescale LS2080AQDS platform.
1216 The LS2080A Development System (QDS) is a high-performance
1217 development platform that supports the QorIQ LS2080A
1218 Layerscape Architecture processor.
1220 config TARGET_LS2080ARDB
1221 bool "Support ls2080ardb"
1224 select ARMV8_MULTIENTRY
1225 select ARCH_SUPPORT_TFABOOT
1226 select BOARD_LATE_INIT
1229 select FSL_DDR_INTERACTIVE if !SPL
1233 Support for Freescale LS2080ARDB platform.
1234 The LS2080A Reference design board (RDB) is a high-performance
1235 development platform that supports the QorIQ LS2080A
1236 Layerscape Architecture processor.
1238 config TARGET_LS2081ARDB
1239 bool "Support ls2081ardb"
1242 select ARMV8_MULTIENTRY
1243 select BOARD_LATE_INIT
1246 Support for Freescale LS2081ARDB platform.
1247 The LS2081A Reference design board (RDB) is a high-performance
1248 development platform that supports the QorIQ LS2081A/LS2041A
1249 Layerscape Architecture processor.
1251 config TARGET_LX2160ARDB
1252 bool "Support lx2160ardb"
1255 select ARMV8_MULTIENTRY
1256 select ARCH_SUPPORT_TFABOOT
1257 select BOARD_LATE_INIT
1259 Support for NXP LX2160ARDB platform.
1260 The lx2160ardb (LX2160A Reference design board (RDB)
1261 is a high-performance development platform that supports the
1262 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1264 config TARGET_LX2160AQDS
1265 bool "Support lx2160aqds"
1268 select ARMV8_MULTIENTRY
1269 select ARCH_SUPPORT_TFABOOT
1270 select BOARD_LATE_INIT
1272 Support for NXP LX2160AQDS platform.
1273 The lx2160aqds (LX2160A QorIQ Development System (QDS)
1274 is a high-performance development platform that supports the
1275 QorIQ LX2160A/LX2120A/LX2080A Layerscape Architecture processor.
1277 config TARGET_LX2162AQDS
1278 bool "Support lx2162aqds"
1280 select ARCH_MISC_INIT
1282 select ARMV8_MULTIENTRY
1283 select ARCH_SUPPORT_TFABOOT
1284 select BOARD_LATE_INIT
1286 Support for NXP LX2162AQDS platform.
1287 The lx2162aqds support is based on LX2160A Layerscape Architecture processor.
1290 bool "Support HiKey 96boards Consumer Edition Platform"
1297 select SPECIFY_CONSOLE_INDEX
1300 Support for HiKey 96boards platform. It features a HI6220
1301 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
1303 config TARGET_HIKEY960
1304 bool "Support HiKey960 96boards Consumer Edition Platform"
1312 Support for HiKey960 96boards platform. It features a HI3660
1313 SoC, with 4xA73 CPU, 4xA53 CPU, MALI-G71 GPU, and 3GB RAM.
1315 config TARGET_POPLAR
1316 bool "Support Poplar 96boards Enterprise Edition Platform"
1325 Support for Poplar 96boards EE platform. It features a HI3798cv200
1326 SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU
1327 making it capable of running any commercial set-top solution based on
1330 config TARGET_LS1012AQDS
1331 bool "Support ls1012aqds"
1334 select ARCH_SUPPORT_TFABOOT
1335 select BOARD_LATE_INIT
1337 Support for Freescale LS1012AQDS platform.
1338 The LS1012A Development System (QDS) is a high-performance
1339 development platform that supports the QorIQ LS1012A
1340 Layerscape Architecture processor.
1342 config TARGET_LS1012ARDB
1343 bool "Support ls1012ardb"
1346 select ARCH_SUPPORT_TFABOOT
1347 select BOARD_LATE_INIT
1351 Support for Freescale LS1012ARDB platform.
1352 The LS1012A Reference design board (RDB) is a high-performance
1353 development platform that supports the QorIQ LS1012A
1354 Layerscape Architecture processor.
1356 config TARGET_LS1012A2G5RDB
1357 bool "Support ls1012a2g5rdb"
1360 select ARCH_SUPPORT_TFABOOT
1361 select BOARD_LATE_INIT
1364 Support for Freescale LS1012A2G5RDB platform.
1365 The LS1012A 2G5 Reference design board (RDB) is a high-performance
1366 development platform that supports the QorIQ LS1012A
1367 Layerscape Architecture processor.
1369 config TARGET_LS1012AFRWY
1370 bool "Support ls1012afrwy"
1373 select ARCH_SUPPORT_TFABOOT
1374 select BOARD_LATE_INIT
1378 Support for Freescale LS1012AFRWY platform.
1379 The LS1012A FRWY board (FRWY) is a high-performance
1380 development platform that supports the QorIQ LS1012A
1381 Layerscape Architecture processor.
1383 config TARGET_LS1012AFRDM
1384 bool "Support ls1012afrdm"
1387 select ARCH_SUPPORT_TFABOOT
1389 Support for Freescale LS1012AFRDM platform.
1390 The LS1012A Freedom board (FRDM) is a high-performance
1391 development platform that supports the QorIQ LS1012A
1392 Layerscape Architecture processor.
1394 config TARGET_LS1028AQDS
1395 bool "Support ls1028aqds"
1398 select ARMV8_MULTIENTRY
1399 select ARCH_SUPPORT_TFABOOT
1400 select BOARD_LATE_INIT
1402 Support for Freescale LS1028AQDS platform
1403 The LS1028A Development System (QDS) is a high-performance
1404 development platform that supports the QorIQ LS1028A
1405 Layerscape Architecture processor.
1407 config TARGET_LS1028ARDB
1408 bool "Support ls1028ardb"
1411 select ARMV8_MULTIENTRY
1412 select ARCH_SUPPORT_TFABOOT
1413 select BOARD_LATE_INIT
1415 Support for Freescale LS1028ARDB platform
1416 The LS1028A Development System (RDB) is a high-performance
1417 development platform that supports the QorIQ LS1028A
1418 Layerscape Architecture processor.
1420 config TARGET_LS1088ARDB
1421 bool "Support ls1088ardb"
1424 select ARMV8_MULTIENTRY
1425 select ARCH_SUPPORT_TFABOOT
1426 select BOARD_LATE_INIT
1428 select FSL_DDR_INTERACTIVE if !SD_BOOT
1430 Support for NXP LS1088ARDB platform.
1431 The LS1088A Reference design board (RDB) is a high-performance
1432 development platform that supports the QorIQ LS1088A
1433 Layerscape Architecture processor.
1435 config TARGET_LS1021AQDS
1436 bool "Support ls1021aqds"
1438 select ARCH_SUPPORT_PSCI
1439 select BOARD_EARLY_INIT_F
1440 select BOARD_LATE_INIT
1442 select CPU_V7_HAS_NONSEC
1443 select CPU_V7_HAS_VIRT
1444 select LS1_DEEP_SLEEP
1447 select FSL_DDR_INTERACTIVE
1448 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1449 select SPI_FLASH_DATAFLASH if FSL_DSPI || FSL_QSPI
1452 config TARGET_LS1021ATWR
1453 bool "Support ls1021atwr"
1455 select ARCH_SUPPORT_PSCI
1456 select BOARD_EARLY_INIT_F
1457 select BOARD_LATE_INIT
1459 select CPU_V7_HAS_NONSEC
1460 select CPU_V7_HAS_VIRT
1461 select LS1_DEEP_SLEEP
1463 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1466 config TARGET_LS1021ATSN
1467 bool "Support ls1021atsn"
1469 select ARCH_SUPPORT_PSCI
1470 select BOARD_EARLY_INIT_F
1471 select BOARD_LATE_INIT
1473 select CPU_V7_HAS_NONSEC
1474 select CPU_V7_HAS_VIRT
1475 select LS1_DEEP_SLEEP
1479 config TARGET_LS1021AIOT
1480 bool "Support ls1021aiot"
1482 select ARCH_SUPPORT_PSCI
1483 select BOARD_LATE_INIT
1485 select CPU_V7_HAS_NONSEC
1486 select CPU_V7_HAS_VIRT
1488 select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI
1491 Support for Freescale LS1021AIOT platform.
1492 The LS1021A Freescale board (IOT) is a high-performance
1493 development platform that supports the QorIQ LS1021A
1494 Layerscape Architecture processor.
1496 config TARGET_LS1043AQDS
1497 bool "Support ls1043aqds"
1500 select ARMV8_MULTIENTRY
1501 select ARCH_SUPPORT_TFABOOT
1502 select BOARD_EARLY_INIT_F
1503 select BOARD_LATE_INIT
1505 select FSL_DDR_INTERACTIVE if !SPL
1506 select FSL_DSPI if !SPL_NO_DSPI
1507 select DM_SPI_FLASH if FSL_DSPI
1511 Support for Freescale LS1043AQDS platform.
1513 config TARGET_LS1043ARDB
1514 bool "Support ls1043ardb"
1517 select ARMV8_MULTIENTRY
1518 select ARCH_SUPPORT_TFABOOT
1519 select BOARD_EARLY_INIT_F
1520 select BOARD_LATE_INIT
1522 select FSL_DSPI if !SPL_NO_DSPI
1523 select DM_SPI_FLASH if FSL_DSPI
1525 Support for Freescale LS1043ARDB platform.
1527 config TARGET_LS1046AQDS
1528 bool "Support ls1046aqds"
1531 select ARMV8_MULTIENTRY
1532 select ARCH_SUPPORT_TFABOOT
1533 select BOARD_EARLY_INIT_F
1534 select BOARD_LATE_INIT
1535 select DM_SPI_FLASH if DM_SPI
1537 select FSL_DDR_BIST if !SPL
1538 select FSL_DDR_INTERACTIVE if !SPL
1539 select FSL_DDR_INTERACTIVE if !SPL
1542 Support for Freescale LS1046AQDS platform.
1543 The LS1046A Development System (QDS) is a high-performance
1544 development platform that supports the QorIQ LS1046A
1545 Layerscape Architecture processor.
1547 config TARGET_LS1046ARDB
1548 bool "Support ls1046ardb"
1551 select ARMV8_MULTIENTRY
1552 select ARCH_SUPPORT_TFABOOT
1553 select BOARD_EARLY_INIT_F
1554 select BOARD_LATE_INIT
1555 select DM_SPI_FLASH if DM_SPI
1556 select POWER_MC34VR500
1559 select FSL_DDR_INTERACTIVE if !SPL
1562 Support for Freescale LS1046ARDB platform.
1563 The LS1046A Reference Design Board (RDB) is a high-performance
1564 development platform that supports the QorIQ LS1046A
1565 Layerscape Architecture processor.
1567 config TARGET_LS1046AFRWY
1568 bool "Support ls1046afrwy"
1571 select ARMV8_MULTIENTRY
1572 select ARCH_SUPPORT_TFABOOT
1573 select BOARD_EARLY_INIT_F
1574 select BOARD_LATE_INIT
1575 select DM_SPI_FLASH if DM_SPI
1578 Support for Freescale LS1046AFRWY platform.
1579 The LS1046A Freeway Board (FRWY) is a high-performance
1580 development platform that supports the QorIQ LS1046A
1581 Layerscape Architecture processor.
1587 select ARMV8_MULTIENTRY
1591 Support for Kontron SMARC-sAL28 board.
1593 config TARGET_COLIBRI_PXA270
1594 bool "Support colibri_pxa270"
1597 config ARCH_UNIPHIER
1598 bool "Socionext UniPhier SoCs"
1599 select BOARD_LATE_INIT
1609 select OF_BOARD_SETUP
1613 select SPL_BOARD_INIT if SPL
1614 select SPL_DM if SPL
1615 select SPL_LIBCOMMON_SUPPORT if SPL
1616 select SPL_LIBGENERIC_SUPPORT if SPL
1617 select SPL_OF_CONTROL if SPL
1618 select SPL_PINCTRL if SPL
1621 imply DISTRO_DEFAULTS
1624 Support for UniPhier SoC family developed by Socionext Inc.
1625 (formerly, System LSI Business Division of Panasonic Corporation)
1628 bool "Support STMicroelectronics STM32 MCU with cortex M"
1635 bool "Support STMicrolectronics SoCs"
1644 Support for STMicroelectronics STiH407/10 SoC family.
1645 This SoC is used on Linaro 96Board STiH410-B2260
1648 bool "Support STMicroelectronics STM32MP Socs with cortex A"
1649 select ARCH_MISC_INIT
1650 select ARCH_SUPPORT_TFABOOT
1651 select BOARD_LATE_INIT
1660 select OF_SYSTEM_SETUP
1666 select SYS_THUMB_BUILD
1670 imply OF_LIBFDT_OVERLAY
1671 imply ENV_VARS_UBOOT_RUNTIME_CONFIG
1674 Support for STM32MP SoC family developed by STMicroelectronics,
1675 MPUs based on ARM cortex A core
1676 U-BOOT is running in DDR, loaded by the First Stage BootLoader (FSBL).
1677 FSBL can be TF-A: Trusted Firmware for Cortex A, for trusted boot
1679 SPL is the unsecure FSBL for the basic boot chain.
1681 config ARCH_ROCKCHIP
1682 bool "Support Rockchip SoCs"
1684 select BINMAN if SPL_OPTEE
1694 select DM_USB if USB
1695 select ENABLE_ARM_SOC_BOOT0_HOOK
1698 select SPL_DM if SPL
1699 select SPL_DM_SPI if SPL
1700 select SPL_DM_SPI_FLASH if SPL
1702 select SYS_THUMB_BUILD if !ARM64
1705 imply DEBUG_UART_BOARD_INIT
1706 imply DISTRO_DEFAULTS
1708 imply SARADC_ROCKCHIP
1710 imply SPL_SYS_MALLOC_SIMPLE
1713 imply USB_FUNCTION_FASTBOOT
1715 config ARCH_OCTEONTX
1716 bool "Support OcteonTX SoCs"
1722 select BOARD_LATE_INIT
1723 select SYS_CACHE_SHIFT_7
1725 config ARCH_OCTEONTX2
1726 bool "Support OcteonTX2 SoCs"
1732 select BOARD_LATE_INIT
1733 select SYS_CACHE_SHIFT_7
1735 config TARGET_THUNDERX_88XX
1736 bool "Support ThunderX 88xx"
1740 select SYS_CACHE_SHIFT_7
1743 bool "Support Aspeed SoCs"
1748 config TARGET_DURIAN
1749 bool "Support Phytium Durian Platform"
1752 Support for durian platform.
1753 It has 2GB Sdram, uart and pcie.
1755 config TARGET_PRESIDIO_ASIC
1756 bool "Support Cortina Presidio ASIC Platform"
1759 config TARGET_XENGUEST_ARM64
1760 bool "Xen guest ARM64"
1764 select LINUX_KERNEL_IMAGE_HEADER
1769 config ARCH_SUPPORT_TFABOOT
1773 bool "Support for booting from TF-A"
1774 depends on ARCH_SUPPORT_TFABOOT
1777 Some platforms support the setup of secure registers (for instance
1778 for CPU errata handling) or provide secure services like PSCI.
1779 Those services could also be provided by other firmware parts
1780 like TF-A (Trusted Firmware for Cortex-A), in which case U-Boot
1781 does not need to (and cannot) execute this code.
1782 Enabling this option will make a U-Boot binary that is relying
1783 on other firmware layers to provide secure functionality.
1785 config TI_SECURE_DEVICE
1786 bool "HS Device Type Support"
1787 depends on ARCH_KEYSTONE || ARCH_OMAP2PLUS || ARCH_K3
1789 If a high secure (HS) device type is being used, this config
1790 must be set. This option impacts various aspects of the
1791 build system (to create signed boot images that can be
1792 authenticated) and the code. See the doc/README.ti-secure
1793 file for further details.
1795 if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
1796 config ISW_ENTRY_ADDR
1797 hex "Address in memory or XIP address of bootloader entry point"
1798 default 0x402F4000 if AM43XX
1799 default 0x402F0400 if AM33XX
1800 default 0x40301350 if OMAP54XX
1802 After any reset, the boot ROM searches the boot media for a valid
1803 boot image. For non-XIP devices, the ROM then copies the image into
1804 internal memory. For all boot modes, after the ROM processes the
1805 boot image it eventually computes the entry point address depending
1806 on the device type (secure/non-secure), boot media (xip/non-xip) and
1810 source "arch/arm/mach-aspeed/Kconfig"
1812 source "arch/arm/mach-at91/Kconfig"
1814 source "arch/arm/mach-bcm283x/Kconfig"
1816 source "arch/arm/mach-bcmstb/Kconfig"
1818 source "arch/arm/mach-davinci/Kconfig"
1820 source "arch/arm/mach-exynos/Kconfig"
1822 source "arch/arm/mach-highbank/Kconfig"
1824 source "arch/arm/mach-integrator/Kconfig"
1826 source "arch/arm/mach-ipq40xx/Kconfig"
1828 source "arch/arm/mach-k3/Kconfig"
1830 source "arch/arm/mach-keystone/Kconfig"
1832 source "arch/arm/mach-kirkwood/Kconfig"
1834 source "arch/arm/mach-lpc32xx/Kconfig"
1836 source "arch/arm/mach-mvebu/Kconfig"
1838 source "arch/arm/mach-octeontx/Kconfig"
1840 source "arch/arm/mach-octeontx2/Kconfig"
1842 source "arch/arm/cpu/armv7/ls102xa/Kconfig"
1844 source "arch/arm/mach-imx/mx2/Kconfig"
1846 source "arch/arm/mach-imx/mx3/Kconfig"
1848 source "arch/arm/mach-imx/mx5/Kconfig"
1850 source "arch/arm/mach-imx/mx6/Kconfig"
1852 source "arch/arm/mach-imx/mx7/Kconfig"
1854 source "arch/arm/mach-imx/mx7ulp/Kconfig"
1856 source "arch/arm/mach-imx/imx8/Kconfig"
1858 source "arch/arm/mach-imx/imx8m/Kconfig"
1860 source "arch/arm/mach-imx/imxrt/Kconfig"
1862 source "arch/arm/mach-imx/mxs/Kconfig"
1864 source "arch/arm/mach-omap2/Kconfig"
1866 source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
1868 source "arch/arm/mach-orion5x/Kconfig"
1870 source "arch/arm/mach-owl/Kconfig"
1872 source "arch/arm/mach-rmobile/Kconfig"
1874 source "arch/arm/mach-meson/Kconfig"
1876 source "arch/arm/mach-mediatek/Kconfig"
1878 source "arch/arm/mach-qemu/Kconfig"
1880 source "arch/arm/mach-rockchip/Kconfig"
1882 source "arch/arm/mach-s5pc1xx/Kconfig"
1884 source "arch/arm/mach-snapdragon/Kconfig"
1886 source "arch/arm/mach-socfpga/Kconfig"
1888 source "arch/arm/mach-sti/Kconfig"
1890 source "arch/arm/mach-stm32/Kconfig"
1892 source "arch/arm/mach-stm32mp/Kconfig"
1894 source "arch/arm/mach-sunxi/Kconfig"
1896 source "arch/arm/mach-tegra/Kconfig"
1898 source "arch/arm/mach-u8500/Kconfig"
1900 source "arch/arm/mach-uniphier/Kconfig"
1902 source "arch/arm/cpu/armv7/vf610/Kconfig"
1904 source "arch/arm/mach-zynq/Kconfig"
1906 source "arch/arm/mach-zynqmp/Kconfig"
1908 source "arch/arm/mach-versal/Kconfig"
1910 source "arch/arm/mach-zynqmp-r5/Kconfig"
1912 source "arch/arm/cpu/armv7/Kconfig"
1914 source "arch/arm/cpu/armv8/Kconfig"
1916 source "arch/arm/mach-imx/Kconfig"
1918 source "arch/arm/mach-nexell/Kconfig"
1920 source "board/armltd/total_compute/Kconfig"
1922 source "board/bosch/shc/Kconfig"
1923 source "board/bosch/guardian/Kconfig"
1924 source "board/CarMediaLab/flea3/Kconfig"
1925 source "board/Marvell/aspenite/Kconfig"
1926 source "board/Marvell/gplugd/Kconfig"
1927 source "board/Marvell/octeontx/Kconfig"
1928 source "board/Marvell/octeontx2/Kconfig"
1929 source "board/armltd/vexpress64/Kconfig"
1930 source "board/cortina/presidio-asic/Kconfig"
1931 source "board/broadcom/bcm963158/Kconfig"
1932 source "board/broadcom/bcm968360bg/Kconfig"
1933 source "board/broadcom/bcm968580xref/Kconfig"
1934 source "board/broadcom/bcmns3/Kconfig"
1935 source "board/cavium/thunderx/Kconfig"
1936 source "board/cirrus/edb93xx/Kconfig"
1937 source "board/eets/pdu001/Kconfig"
1938 source "board/emulation/qemu-arm/Kconfig"
1939 source "board/freescale/ls2080aqds/Kconfig"
1940 source "board/freescale/ls2080ardb/Kconfig"
1941 source "board/freescale/ls1088a/Kconfig"
1942 source "board/freescale/ls1028a/Kconfig"
1943 source "board/freescale/ls1021aqds/Kconfig"
1944 source "board/freescale/ls1043aqds/Kconfig"
1945 source "board/freescale/ls1021atwr/Kconfig"
1946 source "board/freescale/ls1021atsn/Kconfig"
1947 source "board/freescale/ls1021aiot/Kconfig"
1948 source "board/freescale/ls1046aqds/Kconfig"
1949 source "board/freescale/ls1043ardb/Kconfig"
1950 source "board/freescale/ls1046ardb/Kconfig"
1951 source "board/freescale/ls1046afrwy/Kconfig"
1952 source "board/freescale/ls1012aqds/Kconfig"
1953 source "board/freescale/ls1012ardb/Kconfig"
1954 source "board/freescale/ls1012afrdm/Kconfig"
1955 source "board/freescale/lx2160a/Kconfig"
1956 source "board/grinn/chiliboard/Kconfig"
1957 source "board/hisilicon/hikey/Kconfig"
1958 source "board/hisilicon/hikey960/Kconfig"
1959 source "board/hisilicon/poplar/Kconfig"
1960 source "board/isee/igep003x/Kconfig"
1961 source "board/kontron/sl28/Kconfig"
1962 source "board/myir/mys_6ulx/Kconfig"
1963 source "board/spear/spear300/Kconfig"
1964 source "board/spear/spear310/Kconfig"
1965 source "board/spear/spear320/Kconfig"
1966 source "board/spear/spear600/Kconfig"
1967 source "board/spear/x600/Kconfig"
1968 source "board/st/stv0991/Kconfig"
1969 source "board/tcl/sl50/Kconfig"
1970 source "board/toradex/colibri_pxa270/Kconfig"
1971 source "board/variscite/dart_6ul/Kconfig"
1972 source "board/vscom/baltos/Kconfig"
1973 source "board/phytium/durian/Kconfig"
1974 source "board/xen/xenguest_arm64/Kconfig"
1976 source "arch/arm/Kconfig.debug"
1981 default "arch/arm/cpu/arm926ejs/mxs/u-boot-spl.lds" if (ARCH_MX23 || ARCH_MX28) && !SPL_FRAMEWORK
1982 default "arch/arm/cpu/arm1136/u-boot-spl.lds" if CPU_ARM1136
1983 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARM64