2 * TLB Exception Handling for ARC
4 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Vineetg: April 2011 :
11 * -MMU v1: moved out legacy code into a seperate file
12 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
13 * helps avoid a shift when preparing PD0 from PTE
16 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
17 * entry, so that it doesn't knock out it's I-TLB entry
18 * -Some more fine tuning:
19 * bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
22 * -Practically rewrote the I/D TLB Miss handlers
23 * Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
24 * Hence Leaner by 1.5 K
25 * Used Conditional arithmetic to replace excessive branching
26 * Also used short instructions wherever possible
28 * Vineetg: Aug 13th 2008
29 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
30 * more information in case of a Fatality
32 * Vineetg: March 25th Bug #92690
33 * -Added Debug Code to check if sw-ASID == hw-ASID
35 * Rahul Trivedi, Amit Bhor: Codito Technologies 2004
40 #include <linux/linkage.h>
41 #include <asm/entry.h>
43 #include <asm/pgtable.h>
44 #include <asm/arcregs.h>
45 #include <asm/cache.h>
46 #include <asm/processor.h>
47 #if (CONFIG_ARC_MMU_VER == 1)
48 #include <asm/tlb-mmu1.h>
51 ;--------------------------------------------------------------------------
52 ; scratch memory to save the registers (r0-r3) used to code TLB refill Handler
53 ; For details refer to comments before TLBMISS_FREEUP_REGS below
54 ;--------------------------------------------------------------------------
58 .align 1 << L1_CACHE_SHIFT ; IMP: Must be Cache Line aligned
59 .type ex_saved_reg1, @object
60 .size ex_saved_reg1, 16
64 ;============================================================================
65 ; Troubleshooting Stuff
66 ;============================================================================
68 ; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
69 ; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
70 ; we use the MMU PID Reg to get current ASID.
71 ; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
72 ; So we try to detect this in TLB Mis shandler
75 .macro DBG_ASID_MISMATCH
77 #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
79 ; make sure h/w ASID is same as s/w ASID
81 GET_CURR_TASK_ON_CPU r3
82 ld r0, [r3, TASK_ACT_MM]
83 ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
89 ; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
91 bbit0 r0, STATUS_U_BIT, 5f
93 ; We sure are in troubled waters, Flag the error, but to do so
94 ; need to switch to kernel mode stack to call error routine
95 GET_TSK_STACK_BASE r3, sp
97 ; Call printk to shoutout aloud
101 5: ; ASIDs match so proceed normally
108 ;============================================================================
109 ;TLB Miss handling Code
110 ;============================================================================
112 ;-----------------------------------------------------------------------------
113 ; This macro does the page-table lookup for the faulting address.
114 ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
115 .macro LOAD_FAULT_PTE
119 lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
121 lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
122 ld.as r1, [r1, r0] ; PGD entry corresp to faulting addr
123 and.f r1, r1, PAGE_MASK ; Ignoring protection and other flags
124 ; contains Ptr to Page Table
125 bz.d do_slow_path_pf ; if no Page Table, do page fault
127 ; Get the PTE entry: The idea is
128 ; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr
129 ; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
131 ; To avoid the multiply by in end, we do the -2, <<2 below
133 lsr r0, r2, (PAGE_SHIFT - 2)
134 and r0, r0, ( (PTRS_PER_PTE - 1) << 2)
135 ld.aw r0, [r1, r0] ; get PTE and PTE ptr for fault addr
136 #ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
137 and.f 0, r0, _PAGE_PRESENT
139 ld r2, [num_pte_not_present]
141 st r2, [num_pte_not_present]
147 ;-----------------------------------------------------------------
148 ; Convert Linux PTE entry into TLB entry
149 ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
150 ; IN: r0 = PTE, r1 = ptr to PTE
152 .macro CONV_PTE_TO_TLB
153 and r3, r0, PTE_BITS_IN_PD1 ; Extract permission flags+PFN from PTE
154 sr r3, [ARC_REG_TLBPD1] ; these go in PD1
156 and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
157 #if (CONFIG_ARC_MMU_VER <= 2) /* Neednot be done with v3 onwards */
158 lsr r2, r2 ; shift PTE flags to match layout in PD0
161 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
163 or r3, r3, r2 ; S | vaddr | {sasid|asid}
164 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
167 ;-----------------------------------------------------------------
168 ; Commit the TLB entry into MMU
170 .macro COMMIT_ENTRY_TO_MMU
172 /* Get free TLB slot: Set = computed from vaddr, way = random */
173 sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
175 /* Commit the Write */
176 #if (CONFIG_ARC_MMU_VER >= 2) /* introduced in v2 */
177 sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
179 sr TLBWrite, [ARC_REG_TLBCOMMAND]
183 ;-----------------------------------------------------------------
184 ; ARC700 Exception Handling doesn't auto-switch stack and it only provides
185 ; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
187 ; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
188 ; "global" is used to free-up FIRST core reg to be able to code the rest of
189 ; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
190 ; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
191 ; need to be saved as well by extending the "global" to be 4 words. Hence
192 ; ".size ex_saved_reg1, 16"
193 ; [All of this dance is to avoid stack switching for each TLB Miss, since we
194 ; only need to save only a handful of regs, as opposed to complete reg file]
196 ; As simple as that....
198 .macro TLBMISS_FREEUP_REGS
199 st r0, [@ex_saved_reg1]
200 mov_s r0, @ex_saved_reg1
205 ; VERIFY if the ASID in MMU-PID Reg is same as
206 ; one in Linux data structures
211 ;-----------------------------------------------------------------
212 .macro TLBMISS_RESTORE_REGS
213 mov_s r0, @ex_saved_reg1
220 .section .text, "ax",@progbits ;Fast Path Code, candidate for ICCM
222 ;-----------------------------------------------------------------------------
223 ; I-TLB Miss Exception Handler
224 ;-----------------------------------------------------------------------------
226 ARC_ENTRY EV_TLBMissI
230 #ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
236 ;----------------------------------------------------------------
237 ; Get the PTE corresponding to V-addr accessed
240 ;----------------------------------------------------------------
241 ; VERIFY_PTE: Check if PTE permissions approp for executing code
242 cmp_s r2, VMALLOC_START
243 mov.lo r2, (_PAGE_PRESENT | _PAGE_READ | _PAGE_EXECUTE)
244 mov.hs r2, (_PAGE_PRESENT | _PAGE_K_READ | _PAGE_K_EXECUTE)
246 and r3, r0, r2 ; Mask out NON Flag bits from PTE
247 xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test )
250 ; Let Linux VM know that the page was accessed
251 or r0, r0, (_PAGE_PRESENT | _PAGE_ACCESSED) ; set Accessed Bit
252 st_s r0, [r1] ; Write back PTE
261 ;-----------------------------------------------------------------------------
262 ; D-TLB Miss Exception Handler
263 ;-----------------------------------------------------------------------------
265 ARC_ENTRY EV_TLBMissD
269 #ifdef CONFIG_ARC_DBG_TLB_MISS_COUNT
275 ;----------------------------------------------------------------
276 ; Get the PTE corresponding to V-addr accessed
277 ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE
280 ;----------------------------------------------------------------
281 ; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)
285 btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access
286 or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE
287 btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access
288 or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE
289 ; Above laddering takes care of XCHG access
290 ; which is both Read and Write
292 ; If kernel mode access, ; make _PAGE_xx flags as _PAGE_K_xx
293 ; For copy_(to|from)_user, despite exception taken in kernel mode,
294 ; this code is not hit, because EFA would still be the user mode
295 ; address (EFA < 0x6000_0000).
296 ; This code is for legit kernel mode faults, vmalloc specifically
297 ; (EFA: 0x7000_0000 to 0x7FFF_FFFF)
300 cmp r3, VMALLOC_START - 1 ; If kernel mode access
301 asl.hi r2, r2, 3 ; make _PAGE_xx flags as _PAGE_K_xx
302 or r2, r2, _PAGE_PRESENT ; Common flag for K/U mode
304 ; By now, r2 setup with all the Flags we need to check in PTE
305 and r3, r0, r2 ; Mask out NON Flag bits from PTE
306 brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)
308 ;----------------------------------------------------------------
309 ; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
311 or r0, r0, (_PAGE_PRESENT | _PAGE_ACCESSED) ; Accessed bit always
312 btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; See if it was a Write Access ?
313 or.nz r0, r0, _PAGE_MODIFIED ; if Write, set Dirty bit as well
314 st_s r0, [r1] ; Write back PTE
318 #if (CONFIG_ARC_MMU_VER == 1)
319 ; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
320 ; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
321 ; But only for old MMU or one with Metal Fix
329 ;-------- Common routine to call Linux Page Fault Handler -----------
332 ; Restore the 4-scratch regs saved by fast path miss handler
335 ; Slow path TLB Miss handled as a regular ARC Exception
336 ; (stack switching / save the complete reg-file).
337 ; That requires freeing up r9
338 EXCPN_PROLOG_FREEUP_REG r9
345 ; ------- setup args for Linux Page fault Hanlder ---------
350 ; Both st and ex imply WRITE access of some sort, hence do_page_fault( )
351 ; invoked with write=1 for DTLB-st/ex Miss and write=0 for ITLB miss or
353 ; DTLB Miss Cause code is ld = 0x01 , st = 0x02, ex = 0x03
354 ; Following code uses that fact that st/ex have one bit in common
356 btst_s r3, ECR_C_BIT_DTLB_ST_MISS
360 ; We don't want exceptions to be disabled while the fault is handled.
361 ; Now that we have saved the context we return from exception hence
362 ; exceptions get re-enable
364 FAKE_RET_FROM_EXCPN r9
371 ARC_ENTRY EV_TLBMissB ; Bogus entry to measure sz of DTLBMiss hdlr