1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
6 #include <asm-offsets.h>
8 #include <linux/linkage.h>
9 #include <asm/arcregs.h>
10 #include <system-constants.h>
13 /* Setup interrupt vector base that matches "__text_start" */
14 sr __ivt_start, [ARC_AUX_INTR_VEC_BASE]
16 ; Disable/enable I-cache according to configuration
17 lr r5, [ARC_BCR_IC_BUILD]
18 breq r5, 0, 1f ; I$ doesn't exist
19 lr r5, [ARC_AUX_IC_CTRL]
20 #if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
21 bclr r5, r5, 0 ; 0 - Enable, 1 is Disable
23 bset r5, r5, 0 ; I$ exists, but is not used
25 sr r5, [ARC_AUX_IC_CTRL]
28 sr r5, [ARC_AUX_IC_IVIC]
29 ; As per ARC HS databook (see chapter 5.3.3.2)
30 ; it is required to add 3 NOPs after each write to IC_IVIC.
36 ; Disable/enable D-cache according to configuration
37 lr r5, [ARC_BCR_DC_BUILD]
38 breq r5, 0, 1f ; D$ doesn't exist
39 lr r5, [ARC_AUX_DC_CTRL]
40 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
41 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
42 bclr r5, r5, 0 ; Enable (+Inv)
44 bset r5, r5, 0 ; Disable (+Inv)
46 sr r5, [ARC_AUX_DC_CTRL]
49 sr r5, [ARC_AUX_DC_IVDC]
53 #ifdef CONFIG_ISA_ARCV2
54 ; Disable System-Level Cache (SLC)
56 breq r5, 0, 1f ; SLC doesn't exist
57 lr r5, [ARC_AUX_SLC_CTRL]
58 bclr r5, r5, 6 ; Invalidate (discard w/o wback)
59 bclr r5, r5, 0 ; Enable (+Inv)
60 sr r5, [ARC_AUX_SLC_CTRL]
65 #ifdef CONFIG_ISA_ARCV2
66 ; In case of DSP extension presence in HW some instructions
67 ; (related to integer multiply, multiply-accumulate, and divide
68 ; operation) executes on this DSP execution unit. So their
69 ; execution will depend on dsp configuration register (DSP_CTRL)
70 ; As we want these instructions to execute the same way regardless
71 ; of DSP presence we need to set DSP_CTRL properly.
72 lr r5, [ARC_AUX_DSP_BUILD]
76 sr r5, [ARC_AUX_DSP_CTRL]
80 #ifdef __ARC_UNALIGNED__
82 * Enable handling of unaligned access in the CPU as by default
83 * this HW feature is disabled while GCC starting from 8.1.0
84 * unconditionally uses it for ARC HS cores.
86 flag 1 << STATUS_AD_BIT
89 /* Establish C runtime stack and frame */
90 mov %sp, SYS_INIT_SP_ADDR
93 /* Allocate reserved area from current top of stack */
95 bl board_init_f_alloc_reserve
96 /* Set stack below reserved area, adjust frame pointer accordingly */
100 /* Initialize reserved area - note: r0 already contains address */
101 bl board_init_f_init_reserve
103 #ifdef CONFIG_DEBUG_UART
104 /* Earliest point to set up early debug uart */
108 /* Zero the one and only argument of "board_init_f" */
112 /* We only get here if relocation is disabled by GD_FLG_SKIP_RELOC */
113 /* Make sure we don't lose GD overwritten by zero new GD */
120 * void board_init_f_r_trampoline(stack-pointer address)
122 * This "function" does not return, instead it continues in RAM
123 * after relocating the monitor code.
125 * r0 = new stack-pointer
127 ENTRY(board_init_f_r_trampoline)
128 /* Set up the stack- and frame-pointers */
132 /* Update position of intterupt vector table */
133 lr %r0, [ARC_AUX_INTR_VEC_BASE]
134 ld %r1, [%r25, GD_RELOC_OFF]
136 sr %r0, [ARC_AUX_INTR_VEC_BASE]
138 /* Re-enter U-Boot by calling board_init_f_r */
140 ENDPROC(board_init_f_r_trampoline)