2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/compiler.h>
10 #include <linux/kernel.h>
11 #include <linux/log2.h>
12 #include <asm/arcregs.h>
13 #include <asm/cache.h>
15 /* Bit values in IC_CTRL */
16 #define IC_CTRL_CACHE_DISABLE (1 << 0)
18 /* Bit values in DC_CTRL */
19 #define DC_CTRL_CACHE_DISABLE (1 << 0)
20 #define DC_CTRL_INV_MODE_FLUSH (1 << 6)
21 #define DC_CTRL_FLUSH_STATUS (1 << 8)
22 #define CACHE_VER_NUM_MASK 0xF
28 /* Bit val in SLC_CONTROL */
29 #define SLC_CTRL_DIS 0x001
30 #define SLC_CTRL_IM 0x040
31 #define SLC_CTRL_BUSY 0x100
32 #define SLC_CTRL_RGN_OP_INV 0x200
35 * By default that variable will fall into .bss section.
36 * But .bss section is not relocated and so it will be initilized before
37 * relocation but will be used after being zeroed.
39 int l1_line_sz __section(".data");
40 bool dcache_exists __section(".data") = false;
41 bool icache_exists __section(".data") = false;
43 #define CACHE_LINE_MASK (~(l1_line_sz - 1))
45 #ifdef CONFIG_ISA_ARCV2
46 int slc_line_sz __section(".data");
47 bool slc_exists __section(".data") = false;
48 bool ioc_exists __section(".data") = false;
49 bool pae_exists __section(".data") = false;
51 void read_decode_mmu_bcr(void)
53 /* TODO: should we compare mmu version from BCR and from CONFIG? */
54 #if (CONFIG_ARC_MMU_VER >= 4)
57 tmp = read_aux_reg(ARC_AUX_MMU_BCR);
60 #ifdef CONFIG_CPU_BIG_ENDIAN
61 unsigned int ver:8, sasid:1, sz1:4, sz0:4, res:2, pae:1,
62 n_ways:2, n_entry:2, n_super:2, u_itlb:3, u_dtlb:3;
64 /* DTLB ITLB JES JE JA */
65 unsigned int u_dtlb:3, u_itlb:3, n_super:2, n_entry:2, n_ways:2,
66 pae:1, res:2, sz0:4, sz1:4, sasid:1, ver:8;
67 #endif /* CONFIG_CPU_BIG_ENDIAN */
70 mmu4 = (struct bcr_mmu_4 *)&tmp;
72 pae_exists = !!mmu4->pae;
73 #endif /* (CONFIG_ARC_MMU_VER >= 4) */
76 static void __slc_entire_op(const int op)
80 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
82 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
83 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
87 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
89 if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */
90 write_aux_reg(ARC_AUX_SLC_INVALIDATE, 0x1);
92 write_aux_reg(ARC_AUX_SLC_FLUSH, 0x1);
94 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
95 read_aux_reg(ARC_AUX_SLC_CTRL);
97 /* Important to wait for flush to complete */
98 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
101 static void slc_upper_region_init(void)
104 * ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1 are always == 0
105 * as we don't use PAE40.
107 write_aux_reg(ARC_AUX_SLC_RGN_END1, 0);
108 write_aux_reg(ARC_AUX_SLC_RGN_START1, 0);
111 static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op)
117 * The Region Flush operation is specified by CTRL.RGN_OP[11..9]
118 * - b'000 (default) is Flush,
119 * - b'001 is Invalidate if CTRL.IM == 0
120 * - b'001 is Flush-n-Invalidate if CTRL.IM == 1
122 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL);
124 /* Don't rely on default value of IM bit */
125 if (!(op & OP_FLUSH)) /* i.e. OP_INV */
126 ctrl &= ~SLC_CTRL_IM; /* clear IM: Disable flush before Inv */
131 ctrl |= SLC_CTRL_RGN_OP_INV; /* Inv or flush-n-inv */
133 ctrl &= ~SLC_CTRL_RGN_OP_INV;
135 write_aux_reg(ARC_AUX_SLC_CTRL, ctrl);
138 * Lower bits are ignored, no need to clip
139 * END needs to be setup before START (latter triggers the operation)
140 * END can't be same as START, so add (l2_line_sz - 1) to sz
142 end = paddr + sz + slc_line_sz - 1;
145 * Upper addresses (ARC_AUX_SLC_RGN_END1 and ARC_AUX_SLC_RGN_START1)
146 * are always == 0 as we don't use PAE40, so we only setup lower ones
147 * (ARC_AUX_SLC_RGN_END and ARC_AUX_SLC_RGN_START)
149 write_aux_reg(ARC_AUX_SLC_RGN_END, end);
150 write_aux_reg(ARC_AUX_SLC_RGN_START, paddr);
152 /* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
153 read_aux_reg(ARC_AUX_SLC_CTRL);
155 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY);
157 #endif /* CONFIG_ISA_ARCV2 */
159 #ifdef CONFIG_ISA_ARCV2
160 static void read_decode_cache_bcr_arcv2(void)
164 #ifdef CONFIG_CPU_BIG_ENDIAN
165 unsigned int pad:24, way:2, lsz:2, sz:4;
167 unsigned int sz:4, lsz:2, way:2, pad:24;
175 #ifdef CONFIG_CPU_BIG_ENDIAN
176 unsigned int pad:24, ver:8;
178 unsigned int ver:8, pad:24;
184 sbcr.word = read_aux_reg(ARC_BCR_SLC);
185 if (sbcr.fields.ver) {
186 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
188 slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
192 struct bcr_clust_cfg {
193 #ifdef CONFIG_CPU_BIG_ENDIAN
194 unsigned int pad:7, c:1, num_entries:8, num_cores:8, ver:8;
196 unsigned int ver:8, num_cores:8, num_entries:8, c:1, pad:7;
202 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER);
208 void read_decode_cache_bcr(void)
210 int dc_line_sz = 0, ic_line_sz = 0;
214 #ifdef CONFIG_CPU_BIG_ENDIAN
215 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
217 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
223 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
224 if (ibcr.fields.ver) {
225 icache_exists = true;
226 l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
228 panic("Instruction exists but line length is 0\n");
231 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
232 if (dbcr.fields.ver){
233 dcache_exists = true;
234 l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
236 panic("Data cache exists but line length is 0\n");
239 if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
240 panic("Instruction and data cache line lengths differ\n");
243 void cache_init(void)
245 read_decode_cache_bcr();
247 #ifdef CONFIG_ISA_ARCV2
248 read_decode_cache_bcr_arcv2();
251 /* IOC Aperture start is equal to DDR start */
252 unsigned int ap_base = CONFIG_SYS_SDRAM_BASE;
253 /* IOC Aperture size is equal to DDR size */
254 long ap_size = CONFIG_SYS_SDRAM_SIZE;
257 invalidate_dcache_all();
259 if (!is_power_of_2(ap_size) || ap_size < 4096)
260 panic("IOC Aperture size must be power of 2 and bigger 4Kib");
263 * IOC Aperture size decoded as 2 ^ (SIZE + 2) KB,
264 * so setting 0x11 implies 512M, 0x12 implies 1G...
266 write_aux_reg(ARC_AUX_IO_COH_AP0_SIZE,
267 order_base_2(ap_size/1024) - 2);
270 /* IOC Aperture start must be aligned to the size of the aperture */
271 if (ap_base % ap_size != 0)
272 panic("IOC Aperture start must be aligned to the size of the aperture");
274 write_aux_reg(ARC_AUX_IO_COH_AP0_BASE, ap_base >> 12);
275 write_aux_reg(ARC_AUX_IO_COH_PARTIAL, 1);
276 write_aux_reg(ARC_AUX_IO_COH_ENABLE, 1);
280 read_decode_mmu_bcr();
283 * ARC_AUX_SLC_RGN_START1 and ARC_AUX_SLC_RGN_END1 register exist
284 * only if PAE exists in current HW. So we had to check pae_exist
287 if (slc_exists && pae_exists)
288 slc_upper_region_init();
289 #endif /* CONFIG_ISA_ARCV2 */
292 int icache_status(void)
297 if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
303 void icache_enable(void)
306 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
307 ~IC_CTRL_CACHE_DISABLE);
310 void icache_disable(void)
313 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
314 IC_CTRL_CACHE_DISABLE);
317 void invalidate_icache_all(void)
319 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
320 if (icache_status()) {
321 write_aux_reg(ARC_AUX_IC_IVIC, 1);
323 * As per ARC HS databook (see chapter 5.3.3.2)
324 * it is required to add 3 NOPs after each write to IC_IVIC.
329 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
332 #ifdef CONFIG_ISA_ARCV2
334 __slc_entire_op(OP_INV);
338 int dcache_status(void)
343 if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
349 void dcache_enable(void)
354 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
355 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
358 void dcache_disable(void)
363 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
364 DC_CTRL_CACHE_DISABLE);
367 #ifndef CONFIG_SYS_DCACHE_OFF
369 * Common Helper for Line Operations on {I,D}-Cache
371 static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
374 unsigned int aux_cmd;
375 #if (CONFIG_ARC_MMU_VER == 3)
376 unsigned int aux_tag;
380 if (cacheop == OP_INV_IC) {
381 aux_cmd = ARC_AUX_IC_IVIL;
382 #if (CONFIG_ARC_MMU_VER == 3)
383 aux_tag = ARC_AUX_IC_PTAG;
386 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
387 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
388 #if (CONFIG_ARC_MMU_VER == 3)
389 aux_tag = ARC_AUX_DC_PTAG;
393 sz += paddr & ~CACHE_LINE_MASK;
394 paddr &= CACHE_LINE_MASK;
396 num_lines = DIV_ROUND_UP(sz, l1_line_sz);
398 while (num_lines-- > 0) {
399 #if (CONFIG_ARC_MMU_VER == 3)
400 write_aux_reg(aux_tag, paddr);
402 write_aux_reg(aux_cmd, paddr);
407 static unsigned int __before_dc_op(const int op)
413 * IM is set by default and implies Flush-n-inv
414 * Clear it here for vanilla inv
416 reg = read_aux_reg(ARC_AUX_DC_CTRL);
417 write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
423 static void __after_dc_op(const int op, unsigned int reg)
425 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
426 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
429 /* Switch back to default Invalidate mode */
431 write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
434 static inline void __dc_entire_op(const int cacheop)
437 unsigned int ctrl_reg = __before_dc_op(cacheop);
439 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
440 aux = ARC_AUX_DC_IVDC;
442 aux = ARC_AUX_DC_FLSH;
444 write_aux_reg(aux, 0x1);
446 __after_dc_op(cacheop, ctrl_reg);
449 static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
452 unsigned int ctrl_reg = __before_dc_op(cacheop);
453 __cache_line_loop(paddr, sz, cacheop);
454 __after_dc_op(cacheop, ctrl_reg);
457 #define __dc_entire_op(cacheop)
458 #define __dc_line_op(paddr, sz, cacheop)
459 #endif /* !CONFIG_SYS_DCACHE_OFF */
461 void invalidate_dcache_range(unsigned long start, unsigned long end)
466 #ifdef CONFIG_ISA_ARCV2
469 __dc_line_op(start, end - start, OP_INV);
471 #ifdef CONFIG_ISA_ARCV2
472 if (slc_exists && !ioc_exists)
473 __slc_rgn_op(start, end - start, OP_INV);
477 void flush_dcache_range(unsigned long start, unsigned long end)
482 #ifdef CONFIG_ISA_ARCV2
485 __dc_line_op(start, end - start, OP_FLUSH);
487 #ifdef CONFIG_ISA_ARCV2
488 if (slc_exists && !ioc_exists)
489 __slc_rgn_op(start, end - start, OP_FLUSH);
493 void flush_cache(unsigned long start, unsigned long size)
495 flush_dcache_range(start, start + size);
498 void invalidate_dcache_all(void)
500 __dc_entire_op(OP_INV);
502 #ifdef CONFIG_ISA_ARCV2
504 __slc_entire_op(OP_INV);
508 void flush_dcache_all(void)
510 __dc_entire_op(OP_FLUSH);
512 #ifdef CONFIG_ISA_ARCV2
514 __slc_entire_op(OP_FLUSH);