2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm/arcregs.h>
11 /* Bit values in IC_CTRL */
12 #define IC_CTRL_CACHE_DISABLE (1 << 0)
14 /* Bit values in DC_CTRL */
15 #define DC_CTRL_CACHE_DISABLE (1 << 0)
16 #define DC_CTRL_INV_MODE_FLUSH (1 << 6)
17 #define DC_CTRL_FLUSH_STATUS (1 << 8)
18 #define CACHE_VER_NUM_MASK 0xF
20 int icache_status(void)
22 /* If no cache in CPU exit immediately */
23 if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
26 return (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE) !=
27 IC_CTRL_CACHE_DISABLE;
30 void icache_enable(void)
32 /* If no cache in CPU exit immediately */
33 if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
36 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
37 ~IC_CTRL_CACHE_DISABLE);
40 void icache_disable(void)
42 /* If no cache in CPU exit immediately */
43 if (!(read_aux_reg(ARC_BCR_IC_BUILD) & CACHE_VER_NUM_MASK))
46 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
47 IC_CTRL_CACHE_DISABLE);
50 void invalidate_icache_all(void)
52 #ifndef CONFIG_SYS_ICACHE_OFF
53 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
54 write_aux_reg(ARC_AUX_IC_IVIC, 1);
55 #endif /* CONFIG_SYS_ICACHE_OFF */
58 int dcache_status(void)
60 /* If no cache in CPU exit immediately */
61 if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
64 return (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE) !=
65 DC_CTRL_CACHE_DISABLE;
68 void dcache_enable(void)
70 /* If no cache in CPU exit immediately */
71 if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
74 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
75 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
78 void dcache_disable(void)
80 /* If no cache in CPU exit immediately */
81 if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
84 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
85 DC_CTRL_CACHE_DISABLE);
88 void flush_dcache_all(void)
90 /* If no cache in CPU exit immediately */
91 if (!(read_aux_reg(ARC_BCR_DC_BUILD) & CACHE_VER_NUM_MASK))
94 /* Do flush of entire cache */
95 write_aux_reg(ARC_AUX_DC_FLSH, 1);
98 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
102 #ifndef CONFIG_SYS_DCACHE_OFF
103 static void dcache_flush_line(unsigned addr)
105 #if (CONFIG_ARC_MMU_VER == 3)
106 write_aux_reg(ARC_AUX_DC_PTAG, addr);
108 write_aux_reg(ARC_AUX_DC_FLDL, addr);
111 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
114 #ifndef CONFIG_SYS_ICACHE_OFF
116 * Invalidate I$ for addresses range just flushed from D$.
117 * If we try to execute data flushed above it will be valid/correct
119 #if (CONFIG_ARC_MMU_VER == 3)
120 write_aux_reg(ARC_AUX_IC_PTAG, addr);
122 write_aux_reg(ARC_AUX_IC_IVIL, addr);
123 #endif /* CONFIG_SYS_ICACHE_OFF */
125 #endif /* CONFIG_SYS_DCACHE_OFF */
127 void flush_dcache_range(unsigned long start, unsigned long end)
129 #ifndef CONFIG_SYS_DCACHE_OFF
132 start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
133 end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
135 for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE)
136 dcache_flush_line(addr);
137 #endif /* CONFIG_SYS_DCACHE_OFF */
140 void invalidate_dcache_range(unsigned long start, unsigned long end)
142 #ifndef CONFIG_SYS_DCACHE_OFF
145 start = start & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
146 end = end & (~(CONFIG_SYS_CACHELINE_SIZE - 1));
148 for (addr = start; addr <= end; addr += CONFIG_SYS_CACHELINE_SIZE) {
149 #if (CONFIG_ARC_MMU_VER == 3)
150 write_aux_reg(ARC_AUX_DC_PTAG, addr);
152 write_aux_reg(ARC_AUX_DC_IVDL, addr);
154 #endif /* CONFIG_SYS_DCACHE_OFF */
157 void invalidate_dcache_all(void)
159 #ifndef CONFIG_SYS_DCACHE_OFF
160 /* Write 1 to DC_IVDC register triggers invalidation of entire D$ */
161 write_aux_reg(ARC_AUX_DC_IVDC, 1);
162 #endif /* CONFIG_SYS_DCACHE_OFF */
165 void flush_cache(unsigned long start, unsigned long size)
167 flush_dcache_range(start, start + size);