2 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
9 #include <linux/compiler.h>
10 #include <linux/kernel.h>
11 #include <asm/arcregs.h>
12 #include <asm/cache.h>
14 /* Bit values in IC_CTRL */
15 #define IC_CTRL_CACHE_DISABLE (1 << 0)
17 /* Bit values in DC_CTRL */
18 #define DC_CTRL_CACHE_DISABLE (1 << 0)
19 #define DC_CTRL_INV_MODE_FLUSH (1 << 6)
20 #define DC_CTRL_FLUSH_STATUS (1 << 8)
21 #define CACHE_VER_NUM_MASK 0xF
22 #define SLC_CTRL_SB (1 << 2)
29 * By default that variable will fall into .bss section.
30 * But .bss section is not relocated and so it will be initilized before
31 * relocation but will be used after being zeroed.
33 int l1_line_sz __section(".data");
34 int dcache_exists __section(".data");
35 int icache_exists __section(".data");
37 #define CACHE_LINE_MASK (~(l1_line_sz - 1))
39 #ifdef CONFIG_ISA_ARCV2
40 int slc_line_sz __section(".data");
41 int slc_exists __section(".data");
43 static unsigned int __before_slc_op(const int op)
45 unsigned int reg = reg;
49 * IM is set by default and implies Flush-n-inv
50 * Clear it here for vanilla inv
52 reg = read_aux_reg(ARC_AUX_SLC_CTRL);
53 write_aux_reg(ARC_AUX_SLC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
59 static void __after_slc_op(const int op, unsigned int reg)
61 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
62 while (read_aux_reg(ARC_AUX_SLC_CTRL) &
66 /* Switch back to default Invalidate mode */
68 write_aux_reg(ARC_AUX_SLC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
71 static inline void __slc_line_loop(unsigned long paddr, unsigned long sz,
77 #define SLC_LINE_MASK (~(slc_line_sz - 1))
79 aux_cmd = op & OP_INV ? ARC_AUX_SLC_IVDL : ARC_AUX_SLC_FLDL;
81 sz += paddr & ~SLC_LINE_MASK;
82 paddr &= SLC_LINE_MASK;
84 num_lines = DIV_ROUND_UP(sz, slc_line_sz);
86 while (num_lines-- > 0) {
87 write_aux_reg(aux_cmd, paddr);
92 static inline void __slc_entire_op(const int cacheop)
95 unsigned int ctrl_reg = __before_slc_op(cacheop);
97 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
98 aux = ARC_AUX_SLC_INVALIDATE;
100 aux = ARC_AUX_SLC_FLUSH;
102 write_aux_reg(aux, 0x1);
104 __after_slc_op(cacheop, ctrl_reg);
107 static inline void __slc_line_op(unsigned long paddr, unsigned long sz,
110 unsigned int ctrl_reg = __before_slc_op(cacheop);
111 __slc_line_loop(paddr, sz, cacheop);
112 __after_slc_op(cacheop, ctrl_reg);
115 #define __slc_entire_op(cacheop)
116 #define __slc_line_op(paddr, sz, cacheop)
119 #ifdef CONFIG_ISA_ARCV2
120 static void read_decode_cache_bcr_arcv2(void)
124 #ifdef CONFIG_CPU_BIG_ENDIAN
125 unsigned int pad:24, way:2, lsz:2, sz:4;
127 unsigned int sz:4, lsz:2, way:2, pad:24;
135 #ifdef CONFIG_CPU_BIG_ENDIAN
136 unsigned int pad:24, ver:8;
138 unsigned int ver:8, pad:24;
144 sbcr.word = read_aux_reg(ARC_BCR_SLC);
145 if (sbcr.fields.ver) {
146 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG);
148 slc_line_sz = (slc_cfg.fields.lsz == 0) ? 128 : 64;
153 void read_decode_cache_bcr(void)
155 int dc_line_sz = 0, ic_line_sz = 0;
159 #ifdef CONFIG_CPU_BIG_ENDIAN
160 unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
162 unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
168 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
169 if (ibcr.fields.ver) {
171 l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
173 panic("Instruction exists but line length is 0\n");
176 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD);
177 if (dbcr.fields.ver){
179 l1_line_sz = dc_line_sz = 16 << dbcr.fields.line_len;
181 panic("Data cache exists but line length is 0\n");
184 if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
185 panic("Instruction and data cache line lengths differ\n");
188 void cache_init(void)
190 read_decode_cache_bcr();
192 #ifdef CONFIG_ISA_ARCV2
193 read_decode_cache_bcr_arcv2();
197 int icache_status(void)
202 if (read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE)
208 void icache_enable(void)
211 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) &
212 ~IC_CTRL_CACHE_DISABLE);
215 void icache_disable(void)
218 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) |
219 IC_CTRL_CACHE_DISABLE);
222 #ifndef CONFIG_SYS_DCACHE_OFF
223 void invalidate_icache_all(void)
225 /* Any write to IC_IVIC register triggers invalidation of entire I$ */
226 if (icache_status()) {
227 write_aux_reg(ARC_AUX_IC_IVIC, 1);
228 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */
232 void invalidate_icache_all(void)
237 int dcache_status(void)
242 if (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE)
248 void dcache_enable(void)
253 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) &
254 ~(DC_CTRL_INV_MODE_FLUSH | DC_CTRL_CACHE_DISABLE));
257 void dcache_disable(void)
262 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) |
263 DC_CTRL_CACHE_DISABLE);
266 #ifndef CONFIG_SYS_DCACHE_OFF
268 * Common Helper for Line Operations on {I,D}-Cache
270 static inline void __cache_line_loop(unsigned long paddr, unsigned long sz,
273 unsigned int aux_cmd;
274 #if (CONFIG_ARC_MMU_VER == 3)
275 unsigned int aux_tag;
279 if (cacheop == OP_INV_IC) {
280 aux_cmd = ARC_AUX_IC_IVIL;
281 #if (CONFIG_ARC_MMU_VER == 3)
282 aux_tag = ARC_AUX_IC_PTAG;
285 /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */
286 aux_cmd = cacheop & OP_INV ? ARC_AUX_DC_IVDL : ARC_AUX_DC_FLDL;
287 #if (CONFIG_ARC_MMU_VER == 3)
288 aux_tag = ARC_AUX_DC_PTAG;
292 sz += paddr & ~CACHE_LINE_MASK;
293 paddr &= CACHE_LINE_MASK;
295 num_lines = DIV_ROUND_UP(sz, l1_line_sz);
297 while (num_lines-- > 0) {
298 #if (CONFIG_ARC_MMU_VER == 3)
299 write_aux_reg(aux_tag, paddr);
301 write_aux_reg(aux_cmd, paddr);
306 static unsigned int __before_dc_op(const int op)
312 * IM is set by default and implies Flush-n-inv
313 * Clear it here for vanilla inv
315 reg = read_aux_reg(ARC_AUX_DC_CTRL);
316 write_aux_reg(ARC_AUX_DC_CTRL, reg & ~DC_CTRL_INV_MODE_FLUSH);
322 static void __after_dc_op(const int op, unsigned int reg)
324 if (op & OP_FLUSH) /* flush / flush-n-inv both wait */
325 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS)
328 /* Switch back to default Invalidate mode */
330 write_aux_reg(ARC_AUX_DC_CTRL, reg | DC_CTRL_INV_MODE_FLUSH);
333 static inline void __dc_entire_op(const int cacheop)
336 unsigned int ctrl_reg = __before_dc_op(cacheop);
338 if (cacheop & OP_INV) /* Inv or flush-n-inv use same cmd reg */
339 aux = ARC_AUX_DC_IVDC;
341 aux = ARC_AUX_DC_FLSH;
343 write_aux_reg(aux, 0x1);
345 __after_dc_op(cacheop, ctrl_reg);
348 static inline void __dc_line_op(unsigned long paddr, unsigned long sz,
351 unsigned int ctrl_reg = __before_dc_op(cacheop);
352 __cache_line_loop(paddr, sz, cacheop);
353 __after_dc_op(cacheop, ctrl_reg);
356 #define __dc_entire_op(cacheop)
357 #define __dc_line_op(paddr, sz, cacheop)
358 #endif /* !CONFIG_SYS_DCACHE_OFF */
360 void invalidate_dcache_range(unsigned long start, unsigned long end)
362 __dc_line_op(start, end - start, OP_INV);
363 #ifdef CONFIG_ISA_ARCV2
365 __slc_line_op(start, end - start, OP_INV);
369 void flush_dcache_range(unsigned long start, unsigned long end)
371 __dc_line_op(start, end - start, OP_FLUSH);
372 #ifdef CONFIG_ISA_ARCV2
374 __slc_line_op(start, end - start, OP_FLUSH);
378 void flush_cache(unsigned long start, unsigned long size)
380 flush_dcache_range(start, start + size);
383 void invalidate_dcache_all(void)
385 __dc_entire_op(OP_INV);
386 #ifdef CONFIG_ISA_ARCV2
388 __slc_entire_op(OP_INV);
392 void flush_dcache_all(void)
394 __dc_entire_op(OP_FLUSH);
395 #ifdef CONFIG_ISA_ARCV2
397 __slc_entire_op(OP_FLUSH);