1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
6 #ifndef __ASM_ARC_CACHE_H
7 #define __ASM_ARC_CACHE_H
12 * As of today we may handle any L1 cache line length right in software.
13 * For that essentially cache line length is a variable not constant.
14 * And to satisfy users of ARCH_DMA_MINALIGN we just use largest line length
15 * that may exist in either L1 or L2 (AKA SLC) caches on ARC.
17 #define ARCH_DMA_MINALIGN 128
19 /* CONFIG_SYS_CACHELINE_SIZE is used a lot in drivers */
20 #define CONFIG_SYS_CACHELINE_SIZE ARCH_DMA_MINALIGN
22 #if defined(ARC_MMU_ABSENT)
23 #define CONFIG_ARC_MMU_VER 0
24 #elif defined(CONFIG_ARC_MMU_V2)
25 #define CONFIG_ARC_MMU_VER 2
26 #elif defined(CONFIG_ARC_MMU_V3)
27 #define CONFIG_ARC_MMU_VER 3
28 #elif defined(CONFIG_ARC_MMU_V4)
29 #define CONFIG_ARC_MMU_VER 4
34 void cache_init(void);
35 void flush_n_invalidate_dcache_all(void);
36 void sync_n_cleanup_cache_all(void);
38 static const inline int is_ioc_enabled(void)
40 return IS_ENABLED(CONFIG_ARC_DBG_IOC_ENABLE);
44 * We export SLC control functions to use them in platform configuration code.
45 * They maust not be used in any generic code!
47 void slc_enable(void);
48 void slc_disable(void);
50 #endif /* __ASSEMBLY__ */
52 #endif /* __ASM_ARC_CACHE_H */