2 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _ASM_ARC_ARCREGS_H
8 #define _ASM_ARC_ARCREGS_H
10 #include <asm/cache.h>
14 * ARC architecture has additional address space - auxiliary registers.
15 * These registers are mostly used for configuration purposes.
16 * These registers are not memory mapped and special commands are used for
20 #define ARC_AUX_IDENTITY 0x04
21 #define ARC_AUX_STATUS32 0x0a
23 /* Instruction cache related auxiliary registers */
24 #define ARC_AUX_IC_IVIC 0x10
25 #define ARC_AUX_IC_CTRL 0x11
26 #define ARC_AUX_IC_IVIL 0x19
27 #if (CONFIG_ARC_MMU_VER == 3)
28 #define ARC_AUX_IC_PTAG 0x1E
30 #define ARC_BCR_IC_BUILD 0x77
31 #define AUX_AUX_CACHE_LIMIT 0x5D
32 #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
34 /* ICCM and DCCM auxiliary registers */
35 #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
36 #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
38 /* Timer related auxiliary registers */
39 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
40 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
41 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
43 #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
44 #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
45 #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */
47 #define ARC_AUX_INTR_VEC_BASE 0x25
49 /* Data cache related auxiliary registers */
50 #define ARC_AUX_DC_IVDC 0x47
51 #define ARC_AUX_DC_CTRL 0x48
53 #define ARC_AUX_DC_IVDL 0x4A
54 #define ARC_AUX_DC_FLSH 0x4B
55 #define ARC_AUX_DC_FLDL 0x4C
56 #if (CONFIG_ARC_MMU_VER == 3)
57 #define ARC_AUX_DC_PTAG 0x5C
59 #define ARC_BCR_DC_BUILD 0x72
60 #define ARC_BCR_SLC 0xce
61 #define ARC_AUX_SLC_CONFIG 0x901
62 #define ARC_AUX_SLC_CTRL 0x903
63 #define ARC_AUX_SLC_FLUSH 0x904
64 #define ARC_AUX_SLC_INVALIDATE 0x905
65 #define ARC_AUX_SLC_IVDL 0x910
66 #define ARC_AUX_SLC_FLDL 0x912
67 #define ARC_AUX_SLC_RGN_START 0x914
68 #define ARC_AUX_SLC_RGN_START1 0x915
69 #define ARC_AUX_SLC_RGN_END 0x916
70 #define ARC_AUX_SLC_RGN_END1 0x917
71 #define ARC_BCR_CLUSTER 0xcf
73 /* MMU Management regs */
74 #define ARC_AUX_MMU_BCR 0x06f
76 /* IO coherency related auxiliary registers */
77 #define ARC_AUX_IO_COH_ENABLE 0x500
78 #define ARC_AUX_IO_COH_PARTIAL 0x501
79 #define ARC_AUX_IO_COH_AP0_BASE 0x508
80 #define ARC_AUX_IO_COH_AP0_SIZE 0x509
83 /* Accessors for auxiliary registers */
84 #define read_aux_reg(reg) __builtin_arc_lr(reg)
86 /* gcc builtin sr needs reg param to be long immediate */
87 #define write_aux_reg(reg_immed, val) \
88 __builtin_arc_sr((unsigned int)val, reg_immed)
90 /* ARCNUM [15:8] - field to identify each core in a multi-core system */
91 #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
93 static const inline int is_isa_arcv2(void)
95 return IS_ENABLED(CONFIG_ISA_ARCV2);
98 static const inline int is_isa_arcompact(void)
100 return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
102 #endif /* __ASSEMBLY__ */
104 #endif /* _ASM_ARC_ARCREGS_H */