1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. All rights reserved.
6 #ifndef _ASM_ARC_ARCREGS_H
7 #define _ASM_ARC_ARCREGS_H
13 * ARC architecture has additional address space - auxiliary registers.
14 * These registers are mostly used for configuration purposes.
15 * These registers are not memory mapped and special commands are used for
20 * Typically 8 least significant bits of Build Configuration Register (BCR)
21 * describe version of the HW block in question. Moreover if decoded version
22 * is 0 this means given HW block is absent - this is especially useful because
23 * we may safely read BRC regardless HW block existence while an attempt to
24 * access any other AUX regs associated with this HW block lead to imediate
25 * "instruction error" exception.
27 * I.e. before using any cofigurable HW block it's required to make sure it
28 * exists at all, and for that we introduce a special macro below.
30 #define ARC_BCR_VERSION_MASK GENMASK(7, 0)
31 #define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK)
33 #define ARC_AUX_IDENTITY 0x04
34 #define ARC_AUX_STATUS32 0x0a
36 /* STATUS32 Bits Positions */
37 #define STATUS_AD_BIT 19 /* Enable unaligned access */
39 /* Instruction cache related auxiliary registers */
40 #define ARC_AUX_IC_IVIC 0x10
41 #define ARC_AUX_IC_CTRL 0x11
42 #define ARC_AUX_IC_IVIL 0x19
43 #if (CONFIG_ARC_MMU_VER == 3)
44 #define ARC_AUX_IC_PTAG 0x1E
46 #define ARC_BCR_IC_BUILD 0x77
47 #define AUX_AUX_CACHE_LIMIT 0x5D
48 #define ARC_AUX_NON_VOLATILE_LIMIT 0x5E
50 /* ICCM and DCCM auxiliary registers */
51 #define ARC_AUX_DCCM_BASE 0x18 /* DCCM Base Addr ARCv2 */
52 #define ARC_AUX_ICCM_BASE 0x208 /* ICCM Base Addr ARCv2 */
54 /* CSM auxiliary registers */
55 #define ARC_AUX_CSM_ENABLE 0x9A0
57 /* Timer related auxiliary registers */
58 #define ARC_AUX_TIMER0_CNT 0x21 /* Timer 0 count */
59 #define ARC_AUX_TIMER0_CTRL 0x22 /* Timer 0 control */
60 #define ARC_AUX_TIMER0_LIMIT 0x23 /* Timer 0 limit */
62 #define ARC_AUX_TIMER1_CNT 0x100 /* Timer 1 count */
63 #define ARC_AUX_TIMER1_CTRL 0x101 /* Timer 1 control */
64 #define ARC_AUX_TIMER1_LIMIT 0x102 /* Timer 1 limit */
66 #define ARC_AUX_INTR_VEC_BASE 0x25
68 /* Data cache related auxiliary registers */
69 #define ARC_AUX_DC_IVDC 0x47
70 #define ARC_AUX_DC_CTRL 0x48
72 #define ARC_AUX_DC_IVDL 0x4A
73 #define ARC_AUX_DC_FLSH 0x4B
74 #define ARC_AUX_DC_FLDL 0x4C
75 #if (CONFIG_ARC_MMU_VER == 3)
76 #define ARC_AUX_DC_PTAG 0x5C
78 #define ARC_BCR_DC_BUILD 0x72
79 #define ARC_BCR_SLC 0xce
80 #define ARC_AUX_SLC_CONFIG 0x901
81 #define ARC_AUX_SLC_CTRL 0x903
82 #define ARC_AUX_SLC_FLUSH 0x904
83 #define ARC_AUX_SLC_INVALIDATE 0x905
84 #define ARC_AUX_SLC_IVDL 0x910
85 #define ARC_AUX_SLC_FLDL 0x912
86 #define ARC_AUX_SLC_RGN_START 0x914
87 #define ARC_AUX_SLC_RGN_START1 0x915
88 #define ARC_AUX_SLC_RGN_END 0x916
89 #define ARC_AUX_SLC_RGN_END1 0x917
90 #define ARC_BCR_CLUSTER 0xcf
92 /* MMU Management regs */
93 #define ARC_AUX_MMU_BCR 0x6f
95 /* IO coherency related auxiliary registers */
96 #define ARC_AUX_IO_COH_ENABLE 0x500
97 #define ARC_AUX_IO_COH_PARTIAL 0x501
98 #define ARC_AUX_IO_COH_AP0_BASE 0x508
99 #define ARC_AUX_IO_COH_AP0_SIZE 0x509
101 /* XY-memory related */
102 #define ARC_AUX_XY_BUILD 0x79
104 /* DSP-extensions related auxiliary registers */
105 #define ARC_AUX_DSP_BUILD 0x7A
106 #define ARC_AUX_DSP_CTRL 0x59F
108 /* ARC Subsystems related auxiliary registers */
109 #define ARC_AUX_SUBSYS_BUILD 0xF0
112 #include <linux/bitops.h>
114 /* Accessors for auxiliary registers */
115 #define read_aux_reg(reg) __builtin_arc_lr(reg)
117 /* gcc builtin sr needs reg param to be long immediate */
118 #define write_aux_reg(reg_immed, val) \
119 __builtin_arc_sr((unsigned int)val, reg_immed)
121 /* ARCNUM [15:8] - field to identify each core in a multi-core system */
122 #define CPU_ID_GET() ((read_aux_reg(ARC_AUX_IDENTITY) & 0xFF00) >> 8)
124 static const inline int is_isa_arcv2(void)
126 return IS_ENABLED(CONFIG_ISA_ARCV2);
129 static const inline int is_isa_arcompact(void)
131 return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
133 #endif /* __ASSEMBLY__ */
135 #endif /* _ASM_ARC_ARCREGS_H */