1 menu "ARC architecture"
8 default "arcv1" if ISA_ARCOMPACT
9 default "arcv2" if ISA_ARCV2
12 prompt "ARC Instruction Set"
18 The original ARC ISA of ARC600/700 cores
23 ISA for the Next Generation ARC-HS cores
28 prompt "CPU selection"
29 default CPU_ARC770D if ISA_ARCOMPACT
30 default CPU_ARCHS38 if ISA_ARCV2
35 depends on ISA_ARCOMPACT
37 Choose this option to build an U-Boot for ARC750D CPU.
42 depends on ISA_ARCOMPACT
44 Choose this option to build an U-Boot for ARC770D CPU.
51 Next Generation ARC Core based on ISA-v2 ISA without MMU.
58 Next Generation ARC Core based on ISA-v2 ISA without MMU.
65 Next Generation ARC Core based on ISA-v2 ISA with MMU.
71 default ARC_MMU_V3 if CPU_ARC770D
72 default ARC_MMU_V2 if CPU_ARC750D
73 default ARC_MMU_ABSENT if CPU_ARCEM6
74 default ARC_MMU_ABSENT if CPU_ARCHS36
75 default ARC_MMU_V4 if CPU_ARCHS38
84 depends on CPU_ARC750D
86 Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
87 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
91 depends on CPU_ARC770D
93 Introduced with ARC700 4.10: New Features
94 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
95 Shared Address Spaces (SASID)
99 depends on CPU_ARCHS38
101 Introduced as a part of ARC HS38 release.
105 config CPU_BIG_ENDIAN
106 bool "Enable Big Endian Mode"
109 Build kernel for Big Endian Mode of ARC CPU
111 config SYS_ICACHE_OFF
112 bool "Do not use Instruction Cache"
115 config SYS_DCACHE_OFF
116 bool "Do not use Data Cache"
120 prompt "Target select"
121 default TARGET_AXS10X
127 bool "Support standalone nSIM & Free nSIM"
130 bool "Support Synopsys Designware SDP board (AXS101 & AXS103)"
134 source "board/abilis/tb100/Kconfig"
135 source "board/synopsys/Kconfig"
136 source "board/synopsys/axs10x/Kconfig"