1 /* SPDX-License-Identifier: GPL-2.0 */
3 * arch/alpha/lib/ev6-copy_page.S
8 /* The following comparison of this routine vs the normal copy_page.S
9 was written by an unnamed ev6 hardware designer and forwarded to me
10 via Steven Hobbs <hobbs@steven.zko.dec.com>.
12 First Problem: STQ overflows.
13 -----------------------------
15 It would be nice if EV6 handled every resource overflow efficiently,
16 but for some it doesn't. Including store queue overflows. It causes
17 a trap and a restart of the pipe.
19 To get around this we sometimes use (to borrow a term from a VSSAD
20 researcher) "aeration". The idea is to slow the rate at which the
21 processor receives valid instructions by inserting nops in the fetch
22 path. In doing so, you can prevent the overflow and actually make
23 the code run faster. You can, of course, take advantage of the fact
24 that the processor can fetch at most 4 aligned instructions per cycle.
26 I inserted enough nops to force it to take 10 cycles to fetch the
27 loop code. In theory, EV6 should be able to execute this loop in
28 9 cycles but I was not able to get it to run that fast -- the initial
29 conditions were such that I could not reach this optimum rate on
30 (chaotic) EV6. I wrote the code such that everything would issue
33 Second Problem: Dcache index matches.
34 -------------------------------------
36 If you are going to use this routine on random aligned pages, there
37 is a 25% chance that the pages will be at the same dcache indices.
38 This results in many nasty memory traps without care.
40 The solution is to schedule the prefetches to avoid the memory
41 conflicts. I schedule the wh64 prefetches farther ahead of the
42 read prefetches to avoid this problem.
44 Third Problem: Needs more prefetching.
45 --------------------------------------
47 In order to improve the code I added deeper prefetching to take the
48 most advantage of EV6's bandwidth.
50 I also prefetched the read stream. Note that adding the read prefetch
51 forced me to add another cycle to the inner-most kernel - up to 11
52 from the original 8 cycles per iteration. We could improve performance
53 further by unrolling the loop and doing multiple prefetches per cycle.
55 I think that the code below will be very robust and fast code for the
56 purposes of copying aligned pages. It is slower when both source and
57 destination pages are in the dcache, but it is my guess that this is
58 less important than the dcache miss case. */
60 #include <asm/export.h>
68 /* Prefetch 5 read cachelines; write-hint 10 cache lines. */
104 /* Main prefetching/write-hinting loop. */
130 /* This gives the extra cycle of aeration above the minimum. */
161 /* Prefetch the final 5 cache lines of the read stream. */
172 /* Non-prefetching, non-write-hinting cleanup loop for the
173 final 10 cache lines. */
205 EXPORT_SYMBOL(copy_page)