2 bool "NXP ESBC (secure boot) functionality"
4 Enable Freescale Secure Boot feature. Normally selected by defconfig.
5 If unsure, do not change.
7 menu "Chain of trust / secure boot options"
8 depends on !FIT_SIGNATURE && NXP_ESBC
14 select SPL_BOARD_INIT if (ARM && SPL)
15 select SPL_HASH if (ARM && SPL)
17 select SHA_PROG_HW_ACCEL
19 select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
20 select CMD_EXT4 if ARM
21 select CMD_EXT4_WRITE if ARM
26 config CMD_ESBC_VALIDATE
27 bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
30 This option enables two commands used for secure booting:
32 esbc_validate - validate signature using RSA verification
33 esbc_halt - put the core in spin loop (Secure Boot Only)
38 config ESBC_ADDR_64BIT
40 depends on ESBC_HDR_LS && FSL_LAYERSCAPE
42 For Layerscape based platforms, ESBC image Address in Header is 64bit.
46 depends on PPC || FSL_LSCH2 || ARCH_LS1021A
50 depends on !SYS_FSL_SFP_BE
53 prompt "SFP IP revision"
54 default SYS_FSL_SFP_VER_3_0 if PPC
55 default SYS_FSL_SFP_VER_3_4
57 config SYS_FSL_SFP_VER_3_0
58 bool "SFP version 3.0"
60 config SYS_FSL_SFP_VER_3_2
61 bool "SFP version 3.2"
63 config SYS_FSL_SFP_VER_3_4
64 bool "SFP version 3.4"
68 config SPL_UBOOT_KEY_HASH
69 string "Non-SRK key hash for U-Boot public/private key pair"
73 Set the key hash for U-Boot here if public/private key pair used to
74 sign U-boot are different from the SRK hash put in the fuse. Example
76 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
77 Otherwise leave this empty.
81 config BOOTSCRIPT_COPY_RAM
82 bool "Secure boot copies boot script to RAM"
84 On systems that support chain of trust booting, a number of addresses
85 are required to set variables that are used in the copying and then
86 verification of different parts of the system. If enabled, the subsequent
87 options are for what location to use in each step.
90 hex "Address in RAM for bs_device"
91 depends on BOOTSCRIPT_COPY_RAM
94 hex "The size of bs_size which is the amount read from bs_device"
95 depends on BOOTSCRIPT_COPY_RAM
98 hex "Address in RAM for bs_ram"
99 depends on BOOTSCRIPT_COPY_RAM
101 config BS_HDR_ADDR_DEVICE
102 hex "Address in RAM for bs_hdr_device"
103 depends on BOOTSCRIPT_COPY_RAM
106 hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
107 depends on BOOTSCRIPT_COPY_RAM
109 config BS_HDR_ADDR_RAM
110 hex "Address in RAM for bs_hdr_ram"
111 depends on BOOTSCRIPT_COPY_RAM
113 config BOOTSCRIPT_HDR_ADDR
114 hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
115 default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
119 config SYS_FSL_SRK_LE
123 config KEY_REVOCATION
128 comment "Other functionality shared between NXP SoCs"
131 bool "Enable SoC deep sleep feature"
132 depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
135 Indicates this SoC supports deep sleep feature. If deep sleep is
136 supported, core will start to execute uboot when wakes up.
138 config LAYERSCAPE_NS_ACCESS
139 bool "Layerscape non-secure access support"
140 depends on ARCH_LS1021A || FSL_LSCH2
143 bool "PCIe controller #1"
144 depends on LAYERSCAPE_NS_ACCESS || PPC
147 bool "PCIe controller #2"
148 depends on LAYERSCAPE_NS_ACCESS || PPC
151 bool "PCIe controller #3"
152 depends on LAYERSCAPE_NS_ACCESS || PPC
155 bool "PCIe controller #4"
156 depends on LAYERSCAPE_NS_ACCESS || PPC
158 config FSL_USE_PCA9547_MUX
159 bool "Enable PCA9547 I2C Mux on Freescale boards"
160 depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
162 This option enables the PCA9547 I2C mux on Freescale boards.
165 bool "Enable Freescale VID"
166 depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (I2C || DM_I2C)
168 This option enables setting core voltage based on individual
169 values saved in SoC fuses.
172 bool "Enable Freescale VID in SPL"
173 depends on (PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3) && (SPL_I2C || DM_SPL_I2C)
175 This option enables setting core voltage based on individual
176 values saved in SoC fuses, in SPL.
181 string "Environment variable for overriding VDD"
183 This option allows for specifying the environment variable
184 to check to override VDD information.
186 config VOL_MONITOR_INA220
187 bool "Enable the INA220 voltage monitor read"
189 This option enables INA220 voltage monitor read
190 functionality. It is used by the common VID driver.
192 config VOL_MONITOR_IR36021_READ
193 bool "Enable the IR36021 voltage monitor read"
195 This option enables IR36021 voltage monitor read
196 functionality. It is used by the common VID driver.
198 config VOL_MONITOR_IR36021_SET
199 bool "Enable the IR36021 voltage monitor set"
201 This option enables IR36021 voltage monitor set
202 functionality. It is used by the common VID driver.
204 config VOL_MONITOR_LTC3882_READ
205 bool "Enable the LTC3882 voltage monitor read"
207 This option enables LTC3882 voltage monitor read
208 functionality. It is used by the common VID driver.
210 config VOL_MONITOR_LTC3882_SET
211 bool "Enable the LTC3882 voltage monitor set"
213 This option enables LTC3882 voltage monitor set
214 functionality. It is used by the common VID driver.
216 config VOL_MONITOR_ISL68233_READ
217 bool "Enable the ISL68233 voltage monitor read"
219 This option enables ISL68233 voltage monitor read
220 functionality. It is used by the common VID driver.
222 config VOL_MONITOR_ISL68233_SET
223 bool "Enable the ISL68233 voltage monitor set"
225 This option enables ISL68233 voltage monitor set
226 functionality. It is used by the common VID driver.
230 config SYS_FSL_NUM_CC_PLLS
231 int "Number of clock control PLLs"
232 depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
233 default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
234 default 6 if FSL_LSCH3 || MPC85xx
236 config SYS_FSL_ESDHC_BE
239 config SYS_FSL_IFC_BE
243 bool "Enable QIXIS support"
244 depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
246 config QIXIS_I2C_ACCESS
247 bool "Access to QIXIS is over i2c"
251 config HAS_FSL_DR_USB
253 depends on USB_EHCI_HCD && PPC