2 depends on SANDBOX || NDS32
5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config NEEDS_MANUAL_RELOC
14 config SYS_CACHE_SHIFT_4
17 config SYS_CACHE_SHIFT_5
20 config SYS_CACHE_SHIFT_6
23 config SYS_CACHE_SHIFT_7
26 config SYS_CACHELINE_SIZE
28 default 128 if SYS_CACHE_SHIFT_7
29 default 64 if SYS_CACHE_SHIFT_6
30 default 32 if SYS_CACHE_SHIFT_5
31 default 16 if SYS_CACHE_SHIFT_4
35 config LINKER_LIST_ALIGN
38 default 8 if ARM64 || X86
41 Force the each linker list to be aligned to this boundary. This
42 is required if ll_entry_get() is used, since otherwise the linker
43 may add padding into the table, thus breaking it.
44 See linker_lists.rst for full details.
47 prompt "Architecture select"
51 bool "ARC architecture"
55 select HAVE_PRIVATE_LIBGCC
56 select SUPPORT_OF_CONTROL
57 select SYS_CACHE_SHIFT_7
61 bool "ARM architecture"
62 select ARCH_SUPPORTS_LTO
63 select CREATE_ARCH_SYMLINK
64 select HAVE_PRIVATE_LIBGCC if !ARM64
65 select SUPPORT_OF_CONTROL
68 bool "M68000 architecture"
69 select HAVE_PRIVATE_LIBGCC
70 select NEEDS_MANUAL_RELOC
71 select SYS_BOOT_GET_CMDLINE
72 select SYS_BOOT_GET_KBD
73 select SYS_CACHE_SHIFT_4
74 select SUPPORT_OF_CONTROL
77 bool "MicroBlaze architecture"
78 select NEEDS_MANUAL_RELOC
79 select SUPPORT_OF_CONTROL
83 bool "MIPS architecture"
84 select HAVE_ARCH_IOREMAP
85 select HAVE_PRIVATE_LIBGCC
86 select SUPPORT_OF_CONTROL
89 bool "NDS32 architecture"
90 select SUPPORT_OF_CONTROL
93 bool "Nios II architecture"
97 select SUPPORT_OF_CONTROL
101 bool "PowerPC architecture"
102 select HAVE_PRIVATE_LIBGCC
103 select SUPPORT_OF_CONTROL
104 select SYS_BOOT_GET_CMDLINE
105 select SYS_BOOT_GET_KBD
108 bool "RISC-V architecture"
109 select CREATE_ARCH_SYMLINK
110 select SUPPORT_OF_CONTROL
125 imply SPL_LIBCOMMON_SUPPORT
126 imply SPL_LIBGENERIC_SUPPORT
132 select ARCH_SUPPORTS_LTO
133 select BOARD_LATE_INIT
144 select GZIP_COMPRESSED
145 select HAVE_BLOCK_DEVICE
147 select OF_BOARD_SETUP
150 select SUPPORT_OF_CONTROL
151 select SYSRESET_CMD_POWEROFF
152 select SYS_CACHE_SHIFT_4
154 select SUPPORT_EXTENSION_SCAN
180 imply UDP_FUNCTION_FASTBOOT
193 imply ACPI_PMC_SANDBOX
205 bool "SuperH architecture"
206 select HAVE_PRIVATE_LIBGCC
207 select SUPPORT_OF_CONTROL
210 bool "x86 architecture"
213 select CREATE_ARCH_SYMLINK
215 select HAVE_ARCH_IOMAP
216 select HAVE_PRIVATE_LIBGCC
219 select SUPPORT_OF_CONTROL
220 select SYS_CACHE_SHIFT_6
222 select USE_PRIVATE_LIBGCC
225 imply HAS_ROM if X86_RESET_VECTOR
228 imply CMD_FPGA_LOADMK
251 imply USB_ETHER_SMSC95XX
256 imply ACPIGEN if !QEMU
257 imply SYSINFO if GENERATE_SMBIOS_TABLE
258 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
261 # Thing to enable for when SPL/TPL are enabled: SPL
264 imply SPL_DRIVERS_MISC
267 imply SPL_LIBCOMMON_SUPPORT
268 imply SPL_LIBGENERIC_SUPPORT
270 imply SPL_SPI_FLASH_SUPPORT
278 imply TPL_DRIVERS_MISC
281 imply TPL_LIBCOMMON_SUPPORT
282 imply TPL_LIBGENERIC_SUPPORT
290 bool "Xtensa architecture"
291 select CREATE_ARCH_SYMLINK
292 select SUPPORT_OF_CONTROL
299 This option should contain the architecture name to build the
300 appropriate arch/<CONFIG_SYS_ARCH> directory.
301 All the architectures should specify this option correctly.
306 This option should contain the CPU name to build the correct
307 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
309 This is optional. For those targets without the CPU directory,
310 leave this option empty.
315 This option should contain the SoC name to build the directory
316 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
318 This is optional. For those targets without the SoC directory,
319 leave this option empty.
324 This option should contain the vendor name of the target board.
326 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
327 directory is compiled.
328 If CONFIG_SYS_BOARD is also set, the sources under
329 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
331 This is optional. For those targets without the vendor directory,
332 leave this option empty.
337 This option should contain the name of the target board.
338 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
339 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
340 whether CONFIG_SYS_VENDOR is set or not.
342 This is optional. For those targets without the board directory,
343 leave this option empty.
345 config SYS_CONFIG_NAME
348 This option should contain the base name of board header file.
349 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
350 should be included from include/config.h.
352 config SYS_DISABLE_DCACHE_OPS
355 This option disables dcache flush and dcache invalidation
356 operations. For example, on coherent systems where cache
357 operatios are not required, enable this option to avoid them.
358 Note that, its up to the individual architectures to implement
363 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
364 default 0xFF000000 if MPC8xx
365 default 0xF0000000 if ARCH_MPC8313
366 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
367 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
368 default SYS_CCSRBAR_DEFAULT
370 Address for the Internal Memory-Mapped Registers (IMMR) window used
371 to configure the features of many Freescale / NXP SoCs.
373 config SKIP_LOWLEVEL_INIT
374 bool "Skip the calls to certain low level initialization functions"
375 depends on ARM || NDS32 || MIPS || RISCV
377 If enabled, then certain low level initializations (like setting up
378 the memory controller) are omitted and/or U-Boot does not relocate
380 Normally this variable MUST NOT be defined. The only exception is
381 when U-Boot is loaded (to RAM) by some other boot loader or by a
382 debugger which performs these initializations itself.
384 config SPL_SKIP_LOWLEVEL_INIT
385 bool "Skip the calls to certain low level initialization functions"
386 depends on SPL && (ARM || NDS32 || MIPS || RISCV)
388 If enabled, then certain low level initializations (like setting up
389 the memory controller) are omitted and/or U-Boot does not relocate
391 Normally this variable MUST NOT be defined. The only exception is
392 when U-Boot is loaded (to RAM) by some other boot loader or by a
393 debugger which performs these initializations itself.
395 config TPL_SKIP_LOWLEVEL_INIT
396 bool "Skip the calls to certain low level initialization functions"
397 depends on SPL && ARM
399 If enabled, then certain low level initializations (like setting up
400 the memory controller) are omitted and/or U-Boot does not relocate
402 Normally this variable MUST NOT be defined. The only exception is
403 when U-Boot is loaded (to RAM) by some other boot loader or by a
404 debugger which performs these initializations itself.
406 config SKIP_LOWLEVEL_INIT_ONLY
407 bool "Skip the call to lowlevel_init during early boot ONLY"
410 This allows just the call to lowlevel_init() to be skipped. The
411 normal CP15 init (such as enabling the instruction cache) is still
414 config SPL_SKIP_LOWLEVEL_INIT_ONLY
415 bool "Skip the call to lowlevel_init during early boot ONLY"
416 depends on SPL && ARM
418 This allows just the call to lowlevel_init() to be skipped. The
419 normal CP15 init (such as enabling the instruction cache) is still
422 config TPL_SKIP_LOWLEVEL_INIT_ONLY
423 bool "Skip the call to lowlevel_init during early boot ONLY"
424 depends on TPL && ARM
426 This allows just the call to lowlevel_init() to be skipped. The
427 normal CP15 init (such as enabling the instruction cache) is still
430 source "arch/arc/Kconfig"
431 source "arch/arm/Kconfig"
432 source "arch/m68k/Kconfig"
433 source "arch/microblaze/Kconfig"
434 source "arch/mips/Kconfig"
435 source "arch/nds32/Kconfig"
436 source "arch/nios2/Kconfig"
437 source "arch/powerpc/Kconfig"
438 source "arch/sandbox/Kconfig"
439 source "arch/sh/Kconfig"
440 source "arch/x86/Kconfig"
441 source "arch/xtensa/Kconfig"
442 source "arch/riscv/Kconfig"