5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config SYS_CACHE_SHIFT_4
14 config SYS_CACHE_SHIFT_5
17 config SYS_CACHE_SHIFT_6
20 config SYS_CACHE_SHIFT_7
23 config SYS_CACHELINE_SIZE
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
32 config LINKER_LIST_ALIGN
35 default 8 if ARM64 || X86
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
44 prompt "Architecture select"
48 bool "ARC architecture"
52 select HAVE_PRIVATE_LIBGCC
53 select SUPPORT_OF_CONTROL
54 select SYS_CACHE_SHIFT_7
56 select SYS_BIG_ENDIAN if CPU_BIG_ENDIAN
57 select SYS_LITTLE_ENDIAN if !CPU_BIG_ENDIAN
60 bool "ARM architecture"
61 select ARCH_SUPPORTS_LTO
62 select CREATE_ARCH_SYMLINK
63 select HAVE_PRIVATE_LIBGCC if !ARM64
65 select SUPPORT_OF_CONTROL
68 bool "M68000 architecture"
69 select HAVE_PRIVATE_LIBGCC
70 select NEEDS_MANUAL_RELOC
71 select SYS_BOOT_GET_CMDLINE
72 select SYS_BOOT_GET_KBD
73 select SYS_CACHE_SHIFT_4
74 select SUPPORT_OF_CONTROL
77 bool "MicroBlaze architecture"
78 select SUPPORT_OF_CONTROL
80 imply SPL_REGMAP if SPL
81 imply SPL_TIMER if SPL
86 bool "MIPS architecture"
87 select HAVE_ARCH_IOREMAP
88 select HAVE_PRIVATE_LIBGCC
89 select SUPPORT_OF_CONTROL
90 select SPL_SEPARATE_BSS if SPL
93 bool "Nios II architecture"
98 select SUPPORT_OF_CONTROL
102 bool "PowerPC architecture"
103 select HAVE_PRIVATE_LIBGCC
104 select SUPPORT_OF_CONTROL
105 select SYS_BOOT_GET_CMDLINE
106 select SYS_BOOT_GET_KBD
109 bool "RISC-V architecture"
110 select CREATE_ARCH_SYMLINK
111 select SUPPORT_OF_CONTROL
114 select SPL_SEPARATE_BSS if SPL
128 imply SPL_LIBCOMMON_SUPPORT
129 imply SPL_LIBGENERIC_SUPPORT
135 select ARCH_SUPPORTS_LTO
136 select BOARD_LATE_INIT
140 select DM_FUZZING_ENGINE
148 select GZIP_COMPRESSED
151 select OF_BOARD_SETUP
154 select SUPPORT_OF_CONTROL
155 select SYSRESET_CMD_POWEROFF
156 select SYS_CACHE_SHIFT_4
158 select SUPPORT_EXTENSION_SCAN
175 imply FUZZING_ENGINE_SANDBOX
182 imply PARTITION_TYPE_GUID
185 imply UDP_FUNCTION_FASTBOOT
198 imply ACPI_PMC_SANDBOX
208 imply GENERATE_ACPI_TABLE
212 bool "SuperH architecture"
213 select HAVE_PRIVATE_LIBGCC
214 select SUPPORT_OF_CONTROL
217 bool "x86 architecture"
220 select CREATE_ARCH_SYMLINK
222 select HAVE_ARCH_IOMAP
223 select HAVE_PRIVATE_LIBGCC
227 select SUPPORT_OF_CONTROL
228 select SYS_CACHE_SHIFT_6
230 select USE_PRIVATE_LIBGCC
233 imply HAS_ROM if X86_RESET_VECTOR
236 imply CMD_FPGA_LOADMK
260 imply USB_ETHER_SMSC95XX
265 imply ACPIGEN if !QEMU && !EFI_APP
266 imply SYSINFO if GENERATE_SMBIOS_TABLE
267 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
270 # Thing to enable for when SPL/TPL are enabled: SPL
273 imply SPL_DRIVERS_MISC
276 imply SPL_LIBCOMMON_SUPPORT
277 imply SPL_LIBGENERIC_SUPPORT
279 imply SPL_SPI_FLASH_SUPPORT
287 imply TPL_DRIVERS_MISC
290 imply TPL_LIBCOMMON_SUPPORT
291 imply TPL_LIBGENERIC_SUPPORT
299 bool "Xtensa architecture"
300 select CREATE_ARCH_SYMLINK
301 select SUPPORT_OF_CONTROL
308 This option should contain the architecture name to build the
309 appropriate arch/<CONFIG_SYS_ARCH> directory.
310 All the architectures should specify this option correctly.
315 This option should contain the CPU name to build the correct
316 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
318 This is optional. For those targets without the CPU directory,
319 leave this option empty.
324 This option should contain the SoC name to build the directory
325 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
327 This is optional. For those targets without the SoC directory,
328 leave this option empty.
333 This option should contain the vendor name of the target board.
335 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
336 directory is compiled.
337 If CONFIG_SYS_BOARD is also set, the sources under
338 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
340 This is optional. For those targets without the vendor directory,
341 leave this option empty.
346 This option should contain the name of the target board.
347 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
348 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
349 whether CONFIG_SYS_VENDOR is set or not.
351 This is optional. For those targets without the board directory,
352 leave this option empty.
354 config SYS_CONFIG_NAME
357 This option should contain the base name of board header file.
358 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
359 should be included from include/config.h.
361 config SYS_DISABLE_DCACHE_OPS
364 This option disables dcache flush and dcache invalidation
365 operations. For example, on coherent systems where cache
366 operatios are not required, enable this option to avoid them.
367 Note that, its up to the individual architectures to implement
371 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
372 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
373 default 0xFF000000 if MPC8xx
374 default 0xF0000000 if ARCH_MPC8313
375 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
376 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
377 default 0xFFE00000 if ARCH_P1010 || ARCH_P1011 || ARCH_P1020 || \
378 ARCH_P1021 || ARCH_P1024 || ARCH_P1025 || \
380 default SYS_CCSRBAR_DEFAULT
382 Address for the Internal Memory-Mapped Registers (IMMR) window used
383 to configure the features of many Freescale / NXP SoCs.
385 config SKIP_LOWLEVEL_INIT
386 bool "Skip the calls to certain low level initialization functions"
387 depends on ARM || MIPS || RISCV
389 If enabled, then certain low level initializations (like setting up
390 the memory controller) are omitted and/or U-Boot does not relocate
392 Normally this variable MUST NOT be defined. The only exception is
393 when U-Boot is loaded (to RAM) by some other boot loader or by a
394 debugger which performs these initializations itself.
396 config SPL_SKIP_LOWLEVEL_INIT
397 bool "Skip the calls to certain low level initialization functions"
398 depends on SPL && (ARM || MIPS || RISCV)
400 If enabled, then certain low level initializations (like setting up
401 the memory controller) are omitted and/or U-Boot does not relocate
403 Normally this variable MUST NOT be defined. The only exception is
404 when U-Boot is loaded (to RAM) by some other boot loader or by a
405 debugger which performs these initializations itself.
407 config TPL_SKIP_LOWLEVEL_INIT
408 bool "Skip the calls to certain low level initialization functions"
409 depends on SPL && ARM
411 If enabled, then certain low level initializations (like setting up
412 the memory controller) are omitted and/or U-Boot does not relocate
414 Normally this variable MUST NOT be defined. The only exception is
415 when U-Boot is loaded (to RAM) by some other boot loader or by a
416 debugger which performs these initializations itself.
418 config SKIP_LOWLEVEL_INIT_ONLY
419 bool "Skip the call to lowlevel_init during early boot ONLY"
422 This allows just the call to lowlevel_init() to be skipped. The
423 normal CP15 init (such as enabling the instruction cache) is still
426 config SPL_SKIP_LOWLEVEL_INIT_ONLY
427 bool "Skip the call to lowlevel_init during early boot ONLY"
428 depends on SPL && ARM
430 This allows just the call to lowlevel_init() to be skipped. The
431 normal CP15 init (such as enabling the instruction cache) is still
434 config TPL_SKIP_LOWLEVEL_INIT_ONLY
435 bool "Skip the call to lowlevel_init during early boot ONLY"
436 depends on TPL && ARM
438 This allows just the call to lowlevel_init() to be skipped. The
439 normal CP15 init (such as enabling the instruction cache) is still
442 config SYS_HAS_NONCACHED_MEMORY
443 bool "Enable reserving a non-cached memory area for drivers"
444 depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
446 This is useful for drivers that would otherwise require a lot of
447 explicit cache maintenance. For some drivers it's also impossible to
448 properly maintain the cache. For example if the regions that need to
449 be flushed are not a multiple of the cache-line size, *and* padding
450 cannot be allocated between the regions to align them (i.e. if the
451 HW requires a contiguous array of regions, and the size of each
452 region is not cache-aligned), then a flush of one region may result
453 in overwriting data that hardware has written to another region in
454 the same cache-line. This can happen for example in network drivers
455 where descriptors for buffers are typically smaller than the CPU
456 cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
458 config SYS_NONCACHED_MEMORY
459 hex "Size in bytes of the non-cached memory area"
460 depends on SYS_HAS_NONCACHED_MEMORY
463 Size of non-cached memory area. This area of memory will be typically
464 located right below the malloc() area and mapped uncached in the MMU.
466 source "arch/arc/Kconfig"
467 source "arch/arm/Kconfig"
468 source "arch/m68k/Kconfig"
469 source "arch/microblaze/Kconfig"
470 source "arch/mips/Kconfig"
471 source "arch/nios2/Kconfig"
472 source "arch/powerpc/Kconfig"
473 source "arch/sandbox/Kconfig"
474 source "arch/sh/Kconfig"
475 source "arch/x86/Kconfig"
476 source "arch/xtensa/Kconfig"
477 source "arch/riscv/Kconfig"
479 if ARM || M68K || PPC
481 source "arch/Kconfig.nxp"
485 source "board/keymile/Kconfig"
487 if MIPS || MICROBLAZE
490 prompt "Endianness selection"
492 Some MIPS boards can be configured for either little or big endian
493 byte order. These modes require different U-Boot images. In general there
494 is one preferred byteorder for a particular system but some systems are
495 just as commonly used in the one or the other endianness.
497 config SYS_BIG_ENDIAN
499 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
501 config SYS_LITTLE_ENDIAN
503 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE