1 config CREATE_ARCH_SYMLINK
4 config HAVE_ARCH_IOREMAP
7 config NEEDS_MANUAL_RELOC
10 config SYS_CACHE_SHIFT_4
13 config SYS_CACHE_SHIFT_5
16 config SYS_CACHE_SHIFT_6
19 config SYS_CACHE_SHIFT_7
22 config SYS_CACHELINE_SIZE
24 default 128 if SYS_CACHE_SHIFT_7
25 default 64 if SYS_CACHE_SHIFT_6
26 default 32 if SYS_CACHE_SHIFT_5
27 default 16 if SYS_CACHE_SHIFT_4
31 config LINKER_LIST_ALIGN
34 default 8 if ARM64 || X86
37 Force the each linker list to be aligned to this boundary. This
38 is required if ll_entry_get() is used, since otherwise the linker
39 may add padding into the table, thus breaking it.
40 See linker_lists.rst for full details.
43 prompt "Architecture select"
47 bool "ARC architecture"
51 select HAVE_PRIVATE_LIBGCC
52 select SUPPORT_OF_CONTROL
53 select SYS_CACHE_SHIFT_7
57 bool "ARM architecture"
58 select ARCH_SUPPORTS_LTO
59 select CREATE_ARCH_SYMLINK
60 select HAVE_PRIVATE_LIBGCC if !ARM64
61 select SUPPORT_OF_CONTROL
64 bool "M68000 architecture"
65 select HAVE_PRIVATE_LIBGCC
66 select NEEDS_MANUAL_RELOC
67 select SYS_BOOT_GET_CMDLINE
68 select SYS_BOOT_GET_KBD
69 select SYS_CACHE_SHIFT_4
70 select SUPPORT_OF_CONTROL
73 bool "MicroBlaze architecture"
74 select NEEDS_MANUAL_RELOC
75 select SUPPORT_OF_CONTROL
79 bool "MIPS architecture"
80 select HAVE_ARCH_IOREMAP
81 select HAVE_PRIVATE_LIBGCC
82 select SUPPORT_OF_CONTROL
85 bool "NDS32 architecture"
86 select SUPPORT_OF_CONTROL
89 bool "Nios II architecture"
93 select SUPPORT_OF_CONTROL
97 bool "PowerPC architecture"
98 select HAVE_PRIVATE_LIBGCC
99 select SUPPORT_OF_CONTROL
100 select SYS_BOOT_GET_CMDLINE
101 select SYS_BOOT_GET_KBD
104 bool "RISC-V architecture"
105 select CREATE_ARCH_SYMLINK
106 select SUPPORT_OF_CONTROL
121 imply SPL_LIBCOMMON_SUPPORT
122 imply SPL_LIBGENERIC_SUPPORT
128 select ARCH_SUPPORTS_LTO
129 select BOARD_LATE_INIT
140 select GZIP_COMPRESSED
141 select HAVE_BLOCK_DEVICE
143 select OF_BOARD_SETUP
146 select SUPPORT_OF_CONTROL
147 select SYSRESET_CMD_POWEROFF
148 select SYS_CACHE_SHIFT_4
150 select SUPPORT_EXTENSION_SCAN
176 imply UDP_FUNCTION_FASTBOOT
189 imply ACPI_PMC_SANDBOX
201 bool "SuperH architecture"
202 select HAVE_PRIVATE_LIBGCC
203 select SUPPORT_OF_CONTROL
206 bool "x86 architecture"
209 select CREATE_ARCH_SYMLINK
211 select HAVE_ARCH_IOMAP
212 select HAVE_PRIVATE_LIBGCC
215 select SUPPORT_OF_CONTROL
216 select SYS_CACHE_SHIFT_6
218 select USE_PRIVATE_LIBGCC
221 imply HAS_ROM if X86_RESET_VECTOR
224 imply CMD_FPGA_LOADMK
247 imply USB_ETHER_SMSC95XX
252 imply ACPIGEN if !QEMU
253 imply SYSINFO if GENERATE_SMBIOS_TABLE
254 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
256 # Thing to enable for when SPL/TPL are enabled: SPL
259 imply SPL_DRIVERS_MISC
262 imply SPL_LIBCOMMON_SUPPORT
263 imply SPL_LIBGENERIC_SUPPORT
265 imply SPL_SPI_FLASH_SUPPORT
273 imply TPL_DRIVERS_MISC
276 imply TPL_LIBCOMMON_SUPPORT
277 imply TPL_LIBGENERIC_SUPPORT
285 bool "Xtensa architecture"
286 select CREATE_ARCH_SYMLINK
287 select SUPPORT_OF_CONTROL
294 This option should contain the architecture name to build the
295 appropriate arch/<CONFIG_SYS_ARCH> directory.
296 All the architectures should specify this option correctly.
301 This option should contain the CPU name to build the correct
302 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
304 This is optional. For those targets without the CPU directory,
305 leave this option empty.
310 This option should contain the SoC name to build the directory
311 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
313 This is optional. For those targets without the SoC directory,
314 leave this option empty.
319 This option should contain the vendor name of the target board.
321 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
322 directory is compiled.
323 If CONFIG_SYS_BOARD is also set, the sources under
324 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
326 This is optional. For those targets without the vendor directory,
327 leave this option empty.
332 This option should contain the name of the target board.
333 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
334 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
335 whether CONFIG_SYS_VENDOR is set or not.
337 This is optional. For those targets without the board directory,
338 leave this option empty.
340 config SYS_CONFIG_NAME
343 This option should contain the base name of board header file.
344 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
345 should be included from include/config.h.
347 config SYS_DISABLE_DCACHE_OPS
350 This option disables dcache flush and dcache invalidation
351 operations. For example, on coherent systems where cache
352 operatios are not required, enable this option to avoid them.
353 Note that, its up to the individual architectures to implement
358 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
359 default 0xFF000000 if MPC8xx
360 default 0xF0000000 if ARCH_MPC8313
361 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
362 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
363 default SYS_CCSRBAR_DEFAULT
365 Address for the Internal Memory-Mapped Registers (IMMR) window used
366 to configure the features of many Freescale / NXP SoCs.
368 config SKIP_LOWLEVEL_INIT
369 bool "Skip the calls to certain low level initialization functions"
370 depends on ARM || NDS32 || MIPS || RISCV
372 If enabled, then certain low level initializations (like setting up
373 the memory controller) are omitted and/or U-Boot does not relocate
375 Normally this variable MUST NOT be defined. The only exception is
376 when U-Boot is loaded (to RAM) by some other boot loader or by a
377 debugger which performs these initializations itself.
379 config SPL_SKIP_LOWLEVEL_INIT
380 bool "Skip the calls to certain low level initialization functions"
381 depends on SPL && (ARM || NDS32 || MIPS || RISCV)
383 If enabled, then certain low level initializations (like setting up
384 the memory controller) are omitted and/or U-Boot does not relocate
386 Normally this variable MUST NOT be defined. The only exception is
387 when U-Boot is loaded (to RAM) by some other boot loader or by a
388 debugger which performs these initializations itself.
390 config TPL_SKIP_LOWLEVEL_INIT
391 bool "Skip the calls to certain low level initialization functions"
392 depends on SPL && ARM
394 If enabled, then certain low level initializations (like setting up
395 the memory controller) are omitted and/or U-Boot does not relocate
397 Normally this variable MUST NOT be defined. The only exception is
398 when U-Boot is loaded (to RAM) by some other boot loader or by a
399 debugger which performs these initializations itself.
401 config SKIP_LOWLEVEL_INIT_ONLY
402 bool "Skip the call to lowlevel_init during early boot ONLY"
405 This allows just the call to lowlevel_init() to be skipped. The
406 normal CP15 init (such as enabling the instruction cache) is still
409 config SPL_SKIP_LOWLEVEL_INIT_ONLY
410 bool "Skip the call to lowlevel_init during early boot ONLY"
411 depends on SPL && ARM
413 This allows just the call to lowlevel_init() to be skipped. The
414 normal CP15 init (such as enabling the instruction cache) is still
417 config TPL_SKIP_LOWLEVEL_INIT_ONLY
418 bool "Skip the call to lowlevel_init during early boot ONLY"
419 depends on TPL && ARM
421 This allows just the call to lowlevel_init() to be skipped. The
422 normal CP15 init (such as enabling the instruction cache) is still
425 source "arch/arc/Kconfig"
426 source "arch/arm/Kconfig"
427 source "arch/m68k/Kconfig"
428 source "arch/microblaze/Kconfig"
429 source "arch/mips/Kconfig"
430 source "arch/nds32/Kconfig"
431 source "arch/nios2/Kconfig"
432 source "arch/powerpc/Kconfig"
433 source "arch/sandbox/Kconfig"
434 source "arch/sh/Kconfig"
435 source "arch/x86/Kconfig"
436 source "arch/xtensa/Kconfig"
437 source "arch/riscv/Kconfig"