5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config SYS_CACHE_SHIFT_4
14 config SYS_CACHE_SHIFT_5
17 config SYS_CACHE_SHIFT_6
20 config SYS_CACHE_SHIFT_7
23 config SYS_CACHELINE_SIZE
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
32 config LINKER_LIST_ALIGN
35 default 8 if ARM64 || X86
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
44 prompt "Architecture select"
48 bool "ARC architecture"
52 select HAVE_PRIVATE_LIBGCC
53 select SUPPORT_OF_CONTROL
54 select SYS_CACHE_SHIFT_7
58 bool "ARM architecture"
59 select ARCH_SUPPORTS_LTO
60 select CREATE_ARCH_SYMLINK
61 select HAVE_PRIVATE_LIBGCC if !ARM64
63 select SUPPORT_OF_CONTROL
66 bool "M68000 architecture"
67 select HAVE_PRIVATE_LIBGCC
68 select NEEDS_MANUAL_RELOC
69 select SYS_BOOT_GET_CMDLINE
70 select SYS_BOOT_GET_KBD
71 select SYS_CACHE_SHIFT_4
72 select SUPPORT_OF_CONTROL
75 bool "MicroBlaze architecture"
76 select SUPPORT_OF_CONTROL
79 imply SPL_REGMAP if SPL
80 imply SPL_TIMER if SPL
85 bool "MIPS architecture"
86 select HAVE_ARCH_IOREMAP
87 select HAVE_PRIVATE_LIBGCC
88 select SUPPORT_OF_CONTROL
89 select SPL_SEPARATE_BSS if SPL
92 bool "Nios II architecture"
97 select SUPPORT_OF_CONTROL
101 bool "PowerPC architecture"
102 select HAVE_PRIVATE_LIBGCC
103 select SUPPORT_OF_CONTROL
104 select SYS_BOOT_GET_CMDLINE
105 select SYS_BOOT_GET_KBD
108 bool "RISC-V architecture"
109 select CREATE_ARCH_SYMLINK
110 select SUPPORT_OF_CONTROL
113 select SPL_SEPARATE_BSS if SPL
127 imply SPL_LIBCOMMON_SUPPORT
128 imply SPL_LIBGENERIC_SUPPORT
134 select ARCH_SUPPORTS_LTO
135 select BOARD_LATE_INIT
146 select GZIP_COMPRESSED
147 select HAVE_BLOCK_DEVICE
149 select OF_BOARD_SETUP
152 select SUPPORT_OF_CONTROL
153 select SYSRESET_CMD_POWEROFF
154 select SYS_CACHE_SHIFT_4
156 select SUPPORT_EXTENSION_SCAN
180 imply PARTITION_TYPE_GUID
183 imply UDP_FUNCTION_FASTBOOT
196 imply ACPI_PMC_SANDBOX
206 imply GENERATE_ACPI_TABLE
210 bool "SuperH architecture"
211 select HAVE_PRIVATE_LIBGCC
212 select SUPPORT_OF_CONTROL
215 bool "x86 architecture"
218 select CREATE_ARCH_SYMLINK
220 select HAVE_ARCH_IOMAP
221 select HAVE_PRIVATE_LIBGCC
225 select SUPPORT_OF_CONTROL
226 select SYS_CACHE_SHIFT_6
228 select USE_PRIVATE_LIBGCC
231 imply HAS_ROM if X86_RESET_VECTOR
234 imply CMD_FPGA_LOADMK
258 imply USB_ETHER_SMSC95XX
263 imply ACPIGEN if !QEMU && !EFI_APP
264 imply SYSINFO if GENERATE_SMBIOS_TABLE
265 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
268 # Thing to enable for when SPL/TPL are enabled: SPL
271 imply SPL_DRIVERS_MISC
274 imply SPL_LIBCOMMON_SUPPORT
275 imply SPL_LIBGENERIC_SUPPORT
277 imply SPL_SPI_FLASH_SUPPORT
285 imply TPL_DRIVERS_MISC
288 imply TPL_LIBCOMMON_SUPPORT
289 imply TPL_LIBGENERIC_SUPPORT
297 bool "Xtensa architecture"
298 select CREATE_ARCH_SYMLINK
299 select SUPPORT_OF_CONTROL
306 This option should contain the architecture name to build the
307 appropriate arch/<CONFIG_SYS_ARCH> directory.
308 All the architectures should specify this option correctly.
313 This option should contain the CPU name to build the correct
314 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
316 This is optional. For those targets without the CPU directory,
317 leave this option empty.
322 This option should contain the SoC name to build the directory
323 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
325 This is optional. For those targets without the SoC directory,
326 leave this option empty.
331 This option should contain the vendor name of the target board.
333 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
334 directory is compiled.
335 If CONFIG_SYS_BOARD is also set, the sources under
336 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
338 This is optional. For those targets without the vendor directory,
339 leave this option empty.
344 This option should contain the name of the target board.
345 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
346 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
347 whether CONFIG_SYS_VENDOR is set or not.
349 This is optional. For those targets without the board directory,
350 leave this option empty.
352 config SYS_CONFIG_NAME
355 This option should contain the base name of board header file.
356 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
357 should be included from include/config.h.
359 config SYS_DISABLE_DCACHE_OPS
362 This option disables dcache flush and dcache invalidation
363 operations. For example, on coherent systems where cache
364 operatios are not required, enable this option to avoid them.
365 Note that, its up to the individual architectures to implement
369 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
370 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
371 default 0xFF000000 if MPC8xx
372 default 0xF0000000 if ARCH_MPC8313
373 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
374 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
375 default SYS_CCSRBAR_DEFAULT
377 Address for the Internal Memory-Mapped Registers (IMMR) window used
378 to configure the features of many Freescale / NXP SoCs.
380 config SKIP_LOWLEVEL_INIT
381 bool "Skip the calls to certain low level initialization functions"
382 depends on ARM || MIPS || RISCV
384 If enabled, then certain low level initializations (like setting up
385 the memory controller) are omitted and/or U-Boot does not relocate
387 Normally this variable MUST NOT be defined. The only exception is
388 when U-Boot is loaded (to RAM) by some other boot loader or by a
389 debugger which performs these initializations itself.
391 config SPL_SKIP_LOWLEVEL_INIT
392 bool "Skip the calls to certain low level initialization functions"
393 depends on SPL && (ARM || MIPS || RISCV)
395 If enabled, then certain low level initializations (like setting up
396 the memory controller) are omitted and/or U-Boot does not relocate
398 Normally this variable MUST NOT be defined. The only exception is
399 when U-Boot is loaded (to RAM) by some other boot loader or by a
400 debugger which performs these initializations itself.
402 config TPL_SKIP_LOWLEVEL_INIT
403 bool "Skip the calls to certain low level initialization functions"
404 depends on SPL && ARM
406 If enabled, then certain low level initializations (like setting up
407 the memory controller) are omitted and/or U-Boot does not relocate
409 Normally this variable MUST NOT be defined. The only exception is
410 when U-Boot is loaded (to RAM) by some other boot loader or by a
411 debugger which performs these initializations itself.
413 config SKIP_LOWLEVEL_INIT_ONLY
414 bool "Skip the call to lowlevel_init during early boot ONLY"
417 This allows just the call to lowlevel_init() to be skipped. The
418 normal CP15 init (such as enabling the instruction cache) is still
421 config SPL_SKIP_LOWLEVEL_INIT_ONLY
422 bool "Skip the call to lowlevel_init during early boot ONLY"
423 depends on SPL && ARM
425 This allows just the call to lowlevel_init() to be skipped. The
426 normal CP15 init (such as enabling the instruction cache) is still
429 config TPL_SKIP_LOWLEVEL_INIT_ONLY
430 bool "Skip the call to lowlevel_init during early boot ONLY"
431 depends on TPL && ARM
433 This allows just the call to lowlevel_init() to be skipped. The
434 normal CP15 init (such as enabling the instruction cache) is still
437 source "arch/arc/Kconfig"
438 source "arch/arm/Kconfig"
439 source "arch/m68k/Kconfig"
440 source "arch/microblaze/Kconfig"
441 source "arch/mips/Kconfig"
442 source "arch/nios2/Kconfig"
443 source "arch/powerpc/Kconfig"
444 source "arch/sandbox/Kconfig"
445 source "arch/sh/Kconfig"
446 source "arch/x86/Kconfig"
447 source "arch/xtensa/Kconfig"
448 source "arch/riscv/Kconfig"
450 source "board/keymile/Kconfig"
452 if MIPS || MICROBLAZE
455 prompt "Endianness selection"
457 Some MIPS boards can be configured for either little or big endian
458 byte order. These modes require different U-Boot images. In general there
459 is one preferred byteorder for a particular system but some systems are
460 just as commonly used in the one or the other endianness.
462 config SYS_BIG_ENDIAN
464 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
466 config SYS_LITTLE_ENDIAN
468 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE