2 depends on SANDBOX || NDS32
5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config NEEDS_MANUAL_RELOC
14 config SYS_CACHE_SHIFT_4
17 config SYS_CACHE_SHIFT_5
20 config SYS_CACHE_SHIFT_6
23 config SYS_CACHE_SHIFT_7
26 config SYS_CACHELINE_SIZE
28 default 128 if SYS_CACHE_SHIFT_7
29 default 64 if SYS_CACHE_SHIFT_6
30 default 32 if SYS_CACHE_SHIFT_5
31 default 16 if SYS_CACHE_SHIFT_4
35 config LINKER_LIST_ALIGN
38 default 8 if ARM64 || X86
41 Force the each linker list to be aligned to this boundary. This
42 is required if ll_entry_get() is used, since otherwise the linker
43 may add padding into the table, thus breaking it.
44 See linker_lists.rst for full details.
47 prompt "Architecture select"
51 bool "ARC architecture"
55 select HAVE_PRIVATE_LIBGCC
56 select SUPPORT_OF_CONTROL
57 select SYS_CACHE_SHIFT_7
61 bool "ARM architecture"
62 select ARCH_SUPPORTS_LTO
63 select CREATE_ARCH_SYMLINK
64 select HAVE_PRIVATE_LIBGCC if !ARM64
66 select SUPPORT_OF_CONTROL
69 bool "M68000 architecture"
70 select HAVE_PRIVATE_LIBGCC
71 select NEEDS_MANUAL_RELOC
72 select SYS_BOOT_GET_CMDLINE
73 select SYS_BOOT_GET_KBD
74 select SYS_CACHE_SHIFT_4
75 select SUPPORT_OF_CONTROL
78 bool "MicroBlaze architecture"
79 select NEEDS_MANUAL_RELOC
80 select SUPPORT_OF_CONTROL
84 bool "MIPS architecture"
85 select HAVE_ARCH_IOREMAP
86 select HAVE_PRIVATE_LIBGCC
87 select SUPPORT_OF_CONTROL
88 select SPL_SEPARATE_BSS if SPL
91 bool "NDS32 architecture"
92 select SUPPORT_OF_CONTROL
95 bool "Nios II architecture"
100 select SUPPORT_OF_CONTROL
104 bool "PowerPC architecture"
105 select HAVE_PRIVATE_LIBGCC
106 select SUPPORT_OF_CONTROL
107 select SYS_BOOT_GET_CMDLINE
108 select SYS_BOOT_GET_KBD
111 bool "RISC-V architecture"
112 select CREATE_ARCH_SYMLINK
113 select SUPPORT_OF_CONTROL
116 select SPL_SEPARATE_BSS if SPL
130 imply SPL_LIBCOMMON_SUPPORT
131 imply SPL_LIBGENERIC_SUPPORT
137 select ARCH_SUPPORTS_LTO
138 select BOARD_LATE_INIT
149 select GZIP_COMPRESSED
150 select HAVE_BLOCK_DEVICE
152 select OF_BOARD_SETUP
155 select SUPPORT_OF_CONTROL
156 select SYSRESET_CMD_POWEROFF
157 select SYS_CACHE_SHIFT_4
159 select SUPPORT_EXTENSION_SCAN
183 imply PARTITION_TYPE_GUID
186 imply UDP_FUNCTION_FASTBOOT
199 imply ACPI_PMC_SANDBOX
209 imply GENERATE_ACPI_TABLE
213 bool "SuperH architecture"
214 select HAVE_PRIVATE_LIBGCC
215 select SUPPORT_OF_CONTROL
218 bool "x86 architecture"
221 select CREATE_ARCH_SYMLINK
223 select HAVE_ARCH_IOMAP
224 select HAVE_PRIVATE_LIBGCC
228 select SUPPORT_OF_CONTROL
229 select SYS_CACHE_SHIFT_6
231 select USE_PRIVATE_LIBGCC
234 imply HAS_ROM if X86_RESET_VECTOR
237 imply CMD_FPGA_LOADMK
261 imply USB_ETHER_SMSC95XX
266 imply ACPIGEN if !QEMU && !EFI_APP
267 imply SYSINFO if GENERATE_SMBIOS_TABLE
268 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
271 # Thing to enable for when SPL/TPL are enabled: SPL
274 imply SPL_DRIVERS_MISC
277 imply SPL_LIBCOMMON_SUPPORT
278 imply SPL_LIBGENERIC_SUPPORT
280 imply SPL_SPI_FLASH_SUPPORT
288 imply TPL_DRIVERS_MISC
291 imply TPL_LIBCOMMON_SUPPORT
292 imply TPL_LIBGENERIC_SUPPORT
300 bool "Xtensa architecture"
301 select CREATE_ARCH_SYMLINK
302 select SUPPORT_OF_CONTROL
309 This option should contain the architecture name to build the
310 appropriate arch/<CONFIG_SYS_ARCH> directory.
311 All the architectures should specify this option correctly.
316 This option should contain the CPU name to build the correct
317 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
319 This is optional. For those targets without the CPU directory,
320 leave this option empty.
325 This option should contain the SoC name to build the directory
326 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
328 This is optional. For those targets without the SoC directory,
329 leave this option empty.
334 This option should contain the vendor name of the target board.
336 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
337 directory is compiled.
338 If CONFIG_SYS_BOARD is also set, the sources under
339 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
341 This is optional. For those targets without the vendor directory,
342 leave this option empty.
347 This option should contain the name of the target board.
348 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
349 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
350 whether CONFIG_SYS_VENDOR is set or not.
352 This is optional. For those targets without the board directory,
353 leave this option empty.
355 config SYS_CONFIG_NAME
358 This option should contain the base name of board header file.
359 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
360 should be included from include/config.h.
362 config SYS_DISABLE_DCACHE_OPS
365 This option disables dcache flush and dcache invalidation
366 operations. For example, on coherent systems where cache
367 operatios are not required, enable this option to avoid them.
368 Note that, its up to the individual architectures to implement
372 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
373 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
374 default 0xFF000000 if MPC8xx
375 default 0xF0000000 if ARCH_MPC8313
376 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
377 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
378 default SYS_CCSRBAR_DEFAULT
380 Address for the Internal Memory-Mapped Registers (IMMR) window used
381 to configure the features of many Freescale / NXP SoCs.
383 config SKIP_LOWLEVEL_INIT
384 bool "Skip the calls to certain low level initialization functions"
385 depends on ARM || NDS32 || MIPS || RISCV
387 If enabled, then certain low level initializations (like setting up
388 the memory controller) are omitted and/or U-Boot does not relocate
390 Normally this variable MUST NOT be defined. The only exception is
391 when U-Boot is loaded (to RAM) by some other boot loader or by a
392 debugger which performs these initializations itself.
394 config SPL_SKIP_LOWLEVEL_INIT
395 bool "Skip the calls to certain low level initialization functions"
396 depends on SPL && (ARM || NDS32 || MIPS || RISCV)
398 If enabled, then certain low level initializations (like setting up
399 the memory controller) are omitted and/or U-Boot does not relocate
401 Normally this variable MUST NOT be defined. The only exception is
402 when U-Boot is loaded (to RAM) by some other boot loader or by a
403 debugger which performs these initializations itself.
405 config TPL_SKIP_LOWLEVEL_INIT
406 bool "Skip the calls to certain low level initialization functions"
407 depends on SPL && ARM
409 If enabled, then certain low level initializations (like setting up
410 the memory controller) are omitted and/or U-Boot does not relocate
412 Normally this variable MUST NOT be defined. The only exception is
413 when U-Boot is loaded (to RAM) by some other boot loader or by a
414 debugger which performs these initializations itself.
416 config SKIP_LOWLEVEL_INIT_ONLY
417 bool "Skip the call to lowlevel_init during early boot ONLY"
420 This allows just the call to lowlevel_init() to be skipped. The
421 normal CP15 init (such as enabling the instruction cache) is still
424 config SPL_SKIP_LOWLEVEL_INIT_ONLY
425 bool "Skip the call to lowlevel_init during early boot ONLY"
426 depends on SPL && ARM
428 This allows just the call to lowlevel_init() to be skipped. The
429 normal CP15 init (such as enabling the instruction cache) is still
432 config TPL_SKIP_LOWLEVEL_INIT_ONLY
433 bool "Skip the call to lowlevel_init during early boot ONLY"
434 depends on TPL && ARM
436 This allows just the call to lowlevel_init() to be skipped. The
437 normal CP15 init (such as enabling the instruction cache) is still
440 source "arch/arc/Kconfig"
441 source "arch/arm/Kconfig"
442 source "arch/m68k/Kconfig"
443 source "arch/microblaze/Kconfig"
444 source "arch/mips/Kconfig"
445 source "arch/nds32/Kconfig"
446 source "arch/nios2/Kconfig"
447 source "arch/powerpc/Kconfig"
448 source "arch/sandbox/Kconfig"
449 source "arch/sh/Kconfig"
450 source "arch/x86/Kconfig"
451 source "arch/xtensa/Kconfig"
452 source "arch/riscv/Kconfig"
454 source "board/keymile/Kconfig"