5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config NEEDS_MANUAL_RELOC
14 config SYS_CACHE_SHIFT_4
17 config SYS_CACHE_SHIFT_5
20 config SYS_CACHE_SHIFT_6
23 config SYS_CACHE_SHIFT_7
26 config SYS_CACHELINE_SIZE
28 default 128 if SYS_CACHE_SHIFT_7
29 default 64 if SYS_CACHE_SHIFT_6
30 default 32 if SYS_CACHE_SHIFT_5
31 default 16 if SYS_CACHE_SHIFT_4
35 config LINKER_LIST_ALIGN
38 default 8 if ARM64 || X86
41 Force the each linker list to be aligned to this boundary. This
42 is required if ll_entry_get() is used, since otherwise the linker
43 may add padding into the table, thus breaking it.
44 See linker_lists.rst for full details.
47 prompt "Architecture select"
51 bool "ARC architecture"
55 select HAVE_PRIVATE_LIBGCC
56 select SUPPORT_OF_CONTROL
57 select SYS_CACHE_SHIFT_7
61 bool "ARM architecture"
62 select ARCH_SUPPORTS_LTO
63 select CREATE_ARCH_SYMLINK
64 select HAVE_PRIVATE_LIBGCC if !ARM64
66 select SUPPORT_OF_CONTROL
69 bool "M68000 architecture"
70 select HAVE_PRIVATE_LIBGCC
71 select NEEDS_MANUAL_RELOC
72 select SYS_BOOT_GET_CMDLINE
73 select SYS_BOOT_GET_KBD
74 select SYS_CACHE_SHIFT_4
75 select SUPPORT_OF_CONTROL
78 bool "MicroBlaze architecture"
79 select NEEDS_MANUAL_RELOC
80 select SUPPORT_OF_CONTROL
84 bool "MIPS architecture"
85 select HAVE_ARCH_IOREMAP
86 select HAVE_PRIVATE_LIBGCC
87 select SUPPORT_OF_CONTROL
88 select SPL_SEPARATE_BSS if SPL
91 bool "Nios II architecture"
96 select SUPPORT_OF_CONTROL
100 bool "PowerPC architecture"
101 select HAVE_PRIVATE_LIBGCC
102 select SUPPORT_OF_CONTROL
103 select SYS_BOOT_GET_CMDLINE
104 select SYS_BOOT_GET_KBD
107 bool "RISC-V architecture"
108 select CREATE_ARCH_SYMLINK
109 select SUPPORT_OF_CONTROL
112 select SPL_SEPARATE_BSS if SPL
126 imply SPL_LIBCOMMON_SUPPORT
127 imply SPL_LIBGENERIC_SUPPORT
133 select ARCH_SUPPORTS_LTO
134 select BOARD_LATE_INIT
145 select GZIP_COMPRESSED
146 select HAVE_BLOCK_DEVICE
148 select OF_BOARD_SETUP
151 select SUPPORT_OF_CONTROL
152 select SYSRESET_CMD_POWEROFF
153 select SYS_CACHE_SHIFT_4
155 select SUPPORT_EXTENSION_SCAN
179 imply PARTITION_TYPE_GUID
182 imply UDP_FUNCTION_FASTBOOT
195 imply ACPI_PMC_SANDBOX
205 imply GENERATE_ACPI_TABLE
209 bool "SuperH architecture"
210 select HAVE_PRIVATE_LIBGCC
211 select SUPPORT_OF_CONTROL
214 bool "x86 architecture"
217 select CREATE_ARCH_SYMLINK
219 select HAVE_ARCH_IOMAP
220 select HAVE_PRIVATE_LIBGCC
224 select SUPPORT_OF_CONTROL
225 select SYS_CACHE_SHIFT_6
227 select USE_PRIVATE_LIBGCC
230 imply HAS_ROM if X86_RESET_VECTOR
233 imply CMD_FPGA_LOADMK
257 imply USB_ETHER_SMSC95XX
262 imply ACPIGEN if !QEMU && !EFI_APP
263 imply SYSINFO if GENERATE_SMBIOS_TABLE
264 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
267 # Thing to enable for when SPL/TPL are enabled: SPL
270 imply SPL_DRIVERS_MISC
273 imply SPL_LIBCOMMON_SUPPORT
274 imply SPL_LIBGENERIC_SUPPORT
276 imply SPL_SPI_FLASH_SUPPORT
284 imply TPL_DRIVERS_MISC
287 imply TPL_LIBCOMMON_SUPPORT
288 imply TPL_LIBGENERIC_SUPPORT
296 bool "Xtensa architecture"
297 select CREATE_ARCH_SYMLINK
298 select SUPPORT_OF_CONTROL
305 This option should contain the architecture name to build the
306 appropriate arch/<CONFIG_SYS_ARCH> directory.
307 All the architectures should specify this option correctly.
312 This option should contain the CPU name to build the correct
313 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
315 This is optional. For those targets without the CPU directory,
316 leave this option empty.
321 This option should contain the SoC name to build the directory
322 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
324 This is optional. For those targets without the SoC directory,
325 leave this option empty.
330 This option should contain the vendor name of the target board.
332 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
333 directory is compiled.
334 If CONFIG_SYS_BOARD is also set, the sources under
335 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
337 This is optional. For those targets without the vendor directory,
338 leave this option empty.
343 This option should contain the name of the target board.
344 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
345 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
346 whether CONFIG_SYS_VENDOR is set or not.
348 This is optional. For those targets without the board directory,
349 leave this option empty.
351 config SYS_CONFIG_NAME
354 This option should contain the base name of board header file.
355 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
356 should be included from include/config.h.
358 config SYS_DISABLE_DCACHE_OPS
361 This option disables dcache flush and dcache invalidation
362 operations. For example, on coherent systems where cache
363 operatios are not required, enable this option to avoid them.
364 Note that, its up to the individual architectures to implement
368 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
369 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
370 default 0xFF000000 if MPC8xx
371 default 0xF0000000 if ARCH_MPC8313
372 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
373 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
374 default SYS_CCSRBAR_DEFAULT
376 Address for the Internal Memory-Mapped Registers (IMMR) window used
377 to configure the features of many Freescale / NXP SoCs.
379 config SKIP_LOWLEVEL_INIT
380 bool "Skip the calls to certain low level initialization functions"
381 depends on ARM || MIPS || RISCV
383 If enabled, then certain low level initializations (like setting up
384 the memory controller) are omitted and/or U-Boot does not relocate
386 Normally this variable MUST NOT be defined. The only exception is
387 when U-Boot is loaded (to RAM) by some other boot loader or by a
388 debugger which performs these initializations itself.
390 config SPL_SKIP_LOWLEVEL_INIT
391 bool "Skip the calls to certain low level initialization functions"
392 depends on SPL && (ARM || MIPS || RISCV)
394 If enabled, then certain low level initializations (like setting up
395 the memory controller) are omitted and/or U-Boot does not relocate
397 Normally this variable MUST NOT be defined. The only exception is
398 when U-Boot is loaded (to RAM) by some other boot loader or by a
399 debugger which performs these initializations itself.
401 config TPL_SKIP_LOWLEVEL_INIT
402 bool "Skip the calls to certain low level initialization functions"
403 depends on SPL && ARM
405 If enabled, then certain low level initializations (like setting up
406 the memory controller) are omitted and/or U-Boot does not relocate
408 Normally this variable MUST NOT be defined. The only exception is
409 when U-Boot is loaded (to RAM) by some other boot loader or by a
410 debugger which performs these initializations itself.
412 config SKIP_LOWLEVEL_INIT_ONLY
413 bool "Skip the call to lowlevel_init during early boot ONLY"
416 This allows just the call to lowlevel_init() to be skipped. The
417 normal CP15 init (such as enabling the instruction cache) is still
420 config SPL_SKIP_LOWLEVEL_INIT_ONLY
421 bool "Skip the call to lowlevel_init during early boot ONLY"
422 depends on SPL && ARM
424 This allows just the call to lowlevel_init() to be skipped. The
425 normal CP15 init (such as enabling the instruction cache) is still
428 config TPL_SKIP_LOWLEVEL_INIT_ONLY
429 bool "Skip the call to lowlevel_init during early boot ONLY"
430 depends on TPL && ARM
432 This allows just the call to lowlevel_init() to be skipped. The
433 normal CP15 init (such as enabling the instruction cache) is still
436 source "arch/arc/Kconfig"
437 source "arch/arm/Kconfig"
438 source "arch/m68k/Kconfig"
439 source "arch/microblaze/Kconfig"
440 source "arch/mips/Kconfig"
441 source "arch/nios2/Kconfig"
442 source "arch/powerpc/Kconfig"
443 source "arch/sandbox/Kconfig"
444 source "arch/sh/Kconfig"
445 source "arch/x86/Kconfig"
446 source "arch/xtensa/Kconfig"
447 source "arch/riscv/Kconfig"
449 source "board/keymile/Kconfig"