2 depends on SANDBOX || NDS32
5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config NEEDS_MANUAL_RELOC
14 config SYS_CACHE_SHIFT_4
17 config SYS_CACHE_SHIFT_5
20 config SYS_CACHE_SHIFT_6
23 config SYS_CACHE_SHIFT_7
26 config SYS_CACHELINE_SIZE
28 default 128 if SYS_CACHE_SHIFT_7
29 default 64 if SYS_CACHE_SHIFT_6
30 default 32 if SYS_CACHE_SHIFT_5
31 default 16 if SYS_CACHE_SHIFT_4
35 config LINKER_LIST_ALIGN
38 default 8 if ARM64 || X86
41 Force the each linker list to be aligned to this boundary. This
42 is required if ll_entry_get() is used, since otherwise the linker
43 may add padding into the table, thus breaking it.
44 See linker_lists.rst for full details.
47 prompt "Architecture select"
51 bool "ARC architecture"
55 select HAVE_PRIVATE_LIBGCC
56 select SUPPORT_OF_CONTROL
57 select SYS_CACHE_SHIFT_7
61 bool "ARM architecture"
62 select ARCH_SUPPORTS_LTO
63 select CREATE_ARCH_SYMLINK
64 select HAVE_PRIVATE_LIBGCC if !ARM64
65 select SUPPORT_OF_CONTROL
68 bool "M68000 architecture"
69 select HAVE_PRIVATE_LIBGCC
70 select NEEDS_MANUAL_RELOC
71 select SYS_BOOT_GET_CMDLINE
72 select SYS_BOOT_GET_KBD
73 select SYS_CACHE_SHIFT_4
74 select SUPPORT_OF_CONTROL
77 bool "MicroBlaze architecture"
78 select NEEDS_MANUAL_RELOC
79 select SUPPORT_OF_CONTROL
83 bool "MIPS architecture"
84 select HAVE_ARCH_IOREMAP
85 select HAVE_PRIVATE_LIBGCC
86 select SUPPORT_OF_CONTROL
89 bool "NDS32 architecture"
90 select SUPPORT_OF_CONTROL
93 bool "Nios II architecture"
97 select SUPPORT_OF_CONTROL
101 bool "PowerPC architecture"
102 select HAVE_PRIVATE_LIBGCC
103 select SUPPORT_OF_CONTROL
104 select SYS_BOOT_GET_CMDLINE
105 select SYS_BOOT_GET_KBD
108 bool "RISC-V architecture"
109 select CREATE_ARCH_SYMLINK
110 select SUPPORT_OF_CONTROL
125 imply SPL_LIBCOMMON_SUPPORT
126 imply SPL_LIBGENERIC_SUPPORT
132 select ARCH_SUPPORTS_LTO
133 select BOARD_LATE_INIT
144 select GZIP_COMPRESSED
145 select HAVE_BLOCK_DEVICE
147 select OF_BOARD_SETUP
150 select SUPPORT_OF_CONTROL
151 select SYSRESET_CMD_POWEROFF
152 select SYS_CACHE_SHIFT_4
154 select SUPPORT_EXTENSION_SCAN
180 imply UDP_FUNCTION_FASTBOOT
193 imply ACPI_PMC_SANDBOX
205 bool "SuperH architecture"
206 select HAVE_PRIVATE_LIBGCC
207 select SUPPORT_OF_CONTROL
210 bool "x86 architecture"
213 select CREATE_ARCH_SYMLINK
215 select HAVE_ARCH_IOMAP
216 select HAVE_PRIVATE_LIBGCC
219 select SUPPORT_OF_CONTROL
220 select SYS_CACHE_SHIFT_6
222 select USE_PRIVATE_LIBGCC
225 imply HAS_ROM if X86_RESET_VECTOR
228 imply CMD_FPGA_LOADMK
251 imply USB_ETHER_SMSC95XX
256 imply ACPIGEN if !QEMU
257 imply SYSINFO if GENERATE_SMBIOS_TABLE
258 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
260 # Thing to enable for when SPL/TPL are enabled: SPL
263 imply SPL_DRIVERS_MISC
266 imply SPL_LIBCOMMON_SUPPORT
267 imply SPL_LIBGENERIC_SUPPORT
269 imply SPL_SPI_FLASH_SUPPORT
277 imply TPL_DRIVERS_MISC
280 imply TPL_LIBCOMMON_SUPPORT
281 imply TPL_LIBGENERIC_SUPPORT
289 bool "Xtensa architecture"
290 select CREATE_ARCH_SYMLINK
291 select SUPPORT_OF_CONTROL
298 This option should contain the architecture name to build the
299 appropriate arch/<CONFIG_SYS_ARCH> directory.
300 All the architectures should specify this option correctly.
305 This option should contain the CPU name to build the correct
306 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
308 This is optional. For those targets without the CPU directory,
309 leave this option empty.
314 This option should contain the SoC name to build the directory
315 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
317 This is optional. For those targets without the SoC directory,
318 leave this option empty.
323 This option should contain the vendor name of the target board.
325 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
326 directory is compiled.
327 If CONFIG_SYS_BOARD is also set, the sources under
328 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
330 This is optional. For those targets without the vendor directory,
331 leave this option empty.
336 This option should contain the name of the target board.
337 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
338 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
339 whether CONFIG_SYS_VENDOR is set or not.
341 This is optional. For those targets without the board directory,
342 leave this option empty.
344 config SYS_CONFIG_NAME
347 This option should contain the base name of board header file.
348 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
349 should be included from include/config.h.
351 config SYS_DISABLE_DCACHE_OPS
354 This option disables dcache flush and dcache invalidation
355 operations. For example, on coherent systems where cache
356 operatios are not required, enable this option to avoid them.
357 Note that, its up to the individual architectures to implement
362 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
363 default 0xFF000000 if MPC8xx
364 default 0xF0000000 if ARCH_MPC8313
365 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
366 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
367 default SYS_CCSRBAR_DEFAULT
369 Address for the Internal Memory-Mapped Registers (IMMR) window used
370 to configure the features of many Freescale / NXP SoCs.
372 config SKIP_LOWLEVEL_INIT
373 bool "Skip the calls to certain low level initialization functions"
374 depends on ARM || NDS32 || MIPS || RISCV
376 If enabled, then certain low level initializations (like setting up
377 the memory controller) are omitted and/or U-Boot does not relocate
379 Normally this variable MUST NOT be defined. The only exception is
380 when U-Boot is loaded (to RAM) by some other boot loader or by a
381 debugger which performs these initializations itself.
383 config SPL_SKIP_LOWLEVEL_INIT
384 bool "Skip the calls to certain low level initialization functions"
385 depends on SPL && (ARM || NDS32 || MIPS || RISCV)
387 If enabled, then certain low level initializations (like setting up
388 the memory controller) are omitted and/or U-Boot does not relocate
390 Normally this variable MUST NOT be defined. The only exception is
391 when U-Boot is loaded (to RAM) by some other boot loader or by a
392 debugger which performs these initializations itself.
394 config TPL_SKIP_LOWLEVEL_INIT
395 bool "Skip the calls to certain low level initialization functions"
396 depends on SPL && ARM
398 If enabled, then certain low level initializations (like setting up
399 the memory controller) are omitted and/or U-Boot does not relocate
401 Normally this variable MUST NOT be defined. The only exception is
402 when U-Boot is loaded (to RAM) by some other boot loader or by a
403 debugger which performs these initializations itself.
405 config SKIP_LOWLEVEL_INIT_ONLY
406 bool "Skip the call to lowlevel_init during early boot ONLY"
409 This allows just the call to lowlevel_init() to be skipped. The
410 normal CP15 init (such as enabling the instruction cache) is still
413 config SPL_SKIP_LOWLEVEL_INIT_ONLY
414 bool "Skip the call to lowlevel_init during early boot ONLY"
415 depends on SPL && ARM
417 This allows just the call to lowlevel_init() to be skipped. The
418 normal CP15 init (such as enabling the instruction cache) is still
421 config TPL_SKIP_LOWLEVEL_INIT_ONLY
422 bool "Skip the call to lowlevel_init during early boot ONLY"
423 depends on TPL && ARM
425 This allows just the call to lowlevel_init() to be skipped. The
426 normal CP15 init (such as enabling the instruction cache) is still
429 source "arch/arc/Kconfig"
430 source "arch/arm/Kconfig"
431 source "arch/m68k/Kconfig"
432 source "arch/microblaze/Kconfig"
433 source "arch/mips/Kconfig"
434 source "arch/nds32/Kconfig"
435 source "arch/nios2/Kconfig"
436 source "arch/powerpc/Kconfig"
437 source "arch/sandbox/Kconfig"
438 source "arch/sh/Kconfig"
439 source "arch/x86/Kconfig"
440 source "arch/xtensa/Kconfig"
441 source "arch/riscv/Kconfig"