5 config CREATE_ARCH_SYMLINK
8 config HAVE_ARCH_IOREMAP
11 config SYS_CACHE_SHIFT_4
14 config SYS_CACHE_SHIFT_5
17 config SYS_CACHE_SHIFT_6
20 config SYS_CACHE_SHIFT_7
23 config SYS_CACHELINE_SIZE
25 default 128 if SYS_CACHE_SHIFT_7
26 default 64 if SYS_CACHE_SHIFT_6
27 default 32 if SYS_CACHE_SHIFT_5
28 default 16 if SYS_CACHE_SHIFT_4
32 config LINKER_LIST_ALIGN
35 default 8 if ARM64 || X86
38 Force the each linker list to be aligned to this boundary. This
39 is required if ll_entry_get() is used, since otherwise the linker
40 may add padding into the table, thus breaking it.
41 See linker_lists.rst for full details.
44 prompt "Architecture select"
48 bool "ARC architecture"
52 select HAVE_PRIVATE_LIBGCC
53 select SUPPORT_OF_CONTROL
54 select SYS_CACHE_SHIFT_7
58 bool "ARM architecture"
59 select ARCH_SUPPORTS_LTO
60 select CREATE_ARCH_SYMLINK
61 select HAVE_PRIVATE_LIBGCC if !ARM64
63 select SUPPORT_OF_CONTROL
66 bool "M68000 architecture"
67 select HAVE_PRIVATE_LIBGCC
68 select NEEDS_MANUAL_RELOC
69 select SYS_BOOT_GET_CMDLINE
70 select SYS_BOOT_GET_KBD
71 select SYS_CACHE_SHIFT_4
72 select SUPPORT_OF_CONTROL
75 bool "MicroBlaze architecture"
76 select SUPPORT_OF_CONTROL
80 bool "MIPS architecture"
81 select HAVE_ARCH_IOREMAP
82 select HAVE_PRIVATE_LIBGCC
83 select SUPPORT_OF_CONTROL
84 select SPL_SEPARATE_BSS if SPL
87 bool "Nios II architecture"
92 select SUPPORT_OF_CONTROL
96 bool "PowerPC architecture"
97 select HAVE_PRIVATE_LIBGCC
98 select SUPPORT_OF_CONTROL
99 select SYS_BOOT_GET_CMDLINE
100 select SYS_BOOT_GET_KBD
103 bool "RISC-V architecture"
104 select CREATE_ARCH_SYMLINK
105 select SUPPORT_OF_CONTROL
108 select SPL_SEPARATE_BSS if SPL
122 imply SPL_LIBCOMMON_SUPPORT
123 imply SPL_LIBGENERIC_SUPPORT
129 select ARCH_SUPPORTS_LTO
130 select BOARD_LATE_INIT
141 select GZIP_COMPRESSED
142 select HAVE_BLOCK_DEVICE
144 select OF_BOARD_SETUP
147 select SUPPORT_OF_CONTROL
148 select SYSRESET_CMD_POWEROFF
149 select SYS_CACHE_SHIFT_4
151 select SUPPORT_EXTENSION_SCAN
175 imply PARTITION_TYPE_GUID
178 imply UDP_FUNCTION_FASTBOOT
191 imply ACPI_PMC_SANDBOX
201 imply GENERATE_ACPI_TABLE
205 bool "SuperH architecture"
206 select HAVE_PRIVATE_LIBGCC
207 select SUPPORT_OF_CONTROL
210 bool "x86 architecture"
213 select CREATE_ARCH_SYMLINK
215 select HAVE_ARCH_IOMAP
216 select HAVE_PRIVATE_LIBGCC
220 select SUPPORT_OF_CONTROL
221 select SYS_CACHE_SHIFT_6
223 select USE_PRIVATE_LIBGCC
226 imply HAS_ROM if X86_RESET_VECTOR
229 imply CMD_FPGA_LOADMK
253 imply USB_ETHER_SMSC95XX
258 imply ACPIGEN if !QEMU && !EFI_APP
259 imply SYSINFO if GENERATE_SMBIOS_TABLE
260 imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
263 # Thing to enable for when SPL/TPL are enabled: SPL
266 imply SPL_DRIVERS_MISC
269 imply SPL_LIBCOMMON_SUPPORT
270 imply SPL_LIBGENERIC_SUPPORT
272 imply SPL_SPI_FLASH_SUPPORT
280 imply TPL_DRIVERS_MISC
283 imply TPL_LIBCOMMON_SUPPORT
284 imply TPL_LIBGENERIC_SUPPORT
292 bool "Xtensa architecture"
293 select CREATE_ARCH_SYMLINK
294 select SUPPORT_OF_CONTROL
301 This option should contain the architecture name to build the
302 appropriate arch/<CONFIG_SYS_ARCH> directory.
303 All the architectures should specify this option correctly.
308 This option should contain the CPU name to build the correct
309 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU> directory.
311 This is optional. For those targets without the CPU directory,
312 leave this option empty.
317 This option should contain the SoC name to build the directory
318 arch/<CONFIG_SYS_ARCH>/cpu/<CONFIG_SYS_CPU>/<CONFIG_SYS_SOC>.
320 This is optional. For those targets without the SoC directory,
321 leave this option empty.
326 This option should contain the vendor name of the target board.
328 board/<CONFIG_SYS_VENDOR>/common/Makefile exists, the vendor common
329 directory is compiled.
330 If CONFIG_SYS_BOARD is also set, the sources under
331 board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD> directory are compiled.
333 This is optional. For those targets without the vendor directory,
334 leave this option empty.
339 This option should contain the name of the target board.
340 If it is set, either board/<CONFIG_SYS_VENDOR>/<CONFIG_SYS_BOARD>
341 or board/<CONFIG_SYS_BOARD> directory is compiled depending on
342 whether CONFIG_SYS_VENDOR is set or not.
344 This is optional. For those targets without the board directory,
345 leave this option empty.
347 config SYS_CONFIG_NAME
350 This option should contain the base name of board header file.
351 The header file include/configs/<CONFIG_SYS_CONFIG_NAME>.h
352 should be included from include/config.h.
354 config SYS_DISABLE_DCACHE_OPS
357 This option disables dcache flush and dcache invalidation
358 operations. For example, on coherent systems where cache
359 operatios are not required, enable this option to avoid them.
360 Note that, its up to the individual architectures to implement
364 hex "Address for the Internal Memory-Mapped Registers (IMMR) window"
365 depends on PPC || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A
366 default 0xFF000000 if MPC8xx
367 default 0xF0000000 if ARCH_MPC8313
368 default 0xE0000000 if MPC83xx && !ARCH_MPC8313
369 default 0x01000000 if ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
370 default SYS_CCSRBAR_DEFAULT
372 Address for the Internal Memory-Mapped Registers (IMMR) window used
373 to configure the features of many Freescale / NXP SoCs.
375 config SKIP_LOWLEVEL_INIT
376 bool "Skip the calls to certain low level initialization functions"
377 depends on ARM || MIPS || RISCV
379 If enabled, then certain low level initializations (like setting up
380 the memory controller) are omitted and/or U-Boot does not relocate
382 Normally this variable MUST NOT be defined. The only exception is
383 when U-Boot is loaded (to RAM) by some other boot loader or by a
384 debugger which performs these initializations itself.
386 config SPL_SKIP_LOWLEVEL_INIT
387 bool "Skip the calls to certain low level initialization functions"
388 depends on SPL && (ARM || MIPS || RISCV)
390 If enabled, then certain low level initializations (like setting up
391 the memory controller) are omitted and/or U-Boot does not relocate
393 Normally this variable MUST NOT be defined. The only exception is
394 when U-Boot is loaded (to RAM) by some other boot loader or by a
395 debugger which performs these initializations itself.
397 config TPL_SKIP_LOWLEVEL_INIT
398 bool "Skip the calls to certain low level initialization functions"
399 depends on SPL && ARM
401 If enabled, then certain low level initializations (like setting up
402 the memory controller) are omitted and/or U-Boot does not relocate
404 Normally this variable MUST NOT be defined. The only exception is
405 when U-Boot is loaded (to RAM) by some other boot loader or by a
406 debugger which performs these initializations itself.
408 config SKIP_LOWLEVEL_INIT_ONLY
409 bool "Skip the call to lowlevel_init during early boot ONLY"
412 This allows just the call to lowlevel_init() to be skipped. The
413 normal CP15 init (such as enabling the instruction cache) is still
416 config SPL_SKIP_LOWLEVEL_INIT_ONLY
417 bool "Skip the call to lowlevel_init during early boot ONLY"
418 depends on SPL && ARM
420 This allows just the call to lowlevel_init() to be skipped. The
421 normal CP15 init (such as enabling the instruction cache) is still
424 config TPL_SKIP_LOWLEVEL_INIT_ONLY
425 bool "Skip the call to lowlevel_init during early boot ONLY"
426 depends on TPL && ARM
428 This allows just the call to lowlevel_init() to be skipped. The
429 normal CP15 init (such as enabling the instruction cache) is still
432 source "arch/arc/Kconfig"
433 source "arch/arm/Kconfig"
434 source "arch/m68k/Kconfig"
435 source "arch/microblaze/Kconfig"
436 source "arch/mips/Kconfig"
437 source "arch/nios2/Kconfig"
438 source "arch/powerpc/Kconfig"
439 source "arch/sandbox/Kconfig"
440 source "arch/sh/Kconfig"
441 source "arch/x86/Kconfig"
442 source "arch/xtensa/Kconfig"
443 source "arch/riscv/Kconfig"
445 source "board/keymile/Kconfig"
447 if MIPS || MICROBLAZE
450 prompt "Endianness selection"
452 Some MIPS boards can be configured for either little or big endian
453 byte order. These modes require different U-Boot images. In general there
454 is one preferred byteorder for a particular system but some systems are
455 just as commonly used in the one or the other endianness.
457 config SYS_BIG_ENDIAN
459 depends on (SUPPORTS_BIG_ENDIAN && MIPS) || MICROBLAZE
461 config SYS_LITTLE_ENDIAN
463 depends on (SUPPORTS_LITTLE_ENDIAN && MIPS) || MICROBLAZE